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«A 32-bit DSP Ultra Low Power accelerator » E. Beigné [email protected] CEA LETI MINATEC, Grenoble, France www.cea.fr & Low power SOC challenges : Energy Efficiency Fine-Grain AVFS solutions FDSOI technology brings a new actuator Fine-Grain AVFS with Body Biasing Silicon results in FDSOI 28nm Future IoT needs and Conclusions & © CEA. All rights reserved Diego Puschini | ICDV 2014 |2 Low Power le SoC challenges Cliquez pour modifier style du titre Technology Application Process variability Applicative flexibility Unpredictable load Aging Multi-Core Architectures Architecture Massively parallel architectures & © CEA. All rights reserved 2015 COOL Chips– E. Beigné |3 Energy Efficiency Cliquez pour modifier le style du titre Power consumption management follows two objectives today : Reduce the overall power or Increase the global energetic efficiency Performance does no more only mean ‘High frequency’ but also ‘Low power’ High Performance/ Low Power trade-off difficult to reach Mimimum power consumed at a given frequency & © CEA. All rights reserved 2015 COOL Chips– E. Beigné |4 Low power SOC challenges : Energy Efficiency Fine-Grain AVFS solutions FDSOI technology brings a new actuator Fine-Grain AVFS with Body Biasing Silicon results in FDSOI 28nm Future IoT needs and Conclusions & © CEA. All rights reserved Diego Puschini | ICDV 2014 |5 Dynamic & Frequency Scaling Cliquez pourVoltage modifier le style du titre Power Domain DVFS for power-performance trade-off V regulator Ctrl. F generator Core ∝ ∝ 1 ∙ ∙ ∙ ° ∝ ∙ Voltage & " Vdd & F are adjusted to ensure performance at minimum consumption Power Frequency ! Frequency © CEA. All rights reserved 2015 COOL Chips– E. Beigné |6 Adaptive & Frequency Scaling Cliquez pourVoltage modifier le style du titre Power Domain AVFS approach Fmax & PVT monitors Data fusion & adjustment V regulator Ctrl. F generator Core ∝ Adjustment Data fusion ∝ 1 ∙ ∙ ∙ ° ∝ ∙ Frequency ! " F is adjusted to reach Fmax for the given conditions (Vdd, T°…) Voltage & © CEA. All rights reserved 2015 COOL Chips– E. Beigné |7 Low power SOC challenges : Energy Efficiency Fine-Grain AVFS solutions FDSOI technology brings a new actuator Fine-Grain AVFS with Body Biasing Silicon results in FDSOI 28nm Future IoT needs and Conclusions & © CEA. All rights reserved Diego Puschini | ICDV 2014 |8 Body Biasing Multi-Vle UTBBdu FD-SOI T in Cliquez pourand modifier style titre RVT VBNMOS Bulk-like Well NMOS PMOS VBPMOS VBPMOS -300mV p-Well 3V VBNMOS n-Well -3V 300mV GND LVT VBPMOS Flip-Well NMOS PMOS VBNMOS VBPMOS -3V 300mV VBNMOS n-Well p-Well -300mV 3V GND [Flatresse et al. ISSCC 2013] & © CEA. All rights reserved 2015 COOL Chips– E. Beigné |9 Low power SOC challenges : Energy Efficiency Fine-Grain AVFS solutions FDSOI technology brings a new actuator Fine-Grain AVFS with Body Biasing Silicon results in FDSOI 28nm Future IoT needs and Conclusions & © CEA. All rights reserved Diego Puschini | ICDV 2014 | 10 AVFS with Adaptive Biasing Cliquez pour modifier le Body style du titre ABB in FD-SOI Power Domain Ultra Wide Voltage Range (UWVR) Body Bias increases efficiency V regulator Ctrl. F generator Core BB generator Adjustment ∝ Data fusion ∝ 1 Frequency UWVR ∙ ∙ ° ∝ ∙ ! " Eff. 0 1.3V Vdd & Vbb should be chosen to minimize consumption Voltage & ∙ Source: http://www.st.com/web/en/about_st/learn_fd-soi.html © CEA. All rights reserved 2015 COOL Chips– E. Beigné | 11 grain le AVFS with ABB Cliquez pourFine modifier style du titre Power Domain V regulator Ctrl. F generator Core Power Domain BB generator Adjustment Power Domain Fine grain requires per core actuators Low area/complexity enable fine grain AVFS with ABB Concession on performance Data fusion Power Domain Granularity in complex SoC Power Domain Speed Discretization Switching cost Efficiency Example of VDD discretization Frequency Power Domain Power Domain Actuators’ constraints to be considered for management policy Voltage & © CEA. All rights reserved 2015 COOL Chips– E. Beigné | 12 Summarizing AVFS with ABB indu FD-SOI Cliquez pour modifier le style titre VDD generator Fmax monitor low area for fine grain for adaptive approach Power Domain V regulator Ctrl. F generator Core T° monitor BB generator Adjustment for adaptive approach Data fusion F generator VBB generator low area for fine grain & to improve efficiency © CEA. All rights reserved 2015 COOL Chips– E. Beigné | 13 Something new for AVFS power management Cliquez pour modifier le style du titre Dynamic power management today FD-SOI context (UWVR, increased efficiency) New opportunity: extended Body Bias range Source: http://www.st.com/web/en/about_st/learn_fd-soi.html Power Domain 3 on-chip constrained actuators Known target performance (Ftarget) n Power Modes (PM) available V regulator Ctrl. F generator Core BB generator Adjustment Data fusion F P Which configuration to minimize power? taking into account actuators’ constraints Vdd ↗ Vbb & F © CEA. All rights reserved 2015 COOL Chips– E. Beigné | 14 Low power SOC challenges : Energy Efficiency Fine-Grain AVFS solutions FDSOI technology brings a new actuator Fine-Grain AVFS with Body Biasing Silicon results in FDSOI 28nm Future IoT needs and Conclusions & © CEA. All rights reserved Diego Puschini | ICDV 2014 | 15 architecture Cliquez pour modifierDSP le style du titre CODA Serial Interface & Mux Bit Trunc Adder 40b TMFLT-R Input/Output RAM 2x1Kx32 Cordics + Divider MAC Bit Bit Extension Extension Shift Reg. Mux Prog SRAM Data SRAM Address Gen. 32b Multiplier Address Gen. Register Array 2Read-1Write Ports 64x32b 32bit VLIW DSP core - V/F domain Control Comp/Select TMFLT-S TMFLT-S TMFLT-S TMFLT-S TMFLT-S TMFLT-S PLL © CEA. All rights reserved Variability Power Control (CVP) 2015 COOL Chips– E. Beigné | 16 Micrograph Cliquez pour modifierChip le style du titre Technology STMicro Transistors Core area & UTBB FDSOI 28 nm Flip-Well (LVT) L=24nm 1 mm² DSP benchmark VDD range 0.397V-1.3V VBB range 0V/±2V Wilson, R et al., "A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking," International Solid-State Circuits Conference (ISSCC), pp. 452-453, February 2014 E. Beigné, et al., JSSC 2015 © CEA. All rights reserved FFT 1024 2015 COOL Chips– E. Beigné | 17 Power distribution – Body Biasing Cliquez pour modifier le style du titre Including all biasing voltages Thin VBB power stripes Body-Biasing Supplied through specific IOs (± 2V) & © CEA. All rights reserved 2015 COOL Chips– E. Beigné | 18 sub-set Cliquez pourOptimized modifier lelibrary style du titre Use of available standard cells optimized for low voltage: Extend the subset to the Wide Voltage Range Gate length modulation done through Poly Biasing Keep the power-delay optimal cells in UWVR Cells are characterized over [0.275V-1.4V] VDD range and [0V- (±2V)] VBB range & © CEA. All rights reserved 2015 COOL Chips– E. Beigné | 19 Optimized Pulsed-latch FF Cliquez pour modifier le style du titre Transmission-Gate Pulsed Latches A latch and a pulse generator Same behavior as a conventional Master-Slave FF Proved to be the most energy-efficient in a large portion of the design spacee D-to-Q Egy/cycle Area (ps) (fJ) (µm²) ST C2MOS 117.5 6 4,41 ST SA 46.5 (- 60 %) 12.5 (+ 208 %) 6,85 (+ 55 %) TGPLMuxScan 30.5 (- 74 %) 7.2 (+ 20 %) 4,73 (+ 7 %) TGPLMuxClk 26 (- 78 %) 9.1 (+ 56 %) 5,06 (+ 14 %) & © CEA. All rights reserved 2015 COOL Chips– E. Beigné | 20 Timing margins reduction in UWVR : FMAX tracking Cliquez pour modifier le style du titre Design in typical corner case instead of worst case approach Need to compensate for PVT variations in UWVR Reduce energy per operation … or increase clock frequency Track the optimal Frequency/Voltage/Biasing point Real maximum frequency is not available Functional in the UWVR / Low area and power overhead Two complementary solutions proposed on-chip Replica path based CODA (ClOning DAta paths) Timing slack sensor based TMFLT (TiMing FauLT) & © CEA. All rights reserved 2015 COOL Chips– E. Beigné | 21 Fmax tracking (solutionle 1) style : Pathdu Cloning Cliquez pour modifier titre • 16 paths cloned at 1V signoff • Correlation between FMAX and frequency predictions – 5 slots into 21 dies @ 1V & 25°C (+4/-3% accuracy) – 1 slot into 21 dies @ [0.8V-1.3V] & 25°C (6% accuracy) – Not intrusive / Need complementary solution in UWVR & © CEA. All rights reserved 2015 COOL Chips– E. Beigné | 22 Fmax tracking (solution 2) : le Slack Monitoring Cliquez pour modifier style du titre 1 TMFLT-Ring 128 TMFLT-Sensors • Analyze the registers slack time • 300ps detection window • Programmable replica path • Time-to-digital measurement Reset_n SEL 31 RAM E FF FF Prog. delay TMFLT Warning EN Sensor Detectio n window CLK CG reg2 FF Clock tree & reg1 0 0 0 1 1 1 SIG © CEA. All rights reserved slack time 2015 COOL Chips– E. Beigné | 23 Fmax tracking (solution 2) : Slack Monitoring Cliquez pour modifier le style du titre • Frequency estimation error compared to FMAX – Error of ±4% at 1V • Compared to worst case PVT corner (3σ) approach without FMAX tracking: frequency error (%) 8 – Energy gain of 40.6% @ 0.6V 6 – Frequency gain of 24% @1V 4 2 0 -2 -4 21 dies -6 600 700 800 900 1000 1100 1200 1300 Power Supply (mV) & © CEA. All rights reserved 2015 COOL Chips– E. Beigné | 24 Low power SOC challenges : Energy Efficiency Fine-Grain AVFS solutions FDSOI technology brings a new actuator Fine-Grain AVFS with Body Biasing Silicon results in FDSOI 28nm Future IoT needs and Conclusions & © CEA. All rights reserved Diego Puschini | ICDV 2014 | 25 DSP speed performance measurements Cliquez pour modifier le style du titre 3000 Frequency (MHz) 2500 2000 1500 [email protected] Boost 0mV FBB 0V Boost 500mV FBB 0.5V Boost 1000mV FBB 1.0V FBB 1.5V Boost 1500mV FBB 2.0V Boost 2000mV 1GHz@570mV 1000 500 0 300 400 500 460MHz@397mV 600 700 800 900 1000 1100 1200 1300 VDD voltage (mV) • FBB up to +2V and FMAX tracking : – ↗ frequency up to 460MHz at minimum voltage & © CEA. All rights reserved 2015 COOL Chips– E. Beigné | 26 DSP energy performance measurements Cliquez pour modifier le style du titre 450 Boost 0mV FBB 0V Energy/cycle (pJ/cycle) 400 Boost 500mV FBB 0.5V 350 FBB 1.0V Boost 1000mV 300 FBB 1.5V Boost 1500mV 250 FBB 2.0V Boost 2000mV 200 150 100 50 62pJ/cycle @ 460MHz 0 300 500 700 900 1100 1300 1500 1700 • For a fixed voltage supply : 1900 2100 2300 2500 Frequency (MHz) – Lowest energy at 460MHz – Power consumption : 370mW at 1V & © CEA. All rights reserved 2015 COOL Chips– E. Beigné | 27 DSP energy Cliquez pourperformance modifier lemeasurements style du titre 450 400 Boost 0mV FBB 0V 350 Boost 500mV FBB 0.5V 300 Energy/cycle (pJ/cycle) +14% frequency Boost 1000mV FBB 1.0V FBB 1.5V Boost 1500mV 250 FBB 2.0V Boost 2000mV 200 150 -20% energy/cycle 100 50 +59% frequency 0 300 500 700 900 1100 1300 1500 1700 • FBB and FMAX tracking : 1900 2100 2300 2500 Frequency (MHz) – ↗ Frequency up to 59% (target 100pJ/cycle) – ↘ Energy by 20% (target 1.7 GHz) & © CEA. All rights reserved 2015 COOL Chips– E. Beigné | 28 Comparison with State of the Art WVR Cliquez pour modifier le style du titre 3000 3000 This work 22nm, INTEL, ISSCC TI, CEVA, 40nm TI, 40nm Frequency (MHz) 1000 INTEL, 32nm, ISSCC 2012 MIT, TI, 28nm, ISCC 2011 CSEM (100µW/MHz) 100 TI (200µW/MHz) INTEL, 22nm, ISCC MIT, TI, 28nm, ISSCC 2011 2012 10 MIT, TI, 28nm, ISSCC 2011 INTEL, 32nm, ISCC 2012 NXP, IMEC, 32nm, ISSCC 2011 1 00 1.2 & 0,20.2 1.4 0,4 0.4 0,6 0.6 0,8 Supply Voltage (V) © CEA. All rights reserved 0.8 1 1,2 1 2015 COOL Chips– E. Beigné 1,4 | 29 Low power SOC challenges : Energy Efficiency Fine-Grain AVFS solutions FDSOI technology brings a new actuator Fine-Grain AVFS with Body Biasing Silicon results in FDSOI 28nm Future IoT needs and Conclusions & © CEA. All rights reserved Diego Puschini | ICDV 2014 | 30 What about for IoT applications? Cliquez pour FDSOI modifier le style du titre Energy harvesting will bring more challenges to Voltage supplies levels Autonomous Wireless Sensor Nodes are requiring even more Versatility Moving the operating range from very low power to medium speed Leakage is a big constraint Possible use of Reverse Body Biasing and Poly Biasing Analog and RF is performant Towards fully integrated mixed-signal nodes & © CEA. All rights reserved 2015 COOL Chips– E. Beigné | 31 Conclusion Cliquez pour modifier le style du titre Circuit designers are faced with conflicting requirements Decrease the power dissipation AND Maintain the performance In a world of increasing parametric variations This can be met thanks to a combination of design techniques Reduce design margins and adapt to environment Sense&React paradigm Leverage the technology’s possibilities Well engineering and back-biasing in FDSOI Take home message Develop technology that brings additional actuators to circuit designers This will unleash their creativity Think about low leakage applications like IoT Low voltage performances Performance adaptation & © CEA. All rights reserved 2015 COOL Chips– E. Beigné | 32
