Download LS7083 LS7084

LSI/CSI
LS7083
LS7084
UL
®
A3800
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
(631) 271-0400 FAX (631) 271-0405
QUADRATURE CLOCK CONVERTER
RBIAS (Pin 1)
Input for external component connection. A resistor connected
between this input and VSS adjusts the output clock pulse width
(Tow). For proper operation, the output clock pulse width must be
less than or equal to the A, B pulse separation (TOW ≤ TPS).
VDD (Pin 2)
Supply Voltage positive terminal.
VSS (Pin 3)
Supply Voltage negative terminal.
A (Pin 4)
Quadrature Clock Input A. This input has a filter circuit to validate
input logic level and eliminate encoder dither.
B (Pin 5)
Quadrature Clock Input B. This input has a filter circuit identical
to input A.
x4/x1 (Pin 6)
This input selects between x1 and x4 modes of operation. A highlevel selects x4 mode and a low-level selects the x1 mode. In x4
mode, an output pulse is generated for every transition at either
A or B input. In x1 mode, an output pulse is generated in one
combined A/B input cycle. (See Figure 2.)
7083/84-011309-1
V DD (+V )
2
V SS (-V)
3
A
4
RBIAS
1
V DD (+V)
2
V SS (-V)
3
A
4
LS7084
INPUT/OUTPUT DESCRIPTION:
1
LSI
DESCRIPTION
The LS7083 and LS7084 are CMOS quadrature clock converters. Quadrature clocks derived from optical or magnetic encoders, when applied to the A and B inputs of the LS7083 or
LS7084, are converted to strings of Up Clocks and Down Clocks
(LS7083) or to a Clock and an Up/Down direction control
(LS7084). These outputs can be interfaced directly with standard
Up/Down counters for direction and position sensing of the en-
RBIAS
LS7083
Applications:
• Interface incremental encoders to Up / Down Counters
(See Figure 6A and Figure 6B)
• Interface rotary encoders to Digital Potentiometers
(See Figure 7)
PIN ASSIGNMENT - TOP VIEW
LSI
FEATURES:
• x1 and x4 mode selection
• Up to 16MHz output clock frequency
• Programmable output clock pulse width
• On-chip filtering of inputs for optical or
magnetic encoder applications.
• TTL and CMOS compatible I/Os
• +4.5V to +10V operation (VDD - VSS)
• LS7083, LS7084 (DIP);
LS7083-S, LS7084-S (SOIC) - See Figure 1
January 2009
8
UPCK
7
DNCK
6
x4/x1
5
B
8
CLK
7
UP/DN
6
x4/x1
5
B
FIGURE 1
LS7083 - DNCK (Pin 7)
In LS7083, this is the DOWN Clock Output. This output consists of
low-going pulses generated when A input lags the B input.
LS7084 - UP/DN (Pin 7)
In LS7084, this is the count direction indication output. When A input leads the B input, the UP/DN output goes high indicating that
the count direction is UP. When A input lags the B input, UP/DN
output goes low, indicating that the count direction is DOWN.
LS7083 - UPCK (Pin 8)
In LS7083, this is the UP Clock output. This output consists of lowgoing pulses generated when A input leads the B input.
LS7084N - CLK (Pin 8)
In LS7084, this is the combined UP Clock and DOWN Clock output.
The count direction at any instant is indicated by the UP/DN output
(Pin 7).
NOTE: For the LS7084, the timing of CLK and UP/DN requires that
the counter interfacing with LS7084 counts on the rising edge of the
CLK pulses.
ABSOLUTE MAXIMUM RATINGS:
PARAMETER
DC Supply Voltage
Voltage at any input
Operating temperature
Storage temperature
SYMBOL
VDD - VSS
VIN
TA
TSTG
VALUE
11.0
VSS - 0.3 to VDD + 0.3
0 to +70
-55 to +150
UNITS
V
V
°C
°C
DC ELECTRICAL CHARACTERISTICS:
(All voltages referenced to VSS, TA = 0oC to 70oC.)
PARAMETER
Supply voltage
Supply current
SYMBOL
VDD
IDD
MIN
4.5
-
x4/x1 Logic Low
A, B Logic Low
VIL
VIL
-
x4/x1Logic High
A, B Logic High
VIH
VIH
0.7VDD
3.1
5.0
5.6
ALL OUTPUTS:
Sink Current
VOL = 0.4V
IOL
IOH
Source Current
VOH = VDD - 0.5V
MAX
10.0
6.0
UNITS
V
µA
0.3VDD
0.6
1.0
1.1
CONDITION
VDD = 10V, All
input frequencies = 0Hz
RBIAS = 2MΩ
V
V
V
V
VDD = 4.5V
VDD = 9V
VDD = 10V
-
V
V
V
V
VDD = 4.5V
VDD = 9V
VDD = 10V
1.75
5.0
5.7
-
mA
mA
mA
VDD = 4.5V
VDD = 9V
VDD = 10V
1.0
2.5
3.0
-
mA
mA
mA
VDD = 4.5V
VDD = 9V
VDD = 10V
TRANSIENT CHARACTERISTICS:
(TA = 0° C to 70° C)
PARAMETER
A, B inputs:
Validation Delay
SYMBOL
MIN
TVD
A, B inputs:
Pulse Width
-
85
100
160
ns
ns
ns
VDD = 10V
VDD = 9V
VDD = 4.5V
TPW
TVD + TOW
Infinite
ns
-
A to B or B to A
Phase Delay
TPS
TOW
Infinite
ns
-
A, B frequency
fA, B
-
1
2TPW
Hz
-
Input to Output Delay
TDS
-
120
150
235
ns
ns
ns
VDD = 10V
VDD = 9V
VDD = 4.5V
Includes input
validation delay
Output Clock Pulse Width
TOW
50
-
ns
See Fig. 4 & 5
7083/84-121508-2
MAX
UNITS
CONDITION
TPW
A
B
TPS
TDS
UPCK
(x1/7083)
TOW
DNCK
(x1/7083)
UPCK
(x4/7083)
DNCK
(x4/7083)
CLK
(x1/7084)
CLK
(x4/7084)
TDS
UP/DN
(7084)
FIGURE 2. LS7083 / LS7084 INPUT / OUTPUT TIMING DIAGRAM
RBIAS
1
A 4
B
5
CURRENT
MIRROR
FILTER
FILTER
DUAL
ONE-SHOT
DUAL
ONE-SHOT
CLOCK
AND
DIRECTION
DECODE
x4 CLOCK
8
x1 CLOCK
UP/DN
x4/x1
UPCK or CLK
MUX
7 DNCK or UP/DN
6
V DD
2
+V
V SS
3
-V
FIGURE 3. LS7083/LS7084 BLOCK DIAGRAM
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
7083/84-121608-3
1500
1250
V DD = 5V
25
OUTPUT CLOCK PULSE WIDTH, Tow, µs
V DD = 9V
1000
OUTPUT CLOCK PULSE WIDTH, Tow, ns
30
V DD = 5V
V DD = 10V
750
500
250
100
200
300
400
20
V DD = 9V
15
V DD = 10V
10
5
500
2
6
4
Figure 4. Tow vs RBIAS, k
8
12
10
Figure 5. Tow vs RBIAS, M
MODE SELECT
+V
+V
ENCODER
A CLOCK
4
B CLOCK
5
1
6
2
x4/x1
V DD
UPCK
A
B
DNCK
RB
VDD
8
5
7
4
ENCODER
A CLOCK
B CLOCK
CK-DN
4
A
CLK
LS7084
5 B
1
V SS
3
2
VDD
x4/x1
CK-UP
V SS
16
6
40193
LS7083
RBIAS
16
UP/DN
RBIAS
RB
8
+V
+V
R
V DD
8
15
7
10
CK
4516
UP/DN
V SS
3
V SS
8
FIGURE 6B*. TYPICAL APPLICATION FOR LS7084 WITH X4/X1 MODE SELETION
FIGURE 6A. TYPICAL APPLICATION FOR LS7083 IN x4 MODE
*See NOTE at bottom right of Page 1
+5V
DIGITAL
POTENTIOMETER
A1
10k
10k
1M
2
B
ROTARY
ENCODER
1 RBIAS
3
A
GND
10k
10k
VDD
U/D
V SS
X4/X1
4 A
B
7083/84-011209-4
8
1 CLK
7
2
6
3
A1
B1
6
5
4
GND
W1
5
U/D
LS7084
0.01uF
Part Number:
RE11CT-V1Y12-EF2CS
CLK
V DD
CS
AD5220
0.01uF
FIGURE 7. Rotary Encoder Control of Digital Potentiometer
8
7
B1
W1