Download P4M644YL, P8M648YL SDRAM MODULE 4M, 8M x 64 DIMM

SDRAM MODULE
P4M644YL,P8M648YL
4M, 8M x 64 DIMM
Features:
•
•
•
•
•
•
•
•
JEDEC - Standard 168-pin (gold), dual in-line memory
module (DIMM).
TSOP components.
Single 3.3v +.3v power supply.
Nonbuffered fully synchronous; all signals measured on
positive edge of system clock.
Internal pipelined operation; column address can be
changed every clock cycle.
Quad internal banks for hiding row access/precharge.
64ms 4096 cycle refresh.
All inputs, outputs, clocks LVTTL compatible.
Options:
4 - 4Mx16 SDRAM TSOP
8 - 4Mx16 SDRAM TSOP
Part Number:
P4M644YL-XX
P8M648YL-XX
KEY DIMM MODULE TIMING PARAMETERS
Module
Component
Clock
CAS Latency
Marking
Marking
Freq
-66CL2
-10/-12
66MHZ
2 or 3
-100CL3A
-8A
100MHZ
3
GENERAL DESCRIPTION
The S4M644YL and S8M648YL are high performance
dynamic random-access 32MB and 64MB modules
respectively. These modules are organized in a x64
configuration, and utilize dual bank architecture with a
synchronous interface. All signals are registered on the
positive edge of the clock signals CK0 through CK3. Read and
write accesses to the SDRAM are burst oriented; accesses
start at a location and continue for a programmed number of
locations in a sequence. Accesses begin with an ACTIVE
command, which is followed by a READ or WRITE command.
ABSOLUTE MAXIMUM RATINGS:
Voltage on Vcc Supply relative to Vss...................-1 to +4.6V
Operating Temperature TA (Ambient) .............25 ° to +70 °C
Storage Temperature ......................................-55 to +125 °C
Power Dissipation……………………………………4 or 8 W
Short Circuit Output Current……………………….….50 mA
PIN ASSIGNMENT (Front View)
168-PIN DIMM
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Name
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
NC
NC
Vss
NC
NC
Vcc
WE#
DQMB0
QQMB1
SO#
DU
Vss
A0
A2
A4
A6
A8
A10/AP
BA1
Vcc
Vcc
CK0
Pin
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Name
Vss
DU
S2#
DQMB2
DQMB3
DU
Vcc
NC
NC
NC
NC
Vss
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
NC
CKE1
Vss
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
CK2
NC
NC
SDA
SCL
Vcc
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Name
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
NC
NC
Vss
NC
NC
Vcc
CAS#
DQMB4
DQMB5
S1#
RAS#
Vss
A1
A3
A5
A7
A9
BA0
A11
Vcc
CK1
RFU
Pin
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Stresses beyond these may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at or beyond these conditions is not implied.
Exposure to these conditions for extended periods may affect
reliability.
__________________________________________________________________________________________________
P4M644
1
SpecTek reserves the right to change products
Rev: 6/14/99
or specifications without notice. 1999 SpecTek
Name
Vss
CKE0
S3#
DQMB6
DQMB7
RFU
Vcc
NC
NC
NC
NC
Vss
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
NC
NC
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
CK3
NC
SA0
SA1
SA2
Vcc
P4M644YL,P8M648YL
CAPACITANCE: (This parameter is sampled. VCC = +3.3V m 0.3V; f = 1 MHz)
Parameter
Symbol
Input Capacitance: A0 - A11, BAO-BA1, RAS#, CAS#, WE#,
Input Capacitance: S0#-S3#, CK0-CK3
Input Capacitance: CKE0, CKE1,
Input Capacitance: DQMB0#, DQMB7
Input Capacitance: SQL, SA0-SA2
Input/Output Capacitance: DQ0-DQ63, SDA
Cl1
Cl2
Cl3
Cl4
Cl5
CIO
Max
32MB
64MB
25
45
15
25
25
45
8
15
6
6
10
15
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS:
Parameter
Symbol
Min
Supply Voltage
Vcc/Vccq
3.0
Input High (Logic 1) Voltage, All inputs
VIH
2.0
Input Low (Logic 0) Voltage, All inputs
VIL
-0.3
Input Leakage Current Any input = 0V < VIN < Vcc
-10
II
-20
All other pins not under test = 0V
I2
-30
I3
Output Leakage Current DQs are disabled; 0V < VOUT < VccQ
IOZ
-20
Output High Voltage (IOUT = -4 mA)
VOH
2.4
Output Low Voltage (IOUT = 4 mA)
VOL
Units
pF
pF
pF
pF
pF
pF
Max
3.6
Vcc + .3
0.8
10
20
30
20
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS: Vcc = 3.3V ± 10%V, Temp. = 25° to 70 °C
Supply Current
Symbol
-8A
-10
OPERATING CURRENT: ACTIVE mode, burst =
CL = 2
Icc1
32MB
380
N/A
1, READ or WRITE, tRC > tRC (MIN), one bank
64MB
730
active,
CL = 3
Icc1
32MB
440
420
64MB
890
850
STANDBY CURRENT: POWER-DOWN mode,
tCK = 15ns
Icc2
32MB
20
16
CKE = LOW, no accesses in progress
64MB
40
32
CLK = LOW
Icc2
32MB
20
8
64MB
40
16
STANDBY CURRENT: CS# = HIGH, CKE = HIGH,
Icc3
32MB
200
200
tCK = 15ns, both banks idle
64MB
400
400
STANDBY CURRENT: CS# = HIGH, CKE = HIGH, tCK = 15ns,
Icc4
32MB
200
200
both banks active after tRCD met, no accesses in progress.
64MB
400
400
OPERATING CURRENT: BURST mode after tRCD
CL = 2
Icc5
32MB
680
N/A
met, continuous burst, READ, WRITE, tCK > tCK. MIN,
64MB
880
other bank active
CL = 3
Icc5
32MB
780
740
64MB
980
960
AUTO REFRESH CURRENT tRC > tRC (MIN)
CL = 2
Icc6
32MB6
780
N/A
4MB
1560
CL = 3
Icc6
32MB
1000
960
64MB
2000
1920
0.4
Units
V
V
V
uA
uA
V
V
Units
mA
Notes
1, 2, 3
mA
1, 2, 3
mA
mA
mA
3, 4
mA
3, 4
mA
1, 2, 3
mA
1, 2, 3
mA
1, 2, 3
mA
1, 2, 3
NOTES:
1.
2.
3.
4.
Icc is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open.
The Icc current will decrease as the CAS latency is reduced. This is because maximum cycle rate is slower as CAS latency is
reduced.
Address transitions average one transition every 30ns.
Other input signals are allowed to transition no more than once in any 30ns period.
__________________________________________________________________________________________________
P4M644
2
SpecTek reserves the right to change products
Rev: 6/14/99
or specifications without notice. 1999 SpecTek
P4M644YL,P8M648YL
AC ELECTRICAL CHARACTERISTICS: Vcc = 3.3V ± 10%V, Temp. = 25°
AC CHARACTERISTICS
-8A
-8A
PARAMETER
SYM
MIN
MAX
Access time from CLK (positive edge) CL = 3
tAC
6
Access time from CLK (positive edge) CL = 2
tAC
N/A
Address hold time
tAH
1
Address setup time
tAS
2
CLK high level width
tCH
3
CLK low level width
tCL
3
Clock cycle time CL = 3
tCK
8
Clock cycle time CL = 2
tCK
N/A
CKE hold time
tCKH
1
CKE setup time
tCKS
2
CS#, RAS#, CAS#, WE#, DQM hold time
tCMH
1
CS#, RAS#, CAS#, WE#, DQM setup time
tCMS
2
Data-in hold time
tDH
1
Data-in setup time
tDS
2
Data-out high impedance time
tHZ
9
Data-out low impedance time
tLZ
2
Data-out hold time
tOH
3
ACTIVE to PRECHARGE command period
tRAS
50
16K
AUTO REFRESH and ACTIVE to ACTIVE
tRC
80
command period
ACTIVE to READ or WRITE delay
tRCD
30
Refresh period (4096 cycles) tT = 1ns.
tREF
64
PRECHARGE command period
tRP
30
ACTIVE bank A to ACTIVE bank B command
tRRD
20
period
Transition time
tT
3
2
Write recovery time
tWR
20
Exit SELF REFRESH to ACTIVE command
tXSR
80
to 70°C (CL = CAS Latency)
-10
-10
MIN
MAX
UNITS
NOTES
7.5
ns
9
ns
1
ns
3
ns
3.5
ns
3.5
ns
10
ns
15
ns
1
ns
3
ns
1
ns
3
ns
1
ns
3
ns
9
ns
1
2
ns
3
ns
60
16K
ns
96
ns
30
64
30
20
1
20
96
2
ns
ms
ns
ns
ns
ns
ns
NOTES:
1.
2.
tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to Voh or Vol. The last valid data
element will meet tOH before going high-Z.
* See –8 Speed Options Chart on page 2.
AC ELECTRICAL CHARACTERISTICS: Vcc = 3.3V ± 10%V, Temp. = 25° to 70°C (CL = CAS Latency)
PARAMETER
SYM
-8A
-10 UNITS
READ/WRITE command to READ/WRITE command
tCCD
1
1
tCK
CKE to clock disable or power down entry mode
tCKED
1
1
tCK
CKE to clock enable or power down exit setup mode
tPED
1
1
tCK
DQM to input data delay
tDQD
0
0
tCK
DQM to data mask during WRITEs
tDQM
0
0
tCK
DQM to data high-impedance during READs
tDQZ
2
2
tCK
WRITE command to input data delay
tDWD
0
0
tCK
Data-in to ACTIVATE command
tDAL
5
5
tCK
Data-in tp precharge reference clock minimum cycle rate, tWR Timing
tDPL
2
2
tCK
Last data-in to burst stop command
tBDL
0
0
tCK
Last data-in to new READ/WRITE command
tCDL
1
1
tCK
Last data-in to precharge command
tRDL
2
2
tCK
LOAD MODE REGISTER command to command
tMRD
2
2
tCK
Data-out to high impedance from precharge CL = 3
tROH
3
3
tCK
Data-out to high impedance from precharge CL = 2
tROH
2
tCK
NOTES:
1. Clocks required specified by JEDEC functionality and not dependent on any timing parameter.
2. Timing actually specified by tCKS, clock(s) specified as a reference only at a minimum cycle rate.
3. Timing actually specified by tWR plus tRP clock(s) specified as a reference only at a minimum cycle rate.
NOTES
1
2
2
1
1
1
1
3
1
1
1
1
1
1
__________________________________________________________________________________________________
P4M644
3
SpecTek reserves the right to change products
Rev: 6/14/99
or specifications without notice. 1999 SpecTek
P4M644YL,P8M648YL
SERIAL PRESENCE-DETECT OPERATION - This module incorporates Serial Presence-Detect (SPD) . The SPD function is
implemented using a 2,048 bit EEPROM, containing 256 bytes of nonvolatile storage. The first 128 bytes can be programmed by
SpecTek to identify the module type and various DRAM organization and timing parameters. The remaining 128 bytes of storage are
available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device
(DIMM) occur via a standard IIC bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA(2:0), which provide 8
unique DIMM/EEPROM addresses.
SPD CLOCK AND DATA CONVENTIONS - Data states on the SDA line can change only during SCL LOW. SDA state changes during
SCL HIGH are reserved for indicating start and stop conditions (Figures 1 and 2).
SPD START CONDITION - All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is
HIGH. The serial PD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command
until this condition has been met.
SPD STOP CONDITION - All communications are terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL
is HIGH. The stop condition also places the serial PD device into standby power mode.
SPD ACKNOWLEDGE - Acknowledge is a software convention used to indicate successful data transfers. The transmitting device,
either master or slave, will release the bus after transmitting eight bits of data (Figure 3).
The PD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the
device and a write operation have been selected, the PD device will respond with an acknowledge after the receipt of each subsequent
eight bit word. In the read mode the PD device will transmit eight bits of data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return
to standby power mode.
SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS
PARAMETER/CONDITION
Supply Voltage
Input High (Logic 1) Voltage, all inputs
Input Low (Logic 0) Voltage, all inputs
OUTPUT LOW VOLTAGE, IOUT =3mA
INPUT LEAKAGE CURRENT, VIN = GND to Vcc
OUTPUT LEAKAGE CURRENT, VOUT = GND to Vcc
STANDBY CURRENT SCL=SDA=Vcc -0.3V, All other inputs = GND
or 3.3V +10%
POWER SUPPLY CURRENT SCL clock frequency = 100 KHz
Symbol
VCC
VIH
VIL
VOL
ILI
ILO
ISB
MIN
3.0
Vcc x .7
-1.0
ICC
(VCC = +3.3V m 0.3V)
MAX
Units
3.6
V
Vcc x .5 V
Vcc x .3 V
0.4
V
10
µA
10
µA
30
µA
2
Notes
µA
SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS
(VCC = +3.3V m 0.3V)
AC CHARACTERISTICS
PARAMETER/CONDITION
Symbol
MIN
MAX
Units
Notes
t
SCL LOW to SDA data-out valid
AA
0.3
3.5
µs
t
IIdle bus time before a transition can start
BUF
4.7
µs
t
Data-out hold time
DH
300
ns
t
SDA and SCL fall time
F
300
ns
T
Data-in hold time
HD:DAT
0
µs
T
Start condition hold time
HD:STA
4
µs
t
Clock HIGH period
HIGH
4
µs
t
Noise suppresssion time constant at SCL, SDA inputs
l
100
ns
t
Clock LOW period
LOW
4.7
µs
t
SDA and SCL rise time
R
1
µs
t
SCL clock frequency
SCL
100
KHz
T
Data-in setup time
SU:DAT
250
ns
T
Start condition setup time
SU:STA
4.7
µs
T
Stop condition setup time
SU:STO
4.7
µs
t
WRITE cycle time
WR
10
ms
1
NOTES:
t
1. The SPD EEPROM WRITE cycle time ( WR) is the time from a valid stop condition of a WRITE sequence to the end of the
EEPROM internal erase/program cycle. During the WRITE cycle the EEPROM bus interface circuit is disabled, SDA remains HIGH due
to pull-up resistor, and the EEPROM does not respond to its slave address.
__________________________________________________________________________________________________
P4M644
4
SpecTek reserves the right to change products
Rev: 6/14/99
or specifications without notice. 1999 SpecTek
P4M644YL,P8M648YL
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
Figure 1
DATA VALIDITY
SCL
SDA
START
BIT
Figure 2
DEFINITION OF START
AND STOP
STOP
BIT
8
SCL from
Master
9
Data Output
from Transmitter
Data Output
from Receiver
Figure 3
ACKNOWLEDGE RESPONSE
FROM RECEIVER
Acknowledge
__________________________________________________________________________________________________
P4M644
5
SpecTek reserves the right to change products
Rev: 6/14/99
or specifications without notice. 1999 SpecTek