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ISSN 2319-8885
Vol.05,Issue.06,
March-2016,
Pages:1021-1025
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A Novel Arithmetic Logic Unit (ALU) Design using Modified GDI Technique
BHANUPRIYA SONKESHRI1, GOURI SHANKAR SHARMA2
1
PG Scholar, Dept of Electronics & Telecommunication (VLSI & ES Design), Disha Institute of Management and Technology,
Raipur, India, E-mail: [email protected].
2
Assistant Professor, Dept of Electronics & Telecommunication, Disha Institute of Management and Technology, Raipur, India,
E-mail: [email protected].
Abstract: Power dissipation has a main influence in creating almost any project. Since this element has a major role in
determining the efficiency of any developed project that is why in this report we have been advising an agenda with regard to
sequential circuits so that we could reduce the power dissipation. Power dissipation in turn lowers the main power dissipation of
the CPU. In this paper, we offered the low power modified GDI technique so as decrease the power dissipation of any circuit. The
proposed circuit is an ALU (Arithmetic and Logic Unit) made of modified GDI adder as well as MUX based circuits.
Consequently, the planning can be approved for small area as well as low power ALU. With this, ALU is made of 4x1
multiplexer, 2x1 multiplexer as well as full adder made to implement common functions, such as AND, OR, etc. and computation
functions, as ADD and SUBTRACT. GDI cells are used in the circuit connected with multiplexers as well as full adders which
might be subsequently connected to achieve an ALU design. This simulation results are performed Tanner EDA software with
TSMC018 technology.
Keywords: ALU, GDI, Power Dissipation.
I. INTRODUCTION
ALU is one of the principal elements of microprocessor.
Many people employ fast dynamic logic circuits and have
cautiously optimized designs. The power usage of ALU is the
reason for a significant part of overall power use of data path
[1]. ALU is one of the maximum power-density units in the
processor chip, mainly because it is clocked on the maximum
speed which is maintained disorganized most likely resulting
in thermal hotspots and sharp temperature gradients in the
execution core [2]. Power dissipation is essentially the power
that is converted to heat and conducted as well as radiated
away from the circuit. Electronic and electrical equipments
can have a bound on the current they could securely handle
that's not an electric bound, but a new physical one[3]. As an
example, a new transistor may possibly otherwise be able to
handle some amount of current, nonetheless it is granted a
lower current rating for the reason that die will get hot[4].
Power Dissipation is measured in watts, and also works by
using the usual Ohm's law calculations for power [5]. In the
majority of Very Large Scale IC (VLSI) applications, full
adder circuit is functional building block and most vital part
of the complex arithmetic circuits including microprocessors,
digital signal processors as well as any ALUs [6]. Almost
every complex computational circuit needs full adder
circuitry. The whole computational block power dissipation
may be lowered by means of applying low power techniques
in full adder circuitry [7]. We now have created ALU in
several ways through the use of GDI cells to realize
multiplexers and also full adder circuit. The actual input and
output sections include 4x1 and also 2x1 multiplexers and
also ALU is designed using full adder.
II. NEW GDI TECHNIQUE
Gate Diffusion Input (GDI) method is based on the use of a
simple cell. One may remember the standard CMOS inverter
at the first glance of this circuit, but there are some important
dissimilarities: (1) The GDI cell contains three inputs—G
(common gate input of NMOS and PMOS), P (input to the
source/drain of PMOS), and N (input to the source/drain of
NMOS). (2) Bulks of both NMOS and PMOS are connected
to N or P (respectively), so it can be randomly biased in
contrast to CMOS inverter. The basic GDI cell is shown in
Fig.1 below.
Fig.1. The basic GDI cell.
Copyright @ 2016 IJSETR. All rights reserved.
BHANUPRIYA SONKESHRI, GOURI SHANKAR SHARMA
The circuits required to design Arithmetic and Logic unit are
 Multiplexer
 XOR Gate
 Full Adder
A. Multiplexer
Multiplexer will act as a digital switch. Selection line plays
a major role to select particular input. If the number of input
lines is ―2n‖ and selection lines will be ―n‖. With the ―n‖
selection line the particular ―2n‖ input line will be selected.
Figure shows the realization of 2x1 multiplexer and Fig.2
shows the design of 2x1 multiplexer. The number of selection
lines for 2x1 multiplexer is one selection line. According to
the state of select line i.e. 0 or 1, the inputs will be selected. In
the same way 4x1 multiplexer is also designed to implement
arithmetic and logic unit. The number of selection lines
required for 4x1 multiplexer is two and with respect to the
state of the two selection lines the four inputs will be
activated. Fig.3 shows the circuit of 4x1 multiplexer.
Fig.4. GDI based XOR gate.
C. Full adder
Fig.2. GDI based 2x1 Multiplexer.
Fig.5. GDI based One bit full adder.
One bit full adder circuit is also an essential block used to
design Arithmetic and logic unit. Full adder circuit contains
three inputs and two outputs named sum and carry. The
operation adds only one bit numbers. The number of
transistors required to design one bit full adder are less so the
area will be optimized for the better performance of
arithmetic and logic unit circuit design. Fig.5 shows the
implementation of the one bit full adder.
Fig.3. GDI based 4x1 multiplexer.
B. Xor Gate
XOR gate is the major building block of the full adder and
also it gives the sum output of the full adder. The number of
transistors used to design the XOR gate is four. So the adder
circuit can be optimized by reducing the area of XOR gate.
Fig. 4 shows the circuit design of XOR gate.
III. ALU (ARITHMETIC AND LOGIC UNIT)
The Arithmetic and Logic Unit (ALU) is the significant
component in the microprocessor it performs all arithmetic
operations like addition, multiplication, subtraction, etc. and
logical operations like OR, XOR, AND, NAND. In a
computer, Central Processing Unit (CPU) is the brain of the
computer and ALU is fundamental block of CPU. The
processor found inside Graphical Processor Unit is also
containing a powerful ALU as shown in Fig.6. We design
ALU using full adder and the multiplexer circuits. The full
adder circuits used here is a single bit full adder. The
multiplexer circuit is a 4X1 MUX and 2X1 MUX. The full
International Journal of Scientific Engineering and Technology Research
Volume.05, IssueNo.06, March-2016, Pages: 1021-1025
A Novel Arithmetic Logic Unit (ALU) Design using Modified GDI Technique
adder circuits are designed using PTL GDI logic style. The
constant voltage (i.e. supply voltage) and a high-voltage
multiplexer used in the ALU is for input signal selection and
terminal SN configured to be connected to a low constant
to determine what kind operation to performed .The
voltage (i.e. Ground). Including these terminals, this ensures
multiplexer is implemented using six transistors. The
that the Mod-GDI cell can be implemented with all current
transistor count is reduced and power consumption is also low
CMOS technologies
as compared to pass transistor multiplexer. This design is
simple in terms of time and area consumption.
Fig.7. Modified GDI Cell.
With Modified GDI cell we have designed the ALU Unit
Their results are compared and shown below.
V. SIMULATION AND RESULTS
Theses circuits are designed and simulated using Tanner
EDA Tools in 0.18µm technology. Circuits are Design in SEdit and results as shown in Figs. 8 to 11.
Fig.6. ALU Design.
The full adder performs the computing functions of ALU.
The pass transistor logic reduces the parasitic capacitance and
GDI logic increases the speed of the operation. In existing
method, ALU is designed using 4X1 MUX, 2X1 MUX and
full adder. The multiplexers were designed using pass
transistor logic. And the full adder is implemented using 8
transistors. The transistor count is reduced and thus the power
consumption is also reduced.
IV. MODIFIED GDI TECHNIQUE
Power dissipation becomes most important limitation in
high performance applications. Optimizations for basic logic
gates are fundamental in order to get the better performance
of a variety of low power and high performance devices.
These limitations can be overcome by modified gate diffusion
input (Mod-GDI) logic style. This technique allows reducing
power consumption, delay and area of digital circuits. Fig. 7
shows basic Mod-GDI logic style. In contrast with the basic
GDI cell, Modified-GDI [Mod-GDI] cell contains a lowvoltage terminal SP configured to be connected to a high
Fig.8. GDI based ALU Design.
International Journal of Scientific Engineering and Technology Research
Volume.05, IssueNo.06, March-2016, Pages: 1021-1025
BHANUPRIYA SONKESHRI, GOURI SHANKAR SHARMA
TABLE I: Power Consumption Value of GDI and
Modified GDI ALU
TABLE II: Comparisons of Power Consumption Values
With Different Supply Voltage of ALU Designs
Fig.9. Simulation GDI ALU.
Fig.11. Power consumption relation between GDI and
Modified GDI Technique.
The table given above shows the comparison of power
dissipation between the two ALU designs in which one is
designed in GDI and Modified GDI technique.
VI. CONCLUSION
In this paper we implement the ALU design using Modified
Gate Diffusion technique which shows an effective reduction
in the power consumption when compared to the conventional
designs of ALU. In this paper, we have calculated the power
consumption of the ALU designs with different supply
voltages which is shown in the comparison table and in the
graphical representation as shown above. Here, a Modified
GDI technique is proposed which provides a body bias
connection that reduces the leakage current in the circuit.
Hence, the Modified GDI technique shows better
performance than the other existing designs of ALU.
Fig.10. Modified GDI based ALU design.
International Journal of Scientific Engineering and Technology Research
Volume.05, IssueNo.06, March-2016, Pages: 1021-1025
A Novel Arithmetic Logic Unit (ALU) Design using Modified GDI Technique
VII. REFERENCE
Author’s Profile:
[1] J. Han and M. Orshansky, ―Approximate computing: an
Bhanupriya Sonkeshri received her
emerging paradigm for power-efficient design,‖ 18th IEEE
Diploma(Electronics & Telecommunication)
European Test Symposium (ETS), 2013
from Govt. Polytechnic College, Jagdalpur
[2] R. Hegde and N.R. Shan hag, ―Soft digital signal
in 2011 and B. E. (Electronics &
processing,‖ Very Large Scale Integration (VLSI) Systems,
Telecommunication) from Bhilai Institute of
IEEE Transactions on , vol. 9, no. 6, pp. 813–823, 2001.
Technology, Durg in 2014. She is pursuing
[3] Vaibhav Gupta, Debabrata Mohapatra, Anand
her M. Tech. (VLSI & Embedded System
Raghunathan," Low-Power Digital Signal Processing Using
Design) from Disha Institute of Management
Approximate Adders"Computer-Aided Design of Integrated
and Technology, Raipur.
Circuits and Systems, IEEE Transactions on (Volume:32
, Issue: 1 ) 19 December 2012
Mr. Gouri Shankar Sharma is an Asst
[4] P. Kulkarni, P. Gupta, and M. Ercegovac, ―Trading
Professor at Disha Institute of Management
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International Journal of Scientific Engineering and Technology Research
Volume.05, IssueNo.06, March-2016, Pages: 1021-1025