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OUM (OVONIC UNIFIED MEMORY)
SEMINAR REPORT 2014
CONTENTS
INTRODUCTION TO OUM……………………………..……………………………….05
MEMORY STRUCTURE………………………………………………...……………….07
KEY ADVANTAGES OF OUM………………………………………..…………...……08
OUM ATTRIBUTES……………………………………………………….……………..09
ABOUT CHALCOGENIDE ALLOY…………………………………………...………..09
COMPARISON OF AMORPHOUS AND CRYSTALLINE PHASES…………….….....10
BASIC DEVICE OPERATION…………………………………………………...………11
CIRCUIT DEMONSTRATION…………………………………………………...………11
I-V CHRACTERISTICS…………………………………………………………...…...…16
R-V CHRACTERISTICS…………………………………………………………...….….17
TECHNOLOGY & PERFOMANCE………………………………………………….…..18
TECHNOLOGY CAPABILITIES……………………………………………….………..19
OUM: A MEMORY FOR EVERYBODY…………………………………...……….…..19
ADVANTAGES…………………………………………………………………….….….20
CONCLUSION…………………………………………………………………….……...23
REFERENCES………………………………………………………………………..…...23
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INTRODUCTION TO OUM
Almost 25% of the world wide chip markets are memory devices, each
type used for their specific advantages: the high speed of an SRAM, the high integration
density of a DRAM, or the nonvolatile capability of a FLASH memory device.The industry
is searching for a holy grail of future memory technologies to service the upcoming market
of portable and wireless devices. These applications are already available based on existing
memory technology, but for a successful market penetration. A higher performance at a
lower price is required. The existing technologies are characterized by the following
limitations. DRAMs are difficult to integrate. SRAMs are expensive. FLASH memory can
have only a limited number of read and write cycles .EPROMs have high power
requirement and poor flexibility.
None of the present memory technologies combine features like:
 The ability to retain stored charge for long periods with zero applied or refreshed
power.
 High speed of data writes.
 Low power consumption.
 Large number of write cycles.
Therefore, the whole industry is investigating different advanced memory
technologies like MRAM, FRAM, OUM or polymer devices etc.
FRAM:- This technology uses a crystal unit cell of pervoskite PZT (lead zirconate
titanate).data is stored by applying a very low voltage. The electric field moves the central
atom by changing crystal orientation of unit cell which results in the polarization of
internal dipoles.
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MRAM:- It uses a magnetic tunnel junction and transistor. The electric current switches
the magnetic polarity and this change is sensed as a resistance change.
OUM:- There is a growing need for nonvolatile memory technology for high density
stand alone embedded CMOS application with faster write speed and higher endurance
than existing nonvolatile memories. OUM is a promising technology to meet this need.
R.G.Neale, D.L.Nelson, and Gorden.E.Moore originally reported a phase‐change memory
array based on chalcogenide materials in 1970. Improvements in phasechange materials
technology subsequently paved the way for development of commercially available
rewriteable CDs and DVD optical memory disks. These advances, coupled with significant
technology scaling and better understanding of the fundamental electrical device operation,
have motivated development of the OUM technology at the present day technology node.
OUM is the non volatile memory that utilizes a reversible structural phase change
between amorphous and polycrystalline states in a GeSbTe chalcogenide alloy material.
This transition is accomplished by heating a small volume of the material with a write
current pulse and results in a considerable change in alloy resistivity. The amorphous phase
has high resistance and is defined as the RESET state. The low resistance polycrystalline
phase is defined as the SET state.
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MEMORY STRUCTURE
The above figure shows the memory structure of OUM
A memory cell consists of a top electrode, a layer of the
chalcogenide, and a resistive heating element. The base of the heater is connected to a
diode. As with MRAM, reading the micrometer-sized cell is done by measuring its
resistance. But unlike MRAM the resistance change is very large-more than a factor of
100. Thermal insulators are also attached to the memory structure in order to avoid data
lose due to destruction of material at high temperatures. To write data into the cell, the
chalcogenide is heated past its melting point and then rapidly cooled to make it amorphous.
To make it crystalline, it is heated to just below its melting point and held there for
approximately 50ns, giving the atoms time to position themselves in their crystal locations.
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KEY ADVANTAGES OF OUM
The following are the key advantages of OUM:
1. Endurance
2. Read‐write performance
3. Low programming energy
4. Process simplicity
5. Cost
6. CMOS embeddability
7. Scalability
Write endurance is competitive with other potential non volatile memory
technology, is superior to Flash. Read endurance is unlimited. The write/read performance
is comparable to DRAM. The OUM technology offers overwrite capablility, and bit/byte
data can be written randomly with no block erase required. Scaling is a key advantage of
OUM. Write speed and write energy both scales with programmed volume. Its low voltage
operation is compatible with continued CMOS feature and power supply scaling. Low
voltage operation and short programming pulse widths yield low energy operation for the
OUM, a key metric for mobile portable applications.
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 Non volatile in nature
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OUM ATTRIBUTES
 Non destructive read:-ensures that the data is not corrupted during a read cycle.
 Uses very low voltage and power from a single source.
 Write/erase cycles of 10e12 are demonstrated
 Poly crystalline
 This technology offers the potential of easy addition of non volatile memory to a
standard CMOS process.
 This is a highly scalable memory
 Low cost implementation is expected.
ABOUT CHALCOGENIDE ALLOY
Chalcogenide or phase change alloys is a ternary system of Gallium, Antimony
and Tellurium. Chemically it is Ge2Sb2Te5.
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Production Process:Powders for the phase change targets are produced by state‐of –the art
alloying through melting of the raw material and subsequent milling. This achieves the
defined particle size distribution. Then powders are processed to discs through Hot
Isotactic Pressing
COMPARISON OF AMORPHOUS AND CRYSTALLINE
PHASES
Amorphous: Short-range atomic order
 Low free electron density
 High activation energy
 High resistivity
Crystalline: Long-range atomic order
 High free electron density
 Low activation energy
 Low resistivity
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BASIC DEVICE OPERATION
The basic device operation can be explained from the
temperature versus time graph. During the amorphizing reset pulse, the temperature of the
programmed volume of phase change material exceeds the melting point which eliminates
the poly crystalline order in the material. When the reset pulse is terminated the device
quenches to freeze in the disordered structural state. The quench time is determined by the
thermal environment of the device and the fall time of the pulse. The crystallizing set pulse
is of lower amplitude and of sufficient duration to maintain the device temperature in the
rapid crystallization range for a time sufficient for crystal growth.
CIRCUIT DEMONSTRATION
In order to test the behavior of chalcogenide cells as circuit elements, the Chalcogenide
Technology Characterization Vehicle (CTCV) was developed. The CTCV contains a
variety of memory arrays with different architecture, circuit, and layout variations. Key
goals in the design of the CTCV were: 1) to make the read and write circuits robust with
respect to potential variations in cell electrical characteristics; 2) to test the effect of the
memory cell layout on performance; and 3) to maximize the amount of useful data
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obtained that could later be used for product design. The CTCV was sub-divided into four
chiplets, each containing variations of 1T1R cell memory arrays and various standalone
sub circuits. Standalone copies of the array sub circuits were included in each chiplet for
process monitoring and read/write current experiments.
FIGURE 7
A diagram of one of the chiplets is shown in Figure 7.
The arrays all contain 64k 1T1R cells, arranged as 256 rows by 256 columns. This is large
enough to make meaningful analyses of parasitic capacitance effects, while still permitting
four variations of the array to be placed on each chiplet. The primary differences between
arrays consist of the type of sense amp (single-ended or differential) and variations in the
location and number of contacts in the memory cell. The data in the single-ended arrays is
formatted as 4096 16-bit words (64k bits), and in the differential arrays as 4096 8-bit
words (32k bits). The 256 columns are divided into 16 groups of 16. One sense amplifier
services each group, and the 16 columns in each group are selected one at a time based on
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the four most significant address bits. In simulations, stray capacitance was predicted to
cause excessive read settling time when more than 16 columns were connected to a sense
amp. Each column has its own write current river, which also performs the column select
function for write operations.
The single-ended sense amplifier reads the current drawn by a single cell when a
voltage is applied to it. The differential amplifier measures the currents in two selected
cells that have previously been written with complementary data, and senses the difference
in current between them. This cuts the available memory size in half, but increases noise
margin and sensitivity. In both the single-ended and differential sense amplifiers, a voltage
limiting circuit prevents the chalcogenide element voltage from exceeding VT, so that the
cell is not inadvertently re-programmed. On one chiplet, there are two arrays designed
without sense amplifiers. Instead, the selected column outputs are routed directly to the 16
I/O pins where the data outputs would normally be connected. This enables direct analog
measurements to be made on a selected cell. A third array on this chiplet has both the
column select switches and the sense amplifiers deleted. Eight of the 256 columns are
brought out to I/O pins. This enables further analog measurements to be made, without an
intervening column select transistor.
“Conservative” and “aggressive” layout versions of the chalcogenide cell were made.
The conservative cell is larger, and has four contacts to bring current through to the
bottom and top electrodes of the memory cell. The aggressive cell contains only two
contacts per electrode, reducing its size. The pitch of the larger cell was used to establish
row and column spacing in all arrays. The aggressive cell could thus be easily substituted
for the conservative cell. Short wires were added to the smaller cell to map its connection
points to those of the larger. This permitted testing both cells in one array layout without
requiring significant additional layout labor. A final variation in the cell design involved
contact spacing. The contacts on the bottom electrode were moved to be either closer to
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or farther away from the chalcogenide "pore." This allows assessment of the effect of
contact spacing on the thermal and electrical characteristics of the chalcogenide pore.
Process monitoring structures were included on each chiplet to aid in calibration of
memory array test data. These consist of a standalone replica of each of the Write and
Read (single-ended) circuits, a CMOS inverter, and a 1T1R cell. The outputs of each of
these circuits were brought out to permit measurement of currents versus bias voltages.
Pins were provided on the CTCV for external bias voltage inputs to vary the read and
write current levels. The standalone copies of the read/write circuits are provided with all
key nodes brought out to pins. These replica circuits permit the read and write currents to
be programmed by varying the bias voltages. This allows more in-depth characterization
to be performed in advance of designing a product. In an actual product, on-chip
reference circuits would generate bias voltages. In the write circuit, a PFET driver is
connected to each column, and is normally turned off by setting its gate bias to VDD.
When a write is to occur, the selected driver’s gate is switched to one of two external bias
voltages for the required write pulse time. The bias voltages can be calibrated to set the
write drive currents to the levels needed to reliably write a one or a zero. The data inputs
determine which bias voltage is applied to each write driver. For the read circuit, several
cell resistance-sensing schemes were investigated during CTCV development. The
adopted scheme applies a controlled voltage to the cell to be read, and the resulting
current is measured. Care is taken not to exceed VT during a read cycle. The sense
amplifier reflects the read current into a programmable NFET load, thus generating a
high (1) or low (0) output. The gate bias of all sense amplifier loads can be varied in
parallel to change the current level at which the output voltage switches. The bias levels
are calibrated via a standalone copy of the read circuit that has all key nodes brought out
to pins. The NFET load's output is buffered by a string of CMOS inverters to provide full
CMOS logic voltage swing, and then routed to the correct data output I/O pad driver.
When a read circuit supplies a current to a selected cell, the cell's corresponding column
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charges up toward the steady state read voltage. The column voltage waveform is
affected by the programmed resistance and internal capacitances of each of the cells in
the column, and thus is pattern dependent. The combined charge from all of the column's
cells during this charging process may travel into the sense amplifier input, momentarily
causing it to experience a transient, which could prevent the accessed cells’ data from
being read correctly. To minimize this effect, each column is discharged after a write, and
recharged before a read. Transistor parametric and discrete memory element test
structures were tested on the CTCV lot at the wafer level. These tests served two
purposes. The first goal was to confirm that the extra processing steps involved in
inserting the chalcogenide flow had no effect on the base CMOS technology. No
statistical differences in transistor parametric values were noted between these wafers and
standard 0.5μm RHCMOS product. The second goal of wafer test was to measure the set,
reset and dynamic programming resistances (RSET, RRESET and RDYNAMIC),
threshold and holding voltages (VT and VH), and required programming currents (ISET
and IRESET) of stand-alone, two terminal chalcogenide memory elements. These values
were used to set the operating points of the write driver circuits and the bias point of the
sense amp. To allow debug of the CTCV module test setup in parallel with the wafer test
effort, one wafer was selected and diced to remove the CTCV die. Five die of one of the
four chiplets, (chip 1) were sent ahead through the packaging process. Chip 1 has four
different array configurations, two 64 kbit, single ended sense amp arrays and two 32
kbit, differential sense amp arrays. Two of the arrays were constructed with the
conservative cell layout and two with the aggressive cell layout. Functional test patterns
used on these send-ahead devices included all zeros, all ones, checkerboard and
checkerboard bar. The results of this testing showed that all circuit functional blocks
(control circuits, addressing, data I/O, write 0/1, and sense amp) performed as designed.
All four of the array configurations present on the chip showed functional memory
elements, i.e., memory cells could be programmed to zero or one and subsequently read
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out. As more packaged parts become available, more exhaustive test patterns will be
employed for full characterization. The five send-ahead devices were also used for
determining the optimum bias points of the three externally adjustable parameters: write
0 drive current, write 1 drive current, and the sense amp switching point. An Integrated
Measurements Systems XTS-Blazer tester was used to provide stimulus and measure
response curves. A wide range of load conditions was chosen based on the measurements
performed at wafer test. A family of drive current vs. bias voltage curves was constructed
for both on-chip programming drive circuits across various values of RDYNAMIC.
These curves validate design simulations and demonstrate adequate operating range of
each of the circuits. Likewise, a family of switching point curves was generated at
various RSET and RRESET values using the standalone sense amp built onto each die.
These curves were used to determine the optimal sense amp DC bias point for the test
chips and demonstrated the ability of the sense amp to distinguish the 0 and 1 state within
the range of chalcogenide resistance values measured at wafer test.
I-V CHRACTERISTICS
The figure above shows I‐V characteristics of the OUM device. At low
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voltages, the device exhibits either a low resistance (~1k) or high resistance (>100k),
depending on its programmed state. This is the read region of operation. To program the
device, a pulse of sufficient voltage is applied to drive the device into a high conduction
“dynamic on state”. For a reset device, this requires a voltage greater than Vth. Vth is the
device design parameter and for current memory application is chosen to be in the range of
0.5 to 0.9 V. to avoid read disturb, the device read region as shown in the figure, is well
below Vth and also below the reset regime.
The device is programmed while it is in the dynamic on state. The final
programmed state of the device is determined by the current amplitude and the pulse
duration in the dynamic on state. The reciprocal slope of the I‐V curve in the dynamic on
state is the series device resistance.
R-I CHARACTERISTICS
The above figure shows the device read resistance resulting from
application of the programming current pulse amplitude. Starting in the set condition,
moving from left to right, the device continues to remain in SET state as the amplitude is
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increased. Further increase in the pulse amplitude begins to reset the device with still
further increase resetting the device to a standard amorphous resistance. Beginning again
with a device initially in the RESET state, low amplitude pulses at voltages less than Vth
do not set the device. Once Vth is surpassed, the device switches to the dynamic on state
and programmed resistance is dramatically reduced as crystallization of the material is
achieved.
Further increase in programming current further crystallizes the material, which drops the
resistance to a minimum value. As the programming pulse amplitude is increased further,
resetting again is exhibited as in the case above. Devices can be safely reset above the
saturation point for margin. Importantly, the right side of the curve exhibits direct
overwrite capability, where a particular resistance value can be obtained from a
programming pulse, irrespective of the prior state of the material. The slope of the right
side of the curve is the device design parameter and can be adjusted to enable a multi‐ state
memory cell.
TECHNOLOGY & PERFOMANCE
The figure below shows device resistance versus write pulse width. The
reset resistance saturates when the pulse width is long enough to achieve melting of the
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phase change material. The set pulse adequately crystallizes the bit in 50 ns with a
RESET/SET resistance ratio of greater than 100.
TECHNOLOGY CAPABILITIES
Direct write capability (no erase before write) as well as byte function (no block flash
erase) makes it RAM like, easing significantly system implementation
 For flash, changing a byte involves saving the current data, erasig a whole block
(>100 mSec) and writing back old data + new byte (total ~1 sec)
 For PCM, changing a byte involves writing the new data: (total < 100 nSec, can be
less than 50 nSec with new alloy)
 Demonstrated endurance of 1013 cycles.
With read current > 10 μA, read speed is expected to be comparable to NOR and
DRAM
 The device has an excellent life as failure occurrence is negligible.
OUM: A MEMORY FOR EVERYBODY
Even though Phase Change Memory (OUM) is not an universal memory in all respects, it
comes close to an universal memory on how it can be used.
 For embedded with the smallest amount of process change, one can get a high cycle
EEPROM equivalent at lower cost.
 By using the same process but changing the alloy, one can get a high temperature
memory suitable for the most demanding automotive application.
 For dedicated high density memory, one can get a memory cell that is smaller than
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DRAM and has multi‐level cell capability.
 Using high performance alloys, programming speed similar to DRAM are available.
 Using special switched selectors, one can get multi‐layer memory than can rival
NAND memory in cost.
ADVANTAGES
Cost/Bit reduction: Small active storage medium
 Small cell size – small die size
 Simple manufacturing process – low step count
 Simple planar device structure
 Low voltage – single supply
 Reduced assembly and test costs
Near Ideal Memory Quality: Non-volatile
 High endurance – >1013 demonstrated
 Long data retention – >10 years
 Static – no refresh overhead penalty
 Random accessible – read and write
 Direct overwrite capability
 Large dynamic range for data (>40X)
 Actively driven digit-line during read
 Good array efficiency expected
 No memory SER – RAD hard
 No charge loss failure mechanisms
 High switching speed
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 Non-destructive read
Highly Scalable: Performance improves with scaling
 Only lithography limited
 Low voltage operation
 Multi-state demonstrated
 3D multi-layer potential with thin films
 Higher Density, Ease of Integration.
Logic Process Compatible: Late low-temperature processing– Doesn’t compromise P-channel devices
 Adds 2 to 4 mask steps to conventional CMOS logic process with low topography
 Low-voltage operation
 Enables economic merged memory/logic
 Enables realistic System-On-a-Chip (SOC) products: – Logic/Non-volatile
memory/Data memory/Linear
Radiation Immunity:One very important advantage offered by OUM over other conventional
memory types, is irradiation immunity. FLASH memory stores the bits in the form of
connections between the floating gate and the control gate. FLASH which is otherwise
nonvolatile, can loose its data in the presence of radiations which are very common
considering Medical and Space applications. The memory element is exposed to ionizing
radiation which have the ability to eject an electron thereby causing disruption of the links
which form the basis of memory storage in the flash memory. OUM however offers the
distinctive advantage over all other memory types owing to its Radiation Immunity
characteristics. As the bits are not stored in form of charge or links but in form of two
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definitive phases, Crystalline and amorphous, which are seldom affected by the presence of
High energy radiations. Hence OUM can be safely employed in all Medical and Space
application.
3-D NATURE (similar to polymer memory)
Another important characteristic of OUM is that like its counterpart Polymer memory, the
OUM can also be grown in 3 dimensions thereby offering even high density using a small
area.
RISK FACTORS
 Reset current < min W switch current
 Standard CMOS process integration
 Alloy optimization for robust high temp operation and speed
 Endurance testing to 1014–DRAM
 Defect density and failure mechanisms
5.3 TECHNOLOGY CHALLENGES
 Reduction of programming current for lower voltage and lower power operation.
 Increased set/reset resistance and decreased read current/set current margin with
scaling → impact on read performance/margin.
 Management of proximity heating with declining cell space → disturb risk.
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CONCLUSION
Unlike conventional flash memory Ovonic unified memory can be randomly addressed.
OUM cell can be written 10 trillion times when compared with conventional flash
memory. The computers using OUM would not be subjected to critical data loss when the
system hangs up or when power is abruptly lost as are present day computers using DRAM
a/o SRAM. OUM requires fewer steps in an IC manufacturing process resulting in reduced
cycle times, fewer defects, and greater manufacturing flexibility. These properties
essentially make OUM an ideal commercial memory. Current commercial technologies do
not satisfy the density, radiation tolerance, or endurance requirements for space
applications. OUM technology offers great potential for low power operation and radiation
tolerance, which assures its compatibility in space applications. OUM has direct
applications in all products presently using solid state memory, including computers, cell
phones, graphics-3D rendering, GPS, video conferencing, multimedia, Internet networking
and interfacing, digital TV, telecom, PDA, digital voice recorders, modems, DVD,
networking (ATM), Ethernet, and pagers. OUM offers a way to realize full system-onachip capability through integrating unified memory, linear, and logic on the same silicon
chip.
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REFERENCES
1. www.intel.com
2. www.ovonyx.com
3. www.baesystems.com
4. www.aero.org
5. IEEE SPECTRUM
6. www.wikisedia.com
7. www.pediain.com
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