Download 100390 Low Power Single Supply Hex ECL-to

100390
Low Power Single Supply Hex ECL-to-TTL Translator
General Description
Features
The 100390 is a hex translator for converting F100K logic
levels to TTL logic levels. Unlike other level translators, the
100390 operates using only one a 5V supply. Differential
inputs allow each circuit to be used as an inverting, noninverting, or differential receiver. An internal reference generator provides VBB for single-ended operation. The standard FASTÉ TRI-STATEÉ outputs are enabled by a common active low TTL compatible OE input. Partitioned VCCs
on chip are brought out on separate power pins, allowing
the noisy TTL VCC power plane to be isolated from the relatively quiet ECL VCC. The 100390 is ideal for applications
limited to a single a 5V supply, allowing for easy ECL to TTL
Interfacing.
Y
Y
Y
Y
Operates from a single a 5V supply
TRI-STATE outputs
2000V ESD protection
VBB supplied for single-ended operation
Logic Symbols
Pin Names
TL/F/10897 – 1
D0 –D5
D0 –D5
Q0 –Q5
OE
VBB
Description
Data Inputs (PECL)
Inverting Data Inputs (PECL)
Data Outputs (TTL)
Output Enable (TTL)
Reference Voltage (PECL)
Connection Diagrams
24-Pin DIP/SOIC
28-Pin PCC
24-Pin Quad Cerpak
TL/F/10897 – 3
TL/F/10897 – 4
TL/F/10897–2
FASTÉ and TRI-STATEÉ are registered trademarks of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/10897
RRD-B30M105/Printed in U. S. A.
100390 Low Power Single Supply Hex ECL-to-TTL Translator
July 1993
Logic Diagram
Detail
TL/F/10897 – 11
TL/F/10897–5
Truth Table
Data
Inputs
(PECL)
Control
Input
(TTL)
TTL
Outputs
Dn
Dn
OE
Qn
X
L
H
L
H
OPEN
L
H
VBB
VBB
VBB
OPEN
X
H
L
L
H
OPEN
VBB
VBB
L
H
OPEN
VBB
H
L
L
L
L
L
L
L
L
L
L
L
Z
L
H
U
U
U
L
H
H
L
H
L
Comments
Outputs Disable
Differential Operation
Differential Operation
Invalid Input States
Invalid Input States
Invalid Input States
Single Ended Operation
Single Ended Operation
Single Ended Operation
Single Ended Operation
Single Ended Operation
Single Ended Operation
H e HIGH Voltage Level
L e LOW Voltage Level
Z e HIGH Impedance
U e Undefined
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage Applied to Output
in High State (with VCC e 0V)
TRI-STATE Output
Storage Temperature
Current Applied to Output
in Low State (Max)
b 65§ C to a 150§ C
Maximum Junction Temperature
Ceramic
Plastic
a 175§ C
a 150§ C
VCC Pin Potential to
Ground Pin
2000V
Recommended Operating
Conditions
b 0.5V to a 7.0V
Case Temperature
Supply Voltage
b 30 mA to a 5.0 mA
b 5.0 mA to a 1.0 mA
GND to ECL VCC a 0.5V
VCC Differential
ECL VCC to TTL VCC
Twice the Rated IOL (mA)
ESD Last Passing Voltage (Min)
b 0.5V to a 7.0V
TTL Input Voltage (Note 2)
TTL Input Current (Note 2)
VBB Output Current
ECL Input Potential
b 0.5V to a 5.5V
0§ C to a 85§ C
a 4.75V to a 5.25V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
b 1.0V to a 1.0V
DC Electrical Characteristics ECL VCC e a 5.0V g 5%, TTL VCC e a 5.0V g 5%, GND e 0V
Symbol
Parameter
Min
VIH
Input HIGH Voltage
Data
VIL
Input LOW Voltage
Data
VBB
OE
Max
ECL VCC b 1.165
ECL VCC b 0.870
2.0
Units
Conditions
V
Guaranteed HIGH Signal for ALL
Inputs (with One Input Tied to VBB)
V
Guaranteed HIGH Signal (TTL)
V
Guaranteed LOW Signal for ALL
Inputs (with One Input Tied to VBB)
ECL VCC b 1.830
ECL VCC b 1.475
0.8
V
Guaranteed LOW Signal (TTL)
Output Reference Voltage
ECL VCC b 1.38
ECL VCC b 1.26
V
IBB e 0.0 mA or b1.0 mA
VOH
Output HIGH Voltage (TTL)
2.7
VOL
Output LOW Voltage (TTL)
IIH
Input HIGH Current
IIL
Input LOW Current
IBVI
Input Breakdown Current
ICBO
Input Leakage Current
IOZH
TRI-STATE Current
Output HIGH
50
mA
VOUT e a 2.7V
IOZL
TRI-STATE Current
Output LOW
b 50
mA
VOUT e a 0.5V
ICC
ECL Supply Current
13
30
mA
ICCZ
TTL Supply Current
10
20
mA
TRI-STATE
ICCL
TTL Supply Current
8
17
mA
Low State
ICCH
TTL Supply Current HIGH
0.4
2.0
mA
HIGH State
b 150
b 60
mA
VOUT e 0.0V, VCC e a 5.25
mV
Required for Full Output Swing
OE
V
IOH e b3 mA
0.5
V
IOL e 24 mA
50
mA
VIN e VIH(Max), D0 –D5 e VBB,
D0 –D5 e VIL(Min)
OE
20
mA
VIN e 2.7V (TTL)
OE
b 200
mA
VIN e 0.5V (TTL)
10
mA
VIN e 7.0V (TTL)
mA
VIN e GND, D0 –D5 e VBB
D0 –D5 e VIL(Min)
Data
OE
b 10
IOS
Output Short-Circuit Current
VDiff
Differential Input Voltage
150
VCM
Common Mode Voltage
ECL VCC b 2.0
VCD
Clamp Diode Voltage
3
ECL VCC b 0.5
V
b 1.2
V
IIN e b18 mA
DIP AC Electrical Characteristics
VCC e 5.0V g 5%; TC e 0§ C to a 85§ C
Symbol
TC e 0§ C
Parameter
Min
Max
TC e a 25§ C
TC e a 85§ C
Min
Min
Max
100
Units
Max
100
Fig.
No.
FMAX
Maximum Clock Frequency
100
tPLH
tPHL
Propagation Delay
Data to Output
MHz
3.5
7.2
3.5
6.8
3.5
6.7
ns
1
tPZH
tPZL
Output Enable Time
2.7
2.4
4.8
4.0
2.7
2.4
4.8
4.0
3.0
2.6
5.1
4.2
ns
2
tPHZ
tPLZ
Output Disable Time
2.9
2.3
5.8
3.9
2.9
2.2
5.4
3.9
2.7
2.2
5.1
3.9
ns
2
Units
Fig.
No.
SOIC, Cerpak and PCC Package AC Electrical Characteristics
VCC e 5.0V g 5%; TC e 0§ C to a 85§ C
Symbol
TC e 0§ C
Parameter
Min
Max
TC e a 25§ C
TC e a 85§ C
Min
Min
Max
100
Max
FMAX
Maximum Clock Frequency
100
tPLH
tPHL
Propagation Delay
Data to Output
100
MHz
3.5
7.0
3.5
6.6
3.5
6.5
ns
1
tPZH
tPZL
Output Enable Time
2.7
2.4
4.6
3.8
2.7
2.4
4.6
3.8
3.0
2.6
4.9
4.0
ns
2
tPHZ
tPLZ
Output Disable Time
2.9
2.3
5.6
3.7
2.9
2.2
5.2
3.7
2.7
2.2
4.9
3.7
ns
2
Switching Waveforms
TL/F/10897 – 6
FIGURE 1. Data to Output Propagation Delay
TL/F/10897 – 10
FIGURE 2. Enable/Disable Propagation Delay
4
Test Circuit
TL/F/10897 – 7
FIGURE 3. AC Test Circuit
Notes:
GND e 0V, ECL VCC e a 5V, TTL VCC e a 5V
L1 and L2 e equal length 50X impedance lines
50X terminators are internal to S/H measurement unit
Decoupling 0.1 mF from GND to ECL VCC and TTL VCC
All unused outputs are loaded with 500X to GND
CL e Fixture and stray capacitance e 50 pF
Switch S1 is open for tPLH, tPHL, tPHZ and tPZH tests
Switch S1 is closed only for tPLZ and tPZL tests
Application Notes
4. Undefined output states can occur for some invalid combinations. See Truth Table. This should be avoided to
prevent possible oscillation or increased power consumption due to TTL outputs biased into a quasi state
with both pullup and pulldown stages partially on. TRISTATEing the outputs will counteract the effects of invalid input states.
5. Pins 8, 15, and 22 on the 28-pin PCC package are tied to
the chip’s substrate and are named GNDs. These pins
are electrically common to the ground pins 1, 2, and 28.
For best thermal performance, tie the GND pins to the
circuit ground plane. They may be tied to an electrically
isolated thermal dissipation plane or may float.
6. Figure 4 illustrates typical differential input operation.
1. Device performance will be enhanced by the use of dual
VCC power planes as illustrated in the Application Figures 4 and 5. This will minimize the coupling of TTL
switching noise into the primary reference to the ECL
circuitry and take full advantage of the 100390’s on chip
VCC partitioning.
2. The device’s partitioned VCC may be operated from two
5V, 5% tolerance, supplies provided that they are
ramped up/down together so that the max differential is
1V. This is to prevent overstress to internal ESD diodes.
If the ECL driver to the F390 is powered from a separate
supply, it must obey this sequence rule also.
3. Glitch-free power up, independent of Data input levels, is
achieved if TTL logic HIGH is held on the Output Enable
pin during ramping up/down of the VCC supply.
7. Figure 5 illustrates typical single-ended input operation.
5
Application Notes (Continued)
TL/F/10897 – 8
FIGURE 4
TL/F/10897 – 9
FIGURE 5
Ordering Information
The device number is used to form part of a simplified purchasing code where a package type and temperature range are
defined as follows:
100390
Device Number (Basic)
D
C
QB
Special Variation
QB e Military Grade Device
with Environmental
and Burn-in Processing
Package Code
D e Ceramic Dual-In-Line
F e Quad Cerpak
Q e Plastic-Leaded Chip Carrier (PCC)
P e Plastic DIP
S e Small Outline (SOIC)
Temperature Range
C e Commercial (0§ C to a 85§ C)
M e Military (b55§ C to a 125§ C)
6
Physical Dimensions inches (millimeters)
24-Lead Ceramic Dual-In-Line Package
(0.400× Wide) (D)
NS Package Number J24E
7
Physical Dimensions inches (millimeters) (Continued)
24-Lead Molded Package
(0.300× Wide) (S)
NS Package Number M24B
24-Lead Plastic Dual-In-Line Package (P)
NS Package Number N24E
8
Physical Dimensions inches (millimeters) (Continued)
28-Lead Plastic Chip Carrier (Q)
NS Package Number V28A
9
100390 Low Power Single Supply Hex ECL-to-TTL Translator
Physical Dimensions inches (millimeters) (Continued)
24-Lead Quad Cerpak (F)
NS Package Number W24B
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