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Proposed Architecture for Low Power and Area
Efficient Edge Combiner
Sohaib A. Qazi1, Syed Asmat Ali Shah, Saad Arslan
CAST Department, COMSATS Institute of Information Technology Islamabad, Pakistan
[email protected], phone:+92 345 507 6730
1
Abstract— This paper proposes an architecture of edge combiner
circuit that consumes very low power as compared to a
conventional XOR edge multiplier design. The proposed edge
combiner's architecture is well suited for frequency multiplier
applications and it is tested for input frequencies of up to
250MHz. The design is implemented on 65nm complementary
metal oxide semiconductor (CMOS) process. Simulation results
show that the total power consumption of proposed design is 7.68
times less than the total power of conventional XOR edge
combiner. The switching power of proposed design is only 8% of
the total power which was 25% in conventional edge combiner.
Area of the edge combiner is 7.8nm i.e. 3.33 times less than the
XOR edge combiner.
Index Terms— Edge Combiner, Delay Locked Loop (DLL),
Frequency Multiplier, Phase Detector, Complementary Metal Oxide
Semiconductor (CMOS).
I.
INTRODUCTION
Advancement in the field of digital design and mixed signal
systems has resulted in increased bandwidth requirements for
digital and very large scale integration (VLSI) equipment. High
bandwidth operations also require relatively high frequency.
The efficient and low jitter clock generators play an important
role in high speed VLSI, digital and analog applications. Onchip clock generator circuits are very commonly used now-adays as they provide in-phase on-board clock signals which are
more effective than off-board clocks.
Historically, Phase Locked Loops (PLLs) were used for
high performance in high speed microprocessors. The biggest
hurdles that PLLs are facing these days are complexity and
cost. The PLLs use voltage controlled oscillator which makes
PLL a higher order system. The higher order systems are hard
to design for low power and area efficient applications [1].
Digital phase locked loops (DLLs) emerged as a viable
alternative to traditional PLLs [2] [3]. The DLLs have now
been adopted widely as they have considerable advantages over
conventional PLLs. The DLLs are first order systems and are
easier to design. The first order systems are preferred as theses
are stable systems [4]. Moreover, DLL has a limited locking
range as compared to PLLs [3].
Research in the area has proposed many improvements in
DLLs, but there is still room for improvement. C. Kim, et.al
has proposed a phase detector with reset feature added and a
new frequency multiplication technique in [4]. The frequency
multiplier proposed in [4] has timing issues in switching of
transistors, i.e. the transistors being in cutoff region or in linear
region. The transistors are not turned on (linear region)
simultaneously as one NMOS transistor is in direct contact
with the input signal and the other has a delay of three gate
cycles, so the data transfer through the transistors will be
corrupted in some cases. A frequency multiplier for Systemon-Chip (SoC) applications is proposed by K. H. Cheng et.al in
[5]. As the design proposed in [5] avoids the use of LC tanks so
it is claimed that the design consumes less area and power.
However, the edge combiner circuit design used in [5]
consumes considerable area because of the buffers, SR latches
and OR gates that are used in the design. A research conducted
at university of California by G. Chien and P. R. Gray has
proposed a DLL based oscillator for personal communication
systems [6]. LC tanks are used at the outputs, to enhance the
output impedance, consuming large area; LC tanks are not a
viable solution for small area and low power applications. P. C.
Huang et.al [7] has proposed a phase error calibration DLL
with edge combiner. The edge combiner proposed in [7] is
based on symmetric AND gates so it consumes more area than
the architecture proposed in this article. The design proposed in
this article is optimized for area and power.
The article is divided in following sections. The next
section, i.e. second section describes the conventional DLL
multiplier. The third section describes the proposed
architecture. Section four is composed of the simulation results,
comparison of conventional and proposed edge combiner and
the final section i.e. section five concludes the discussion on
the proposed architecture.
Figure 1: System diagram of DLL based Frequency Multiplier
Figure 2: Conventional Edge Combiner Circuit that is Implemented using
XOR Gates
Sohaib A. Qazi|Introduction
45
II.
CONVENTIONAL DLL MULTIPLIER
The increase in frequency of operation has also emphasized on
the importance of circuits that are helpful in providing reduced
skew and jitter. In analog, digital and mixed signal circuits
where delay is an important factor to be considered on receiver
end, skew plays an important role. Skew and jitter must be
minimized to achieve desired results. The Digital Locked Loop
(DLL) based frequency multiplier shown in Figure 1 is an
applicable solution to provide on chip reduced jitter and skew
clocks for the analog, digital and mixed signal circuits. As the
name suggests, this DLL based frequency multiplier is also
helpful in providing in-phase clocks of different frequencies to
the same circuit. DLL frequency multiplier can reduce skew
and jitter problems quite significantly. Also, the circuit can be
used for frequency multiplication besides reduction in skew
and jitter.
Phase Detector (PD), shown in Figure 1, detects the
difference in phase of reference clock and the Voltage
Controlled Delay Line’s (VCDL) output. The output of PD (up
and down signals) indicates whether the phase is leading or
lagging. The charge pump is controlled by the phase detector’s
output. The amount of current produced by the charge pump
depends upon the outputs of PD. The VCDL consists of
differential voltage-controlled inverter stages. When the phase
of reference input signal and the output of delay line is locked,
the VCDL generates equally spaced clock phases within one
clock period. The edge combiner of Figure 1 generates the
multiplied version of the reference clock.
multiplied frequency depends upon the phase difference of the
input clocks [8].
The conventional edge combiner is based on XOR gates.
The multiplication factor of four is achieved by eight different
phase signals. All these phase signals are combined in such a
way that it ends up in multiplying the phase signals four times
the original reference clock [9].
In order to achieve the multiplication factor of M, we need
2 × M different phase clocks from the delay line shown in
Figure 1. The edge combiner is needed to combine these
phases in such a way that we get a frequency M times the
1
reference frequency. Each stage is delayed in phase by
2×𝑀
times the input signal. Here M is the number with which the
reference signal will be multiplied, resulting in a delay of 0.125
time units of the input signal when M is set to four. This
architecture requires 6 XOR gates and a single 2-input OR
gate. The schematic design of an XOR gate is shown in Figure
3. In architecture of Figure 3, 16 PMOS and NMOS transistors
are used for implementation of a single XOR gate. This is quite
high number of transistors for designing an XOR gate as
compared to the design proposed in this article. Similarly OR
gate, shown in Figure 4, also consumes 6 PMOS and NMOS
gates. So an XOR edge multiplier design consumes 51 NMOS
and 51 PMOS gates. Since the edge combiner operates with a
large number of transistors, so the area and power consumption
is quite high.
Figure 5: Relation Between Reference Signal and Delayed Input Signals of
Edge Combiner
Figure 3: Transisitor Schematic of a Single XOR Gate Showing all
Transistors Used.
Figure 6: Output Clock is Compared with Reference Input Clock
III.
Figure 4: Transistor Level Schematic of OR Gate
Edge combiner is a vital part of the DLL frequency
multiplier as it is used to combine inputs of different phase
clocks and generate an output with higher frequency. The
PROPOSED EDGE COMBINER
The proposed architecture only involves four AND gates
and a single OR gate. To achieve a multiplication factor of
four, the VCDL of Figure 1 should produce eight different
phase signals, because the output depends on Equation 1.
𝑂𝑢𝑡𝑝𝑢𝑡𝑐𝑙𝑘 = 𝑅𝑒𝑓𝑒𝑟𝑒𝑛𝑐𝑒𝑐𝑙𝑘 ×
𝑁
(1)
2
Here ’N’ represents number of phases that are required to
generate desired output. According to Equation 1, eight clocks
Sohaib A. Qazi|Conventional DLL Multiplier
46
are required to achieve four times the input reference
frequency. Figure 5 shows the behavior of input reference
clock signal and the delayed phase clocks that are required to
generate output signal. These eight delayed clock signals must
occur within one clock cycle of the reference clock as shown in
Figure 5.
TABLE I.
POWER AND AREA COMPARISON OF AND & XOR BASED
EDGE MULTIPLIER
Area
(nm)
7.8
These 8 delayed clocks should be manipulated in such a
𝑇 𝑇
3𝑇
way that it results in 4 rising edges at 0, , and
of the
4
2
4
𝑇 3𝑇 5𝑇
original reference clock and the falling edges occur at ,
and
7𝑇
8
8
8
,
8
, respectively, as shown in Figure 6.
This paper proposes an architecture that produces a
behavior that was described in Figure 6. The architecture
required for producing the behavior shown in Figure 6 is
described in Figure 7. The proposed architecture includes four
AND gates and a single OR gate. This architecture requires
less number of Metal Oxide (MOS) gates as compared to the
architecture presented in [8]. The only problem with this
proposed architecture is its sensitivity towards the power
supply. This issue can be resolved by using linear regulators,
active and passive filters and differential circuits [10]. Area and
power consumption is a major concern when working to reduce
the power supply interference. The architectures must be
chosen accordingly to reduce area and power.
Power
(µW)
XOR Edge
Multiplier
26
Cell Internal Power
1.432
8.991
Net Switching Power
0.123
2.947
Total Internal Power
1.555
11.938
𝑇
To achieve the rising edges at prescribed location, i.e. 0, ,
𝑇 3𝑇
4
𝑇 3𝑇 5𝑇 7𝑇
,
and falling edges at , , , , the delayed signals are
2 4
8 8
8 8
fed to the AND gates in a specific order.
The order of the signals fed to the AND gates are shown in
Figure 7. The combinations used for AND gates’ input are
first/sixth phase, third/eighth phase, second/fifth and
fourth/seventh phase. Finally, the OR gate combines the output
pulses of AND gates and produces an output as shown in
Figure 8. The AND gates produce rising and falling edges at
𝑇
𝑇 3𝑇
𝑇 5𝑇
3𝑇 7𝑇
(0, ), ( ), ), ( , ) and ( , ).
8
4
8
2
8
IV.
Figure 7: Proposed Edge Combiner Circuit is Implemented using AND Gates
AND Edge
Multiplier
Power
4
8
SIMULATION RESULTS
The simulations are carried out in ModelSim, a tool by
Mentor Graphics. The reference clock frequency used was
250MHz and the output frequency obtained from edge
multiplier was 1GHz. The simulation results are shown in
figure 9. The figure 9 indicates the input clock of 40ns which
corresponds to 250MHz frequency. The functionality of both
architectures is same which is indicated by signals
"f_out_and" and "f_out_xor" in Figure 9. The frequency of
output signals is 1GHz which is four times the input frequency
of the edge combiner. The proposed edge multiplier is
implemented using 65nm CMOS technology. Power and area
consumption is estimated using Design Vision, a tool from
synopsys. The supply voltage for the design is 1 Volt.
Figure 8: Multiplication Principle for Edge Multiplier
Sohaib A. Qazi|/
47
Figure 9: Comparison of Conventional and Proposed Edge Combiner Results in ModelSim
The total power consumption of the design proposed is
1.5551μW (reduced by 7.68% of the power that was consumed
by the conventional XOR multiplier). The power consumption
of the design is estimated using the design compiler from
Synopsys.
The total power consumed in design is shown in Table I.
Switching power is another main concern for the designers to
look for. The design proposed in this article reduces the
switching power quite significantly. The conventional edge
multiplier’s switching power consumption is about 25% of the
total power, but the design proposed in this article consumes
only 8% of the total power for switching purpose.
The edge multiplier consumes only 7.8 units which is
about 3.33 times less than the XOR edge multiplier. The
comparison of area and power consumption is shown in Table
I.
V.
CONCLUSION
The proposed architecture is well suited for low power
applications as it consumes 7.68% less power than the
conventional XOR edge combiner. The edge combiner also
occupies very less area that is 3.33 times less than the
conventional edge combiner.
In future we are also looking forward to integrate this
architecture in a DLL frequency multiplier.
ACKNOWLEDGMENT
The authors would like to thank Mr. M. Touqeer Pasha at
Linkoping University, who provided assistance for edge
combiner.
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[1]
Sohaib A. Qazi|Conclusion
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