Download A comparison between the TTL and CMOS families of logic devices

Digital Fundamentals
Logic Family Interfacing
Supplement
Prepared by Mike Crompton (Revised 20 August 2008)
Logic Families
Over the years, the devices used to carry out logic functions have changed considerably.
An early family of devices were simple switches, which gave way to relays. These in turn
were superceded by diodes and eventually transistors. Transistor to Transistor Logic
(TTL) remained popular for a relatively long period of time and even today is favoured
for certain applications. The invention of Field Effect Transistors (FETs), and in
particular Complimentary Metal Oxide Semi-conductor Transistors (CMOS) FETs
changed basic logic design. The main advantage of CMOS over TTL was the very low
power consumption and small size. However the speed at which they could switch was
considerably slower and produced longer propagation delays. With time, TTL devices
that consumed much less power, and CMOS devices that could switch faster have blurred
the line between the two types, leaving size as the major difference.
The advent of personal computers and their ever increasing search for faster operating
speeds has probably had the greatest effect on choice of logic devices. Many more
operations per second, now exceeding 2000 million, have driven up the power
consumption and related heat dissipation problems. This led designers to reduce the
traditional 5 Volt logic High level to 3.5 Volts. Since power is V2/R, this achieved a 34%
decrease in consumption, but an increase in compatibility problems between the different
logic families. Minimum voltage levels of Highs and Maximum voltage levels of Lows
began to cross, and fall outside the Max/Mins of other device families. Since individual
pieces of equipment rarely have a mix of logic devices, this does not present any problem
for that particular equipment. However, inter connection between different pieces of
equipment using different logic families gives rise to serious incompatibilities.
Listed below are the various type of TTL and CMOS devices along with their history and
features.
TTL.
74XX series.
The original TTL series developed in the 1960s. Had a per gate propagation delay of 10
nano seconds, power consumption of 10mW and could feed (Fan-Out) up to 10 other
74XX gates. The min High I/P voltage is 2V and min High O/P is 2.4V. It’s max Lo I/P
voltage is 0.8V and max Lo O/P is 0.4V.
74SXX series.
The 10 nano second propagation delay of the 74XX series was the result of the transistors
in the gate saturating. When going to cut-off they were being held at saturation, for a
period, by internal capacitance. The inclusion of Schottky diodes prevented the
transistors from going to full saturation and reduced propagation delay by a factor of 4.
Unfortunately the power consumption doubled but the speed-power factor remained the
same. Speed–power factor is a figure of merit obtained by multiplying delay time by
power consumption and is expressed in picoWatts per Second (pW/Sec)
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74LSXX series.
Using different manufacturing techniques for integrating the transistors, and using higher
value of resistors reduced the power consumption of the 74S considerably (to about 2mW
per gate). 74LS series speed-power factor is only 1/3 of the 74S series and 1/5 of the
original 74 series. This series is still quite popular today and many of the logic devices in
the electronic technician’s parts kit are 74LS type.
74ALSXX and 74FXX series.
Improved isolation between internal transistors resulting in reduced size and therefore
reduced capacitance, has reduced propagation delays to <3 to 4 nano seconds, and power
dissipation to 1mW per gate.
ECL Series.
Emitter Coupled Logic is a special case of transistor logic. By altering the configuration
of the internal transistors to differential amplifiers, with coupled emitters, extremely short
propagation delays in the region of 0.8 nano-seconds can be achieved. This increase in
speed is at the expense of power consumption which goes up to 40mW per gate, or 20 to
40 times that of LS TTL or ALS TTL. ECL also uses –0.8V as a logic Hi and –1.7V as a
Lo, making interconnecting to other families more difficult.
CMOS.
4000 / 4000B series.
The original CMOS series offering very low power consumption and allowing battery
powered devices to become efficient alternatives. This series had little ‘static electricity’
protection, and was much slower than it’s TTL counterparts. They could operate with a
power supply voltage (VDD) of +3V to +15V. The min High level voltage is 2/3 VDD (the
supply voltage used) and max Lo level voltage is 1/3 VDD.
40H00 series.
Slight improvement in speed, but still much slower than TTL.
74C00 series.
This series was designed to be pin compatible with TTL, making direct replacement
possible. The speed, however, was still poor compared to TTL although the power
savings were considerable.
74HC00 and 74HCT00 series.
74HC is high speed CMOS, and 74HCT is high speed TTL compatible CMOS. Both
offer drastic improvements over their predecessors with speeds as fast as LS TTL and yet
still consuming less power when used at the same switching speeds. The HCT series also
has I/P and O/P voltage level compatibility with LS TTL. Further improvements have led
to the advanced series below.
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74AHC00 and 74AHCT00 series.
Basically improved versions of the HC and HCT series, with propagation delays reduced
to 1/3, power consumption to ½ and an increase of O/P drive current (improved fan-out).
This series is also available in a wide-bus version utilizing a 16 Bit I/O used in many
microprocessor applications.
74BiMOS series.
A hybrid series containing both TTL and CMOS components. By using the advantages,
and minimizing the disadvantages of each, optimum performance in speed, power
consumption, low I/P current requirements and high O/P current capabilities (Fan-Out) is
realized.
The following table lists the parameters of the most common families.
Type
Prop/Del
Power
Speed/Pwr Min Lvl Min Lvl Max Lvl Max Lvl
in nSec
mW
pW/Sec
Vin Hi Vout Hi Vin Lo
Vout Lo
74 ~
10
10
100
2V
2.4V
0.8V
0.4V
74S ~
3
20
60
2V
2.4V
0.8V
0.4V
74LS ~
9
2
18
2V
2.7V
0.8V
0.4V
74ALS~
4
1
4
2V
2.7V
0.8V
0.4V
1@1MHz
4000B *
105
105
3.3V
4.95V
1.67V
0.05V
1.5@1MHz
74HC *
10
15
3.5V
4.9V
1V
0.1V
74Bi ~*
2.9
.0003-7.5 .00087-22
2V
2.7V
0.8V
0.4V
ECL
0.8
40
32
-0.8V
-0.8V
-1.7V
-1.7V
~ = TTL Logic families * = CMOS Logic families ~* = TTL and CMOS Logic families
By checking the table, it can be seen that for a LS-TTL gate to drive (or feed into) a
CMOS gate there is a problem. The minimum level Hi O/P of the TTL is 2.7V and the
minimum level Hi I/P of the CMOS is 3.3V (or 3.5V for HC). Meaning the CMOS will
read the Hi O/P of the TTL as a Lo!! A simple circuit to correct this problem is shown
below right.
When the O/P of the TTL gate is supposed to
be Hi, the I/P to the CMOS gate will be
almost 5V. The I/P current of the CMOS gate
is so low (approx. 1A), there is almost no
current flow through the 10k resistor, and
therefore almost no voltage drop across it.
When the O/P of the TTL is Lo, the bottom
end of the 10k is basically at ground (0V)
and current ‘sink’ through the TTL gate is
5V/10k = 0.5mA. This is well within it’s
sink current capability of 16mA. You will
recognize this as a simple ‘pull-up’ resistor
circuit.
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Although not shown on the chart, maximum current ‘sinking’ or ‘sourcing’ capabilities
can also play a part in family mis-matching. Often when 4000B CMOS is required to
drive TTL, there is insufficient CMOS current (0.51mA when the O/P is Lo compared to
1.6mA I/P current for TTL). To overcome this problem, special ‘buffer’ CMOS devices
have been designed to enable up to 10 LS-TTL devices to be driven from one CMOS.
See the circuit below.
Example of a CMOS
Buffer being used to
allow a CMOS gate
drive 3 TTL gates.
Another problem can be encountered when different supply voltages are used for
different families. You will recall that the 4000B CMOS family can operate with a supply
voltage of up to 15V, and the maximum Hi and Lo O/Ps are 2/3 and 1/3 of VSUPPLY
respectively. This requires that the Hi and Lo values have to be ‘level shifted’ down for
CMOS driving TTL or up for TTL driving CMOS. Two Level Shifter devices to
accomplish this are the 4050B (shift down) and 4504B (shift up). The 4050B is the same
buffer used for current incompatibilities above.
The upper diagram shows step
down level shifting from 15V
CMOS to 5V TTL.
The lower diagram shows step up
level shifting from 5V TTL to
15V CMOS.
You may not be required to remember all the incompatibilities between the different
logic families, but you will be expected to be aware of their existence and to be able to
refer to the appropriate specification sheets or reference material when inter-connecting.
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