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Run Anywhere
The Hardware Platform Perspective
Ben Pollan, AMD Java Labs
October 28, 2008
Agenda
Java Labs Introduction
Community Collaboration
Performance Optimization Recommendations
Leveraging the Latest Hardware Improvements
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AMD Java Labs
Dedicated AMD Java Labs organization supports Java
development community through
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AMD and Java Relationship
Java Platform Performance Trends on x64
SPECjbb2005 on AMD “Barcelona” processor
Data obtained from Sun Microsystems. Results not verified by AMD.
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Community Collaboration
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Contribution Areas
Open Source
OpenJDK: contributing performance
enhancements
CodeSleuth: Java profiling plug-in for Eclipse,
released as open source project on
sourceforge.net
Collaboration with proprietary JVM vendors
Performance optimizations to leverage hardware
features
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Pursuing Optimizations For:
More efficient use of hardware features
Instruction selection
– Convert integer to double, float to double, shift by
constants
Improve cache efficiency
– Hashmap: common case usage improvements
– BigDecimal: class size reductions
– Field reordering / removal
Improved performance / profiling data
JVMTI: allow tools to track JITed method inlining
Performance data via Instruction Based Sampling
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Hashmap Optimization
Hashmap.get
Leading cause of cache misses
Statistics showed common use pattern
Hashmap.put(int i, object); // where i < #
elements
…
Hashmap.get(int i);
Solution
For this case, implement hashing functions and
buckets as an array lookup
Touches less memory, causing fewer cache misses
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JVMTI Method Inlining Information
Method address to source code mapping is a common
performance analysis task
Memory location->JITed code->bytecode->source
code
JVMTI’s CompiledMethodLoad callback returns information
to assist with this mapping
Broken…does not provide information for inlined
methods
OpenJDK extended to make inlining information available
via JVMTI
Tools writers can use this to produce better mapping
Within JVMTI specification (existing void pointer)
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Performance Optimization Recommendations
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Configuration Options - NUMA
Processors have their own local memory, which is less
costly to access
If running multiple JVMs per system, pin individual JVMs
to a processor
Windows: start /affinity xx java… where xx is
a mask specifying the cores the process will run on
Linux: numactl --cpunodebind=processor_num
--membind=processor_num java…
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Configuration Options – NUMA (cont.)
If running single JVM per system
Try node interleaved memory setting in BIOS
For Sun Solaris JVM, use –XX+UseNUMA
For IBM on Linux, heap automatically interleaved
Don’t do interleave both (cancels each other out)
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Configuration Options – Page Size
Page table maintains virtual to physical address mappings
Translation Lookaside Buffer (TLB) maintains cache
of these
With small page sizes, # of mappings can exceed cache
size, leading to (slower) page table access
For large (2M) page size system configuration
instructions, see article in AMD Java Zone:
Supersizing Java, parts 1 and 2
For those with even larger requirements, 1G Page support
submitted soon for OpenJDK
Only Solaris supports this for now
Working with Linux distributions for support
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Configuration Options – Page Size (cont.)
Sun:
-XX:+UseLargePages
-XX:LargePagesSizeInBytes=n (n=2M or 1G)
Oracle:
Determines if Large Pages are enabled in the
system, then enables their support in JVM
IBM:
-Xlp
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Configuration Options – Compressed References
For 64-bit OS and 64-bit JVM, object references stored on
the heap are 64-bits
Compressed references limit references to 32-bits, using
fewer heap resources
To use, your memory requirements must be lower than:
IBM: 25GB
Oracle: 4GB
Sun: 32GB
To enable:
IBM: -Xcompressedrefs
Oracle: -XXcompressedRefs
Sun: -XX:+UseCompressedOops
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Configuration Options - IBM
-Xtlhprefetch
Causes newly allocated area on the heap to be
prefetched with PREFETCHNTA
Prevents L2 processor cache from being polluted,
because when objects are removed from L1, they
aren’t moved to L2
Good to use when you have many short-lived
objects
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Leveraging the Latest Hardware Improvements
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AMD Hardware Advances
Increase in cores per processor
Balance workload between GPU and CPU
Instruction-based sampling (IBS)
Rich set of processor event data
Precisely associates event data with the instructions
that cause the event
JVMs can use this data to make dynamic optimization
decisions
Lightweight Profiling (LWP) Specification
Enable code to make dynamic decisions about how to
improve performance
Suggestions welcome: [email protected]
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AMD Hardware Advances
Advanced Synchronization Facility (ASF)
Experimental AMD64 extension
Lighter weight locking mechanism
Instruction optimizations
With each processor release
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Taking Advantage of Hardware Features
Upgrade to the latest JVMs
Many benefits you will get for free
– Instruction optimizations
– Profiling information, feedback
Use the Java Concurrency Classes
ParallelArray (JDK7) will take advantage of work that
will leverage multiple cores
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More Information at AMD Developer Central
•
•
•
Detailed technical articles
Documentation, tutorials,
and guides
Featuring tips to help
optimize software for AMD
“Barcelona” processors
•
•
•
•
AMD-optimized build tools
(Compilers, JITs)
Performance analysis tools
(AMD CodeAnalystTM
software)
Performance libraries –
AMD Core Math Library
(ACML) and Framewave
(open source)
•
•
Inside look at AMD’s vision
Community
discussions
Subscribe to our free newsletter:
developer.amd.com
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Java Zone on AMD Developer Central
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Disclaimer
The information presented in this document is for informational purposes only and may contain technical inaccuracies, omissions and
typographical errors.
The information contained herein is subject to change and may be rendered inaccurate for many reasons, including but not limited to product
and roadmap changes, component and motherboard version changes, new model and/or product releases, product differences between
differing manufacturers, software changes, BIOS flashes, firmware upgrades, or the like. AMD assumes no obligation to update or otherwise
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Trademark Attribution
AMD, the AMD Arrow logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. SPECjbb is a registered trademark of
Standard Performance Evaluation Corporation (SPEC). Other names are for informational purposes only and may be trademarks of their
respective owners.
© 2008 Advanced Micro Devices, Inc. All rights reserved.
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