Download Analog Design for Production

318-595 Capstone
Design
Analog Design for Production
Circuit Types and Analysis
DFM = Design for Manufacturing
1
DFR = Design for Reliability
318-595 Capstone
Design
Analog Design for Production
Linear Analog Circuit Blocks
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Amplifiers and Attenuators
Math Functions (add, subtract)
Oscillators (sinusoidal)
Filters
Voltage Regulators
Voltage References
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318-595 Capstone
Design
Analog Design for Production
Non-Linear Analog Circuit Blocks
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Comparators
Oscillators (non-sinusoidal, square, sawtooth, etc)
Voltage Limiters and Clamps
Rectifiers and Bridges
Math Functions (multiply, divide)
Log and other Non-linear Amplifiers
Sample and Hold Amplifiers
Envelope & Peak Detectors
Phase Detectors
Phased Locked Loops
Switching Voltage Regulators
3
318-595 Capstone
Design
Analog Design for Production
Passive Components
4
318-595 Capstone
Design
Analog Design for Production
Passive Components, R-L-C
Critical Factors:
1.
Ambient Temperature
2.
Thermal Deratings & Variation of Primary Parameter (Temp Co)
3.
Maximum Imposed Voltage and/or Current
4.
Maximum Imposed dV/dT and/or Frequency
5.
Inductive Frequency (high frequency model)
Minimum Analysis & Selection Considerations:
•
Primary Parameter Tolerances (R, L, C %)
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Total Power vs Package Dissipation
•
Maximum Voltage
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Composition, Specific die-electrics, construction, etc
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318-595 Capstone
Design
Analog Design for Production
Passive Discretes
• Resistors/Inductors: Must specify or account for Tolerance,
Power, Package and Temp Coefficient
– Derating Guide: ~50% of rated power or current
– Std Tolerances: 0.1%, 1%, 5%, 10% and 20%
– Constructional Anomalies: Max Voltage, Inductive with High Freq
• Capacitors: Must specify or account for Tolerance, WV,
Polarization, Dielectric, Temp Co and Package
– Derating Guide: ~50% of rated voltage
– Std Tolerances: 1%, 2%, 5%, 10%, 20%, 80%
– Constructional Anomalies: Charge Leakage, Inductive with High Freq,
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318-595 Capstone
Design
Analog Design for Production
Passive Component Specifications
Passive Discrete Specifications
Nominal
Adjustment
Value or
Range,
Max Value
%/Turn
Tolerance
Around
Nominal
Derated
Pow er
Capacity
Maximum
Working
Voltage
Maximum
Constant
Current
Maximum
Surge
Current
Composition Q Factor or
Dielectric or Frequency
Form
Variation
Package
Component
Resistor
Potentiometer
Fixed Capacitor
Variable Capacitor
Fixed Inductor
Variable Inductor
Key:
Mandatory
Recommended
Not Applicable
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318-595 Capstone
Design
Analog Design for Production
+
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Amplifiers
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318-595 Capstone
Design
Analog Design for Production
Small Signal Amplifiers
Critical Factors:
1.
Component Tolerances, particularly gain setting R’s
2.
OpAmp Input Offset Voltage (Vio), worse for high gain
3.
Input Bias Current (Ib), Input Offset Current (Iio)
4.
Finite Diff Gain (Ad) & Variation of Ad with Frequency
5.
Output Slew Rate and Output Vp-p at Maximum Frequency
Worst Case Analysis:
• Total DC Offset error in Volts (1,2,3)
• Total Gain Error vs Nominal, Converted to Volts (1,4)
• Power Bandwidth for Application (1,5)
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318-595 Capstone
Design
Analog Design for Production
Basic Gain in Voltage, Current or Combination
Linear Operation: No New Frequencies Created
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Voltage Amplifiers (Vin >> Vout):
Current Amplifiers (Iin >> Iout):
Transimpedance (Iin >> Vout):
Transconductance (Vin >> Iout):
Av = Vout/Vin
Ai = Iout/Iin
Zm = Vout/Iin
Gm = Iout/Vin
Additional Parameters
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Input Impedance: Zin = Vin/Iin
Output Impedance: Zout = {Vout(NL) – Vout(L)}/Iout
Slew Rate (SR): Min dVout/dT
Slew Rate BW = SR/2pVp where Vp = Peak Voltage
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318-595 Capstone
Design
Analog Design for Production
Operational Amplifier
Linear, Differential, High Gain Amplifier
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Advantages Over Single
Ended Amplifier Block ??
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• Easy to add positive and negative feedback with
differential input
• Single Ended Application Gains can be tightly controlled
with external components and made insensitive to
internal transistor gain variations
• Inherent noise rejection when noise enters both input
terminals
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318-595 Capstone
Design
Analog Design for Production
Basic Op-Amp Simplified
Implementation
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318-595 Capstone
Design
Analog Design for Production
Operational Amplifier
Ideal Assumptions
Vp
+
Vout
Vn
-
Used for basic analysis,
nominal gain analysis
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•
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Vout = Ad (Vp – Vn) where Ad is the diff gain
Ad = Infinite
Zin = Infinite, Iin = 0 where Iin is the input current
Vp = Vn because of infinite Ad, Vo may be non-zero
under this condition
• Iout = Infinite (Often a false assumption)
These basic assumptions allow simple circuit analysis to determine
Nominal gain applications
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318-595 Capstone
Design
Analog Design for Production
Operational Amplifier
Power Supplies
Vcc
Vp
+
Vout
Vn
-
Power Supplies can be a
critical consideration
-Vcc
• -Vcc < Vout < Vcc At all times, Vout(max) may be as low as 2 to
5 volts below Vcc depending upon model
• Vcc, -Vcc sometimes referred to as “Rails” due to power
distribution on some boards resembling tracks
• Many applications use “Split” supply Operation
• Split Supply means Vcc = |-Vcc|
• Some models characterized for 1 supply operation (but ALL will work there)
• Single Supply means –Vcc = 0
• Vcc, -Vcc power pins should always be capacitively filtered with
14
0.1uf (usually ceramic monolithic X7R or similar)
318-595 Capstone
Design
Analog Design for Production
Operational Amplifier
Classifications
15
318-595 Capstone
Design
Analog Design for Production
Operational Amplifier
Basic Applications
Rf
Ri
Vin
Vout
Rp
Av = - Rf/Ri
Zin = Ri
Inverting Voltage Amp
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318-595 Capstone
Design
Analog Design for Production
Operational Amplifier
Basic Applications
Ri
+
Vin
Vout
Rf
Rp
Av = 1 + Rf/Rp
Zin = Ri +
Non-Inverting Voltage Amp
When Rf=0, Rp=~Infinite…… Av = 1
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318-595 Capstone
Design
Analog Design for Production
Operational Amplifier
Basic Applications
Vin
+
Vout
-
Av = 1
Zin =
Unity Gain Voltage Amp
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318-595 Capstone
Design
Analog Design for Production
Operational Amplifier
Basic Applications
Ri
+
Vin
-
RL
Iout
Rp
Gm = 1/Rp
Zin = Ri +
Transconductance Amp
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318-595 Capstone
Design
Analog Design for Production
Operational Amplifier
Basic Applications
Rf
Iin
Vout
Zm = - Rf
RL
Transimpedance Amp
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318-595 Capstone
Design
Analog Design for Production
Operational Amplifier
Basic Applications
+
Iin
-
RL
Ri
Iout
Rp
Ai = -(1 + Ri/Rp)
Current Amplifier
21
318-595 Capstone
Design
Analog Design for Production
Operational Amplifier
Ideal Assumptions
Vp
+
Vout
Vn
-
Used for basic analysis,
nominal gain analysis
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•
•
•
Vout = Ad (Vp – Vn) where Ad is the diff gain
Ad = Infinite
Zin = Infinite, Iin = 0 where Iin is the input current
Vp = Vn because of infinite Ad, Vo may be non-zero
under this condition
• Iout = Infinite (Often a false assumption)
These basic assumptions allow simple circuit analysis to determine
Nominal gain applications
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318-595 Capstone
Design
Analog Design for Production
Operational Amplifier
Real Characteristics
Ip
Vp
+
Vn
-
Vio
In
Vout
Iout
Used for more accurate
Gain Characterization
• Vout = Ad(Vp – Vn) + Ac(Vp + Vn)/2 + Vio
Ad is the diff gain, Ac is the common mode gain, Vio = offset voltage
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CMRR = Common Mode Rejection Ratio = 20log(Ad/Ac)
Ib = Bias Current (Ave Current = [Ip + In]/2)
Iio = Offset Current (Diff Current = Ip – In)
Iout = Finite, Split between gain set components and load
Vio = Input Diff Voltage reflected back from Vo under the
condition the Vp = Vn = 0
Use superposition to understand contributions
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318-595 Capstone
Design
Analog Design for Production
Operational Amplifier
Real Characteristic Effects
Vp
Basic Strategy
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Vout
Vn
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Consider the Effect Separately, then combine results
Show Ib and Iio as input current sources
Show Vio as diff voltage on Vp-Vn
Use amended opamp in std application circuit, Vin=0
(grounded).
• Find Vout, all Vout will be Verror due to Offset and Bias
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318-595 Capstone
Design
Analog Design for Production
Inverting Configuration
Offset Error Contribution 1
Rf
Ri
If
Vout
Vio
Ii
Rp
Ii = (0-Vio)/Ri
If = (Vio-Vo)/Rf
Ii = If
Vo = Vio(1 + Rf/Ri) = Verr
Inverting Voltage Amp
Error Voltage due to Vio
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318-595 Capstone
Design
Analog Design for Production
Non-inverting Configuration
Offset Error Contribution 1
Ri
+
Vin
Vout
Vio
Rf
If
Ii
Rp
Ii = (0-Vio)/Rp
If = (Vio-Vo)/Rf
Ii = If
Vo = Vio(1 + Rf/Rp) = Verr
Non-Inverting Voltage Amp
Error Voltage due to Vio
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318-595 Capstone
Design
Analog Design for Production
Op-Amp Technologies (EDN)
Offset Voltage Comparisons
IO
27
318-595 Capstone
Design
Analog Design for Production
Op-Amp Technologies (EDN)
Input Bias Current
10 deg C
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318-595 Capstone
Design
Analog Design for Production
Inverting Amplifier
Offset Error Contribution 2
Rf
Ri
If
Vin
Vout
Iio
Ii
Ib
Ib
Rp
At V+: Iio = Ib + V+/Rp
V+ = Rp(Iio-Ib)
At V-: -V-/Ri = (V--Vout)/Rf + Ib + Iio
Sub V+ into above equation
Vo = Verr = Rf(Ib-/+Iio) - [((RfRp)/Ri + Rp)(Ib+/-Iio)]
Note if Iio = ~0 and Rp = Rf//Ri, then Verr = 0
Verr is always minimized when Rp = ~Rf//Ri
Inverting Voltage Amp
Error Voltage due to Ib, Iio
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318-595 Capstone
Design
Analog Design for Production
Non-Inverting Amplifier
Offset Error Contribution 2
Rf
Rp
If
Vout
Iio
Ip
Ib
Ib
Ri
At V+: Iio = Ib + V+/Ri
V+ = Ri(Iio-Ib)
At V-: -V-/Rp = (V--Vout)Rf + Ib + Iio
Sub V+ into above equation
Ii
Vin
Vo = Verr = Rf(Ib-/+Iio) - [((RfRi)/Rp + Ri)(Ib+/-Iio)]
Note if Iio = ~0 and Ri = Rf//Rp, then Verr = 0
Verr is always minimized when Ri = Rf//Rp
Non-Inverting Voltage Amp
Error Voltage due to Ib, Iio
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318-595 Capstone
Design
Analog Design for Production
Inverting Amplifier
Gain Error
Rf
Ri
Av (nom) = - Rf/Ri
But Assume Vout = Ad(V+ - V-)
If
Vin
Vout
Ii
Rp
Find expressions for V+ & VSubstitute into above Vout
Solve for Vout/Vin = Av
Av = -(RfAd)/(RiAd + Ri + Rf)
Av = Av(nom)/CF
CF = Correction Factor
CF = 1 + 1/Ad + Rf/(RiAd)
Don’t Forget to Factor in RTol% !
|Av| < |Av (nom)|
Inverting Voltage Amp
31
318-595 Capstone
Design
Analog Design for Production
Non-Inverting Amplifier
Gain Error
Ri
+
Vin
Vout
Av (nom) = 1+ Rf/Rp
But Assume Vout = Ad(V+ - V-)
Rf
Find expressions for V+ & VSubstitute into above Vout
Solve for Vout/Vin = Av
Rp
Av = Ad(Rp + Rf)/(RpAd + Rp + Rf)
Av = Av(nom)/CF
CF = Correction Factor
CF = 1 + 1/Ad + Rf/(RpAd)
Don’t Forget to Factor in RTol% !
|Av| < |Av (nom)|
Non-Inverting Voltage Amp
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318-595 Capstone
Design
Analog Design for Production
Operational Amplifier
Gain Error
Rf
Ri
If
Vin
Vout
Ii
Largest Error will be due to Rtol !!
Rp
Gain Error = Av(nom) – Av
Verr from Gain Error
Verr = Vin(max) * Gain Error
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318-595 Capstone
Design
Analog Design for Production
Total Error
• Verr due to Gain Error incl Resistor tolerance
• Verr due to Offset and Bias Effects
• Requirements may dictate an outright nominal gain plus
a total error voltage or current budget
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318-595 Capstone
Design
Analog Design for Production
Example
10K
5%
+
0.1V
Vout
TLO72C
-
10K
1%
1K
1%
• Find Overall Worst Case DC Error Voltage
Nominal Gain = 1+Rf/Ri = +11.0
Nominal Output = 1.1V
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318-595 Capstone
Design
Analog Design for Production
Analysis requires opamp data sheet info
10K
5%
+
0.1V
Vout
TLO72C
-
10K
1%
1K
1%
TL072C over 0-70C:
Ib(max) = 7nA
Iio(max) = 2nA
Vio(max) = 13mV
Avo(min) = 15000
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318-595 Capstone
Design
Analog Design for Production
Non-Inverting Amplifier
Gain Error
10K
5%
+
0.1V
Vout
TLO72C
-
10K
1%
Av (nom) = 1+ Rf/Rp = 11.0
Av (min)  Rf down 1%  9.9KW,
Rp up 1%  1.01KW
Av = Ad(Rp + Rf)/(RpAd + Rp + Rf)
1K
Av = Av(nom)/CF
CF = Correction Factor
CF = 1 + 1/Ad + Rf/(RpAd)
1%
Av(min) = 15K(1.01+9.9) / [(15K)(1.01) + 9.9 + 1.01] = 10.79
Error from nominal = 11.0 – 10.79 = 0.21  21mV
Av(max) = 15K(0.99+10.1) / [(15K)(0.99) + 10.1 + 0.99] = 11.19
Error from nominal = 0.19 = |11.0 – 11.19| = 0.19  19mV
Worst Case Gain Error assuming Vin = 0.1V = 19mV or 21mV
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318-595 Capstone
Design
Analog Design for Production
Non-inverting Configuration
Offset Error Contribution 1
10K
5%
+
0.1V
Vout
TLO72C
-
10K
1%
Verr1 = Vio(1 + Rf/Rp)
1K
1%
Verr1a(max) = 13mV(1 + 10.1/0.99) = 145.6mV
Verr1b(max) = 13mV(1 + 9.9/1.01) = 140.4mV
Worst Case Offset 1 Error = 145.6mV or 140.4mV
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318-595 Capstone
Design
Analog Design for Production
Non-Inverting Amplifier
Offset Error Contribution 2
10K
5%
+
0.1V
Vout
TLO72C
-
10K
1%
Verr2 = Rf(Ib-/+Iio) - [((RfRi)/Rp + Ri)(Ib+/-Iio)]
1K
1%
Verr2 = 10(7nA-/+2nA) – [(10)(10)/1 + 10](7nA+/-2nA)
Verr2 worst case = ~1mV
Worst Case Offset 2 Error = ~1mV
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318-595 Capstone
Design
Analog Design for Production
Total Error
• Verr due to Gain Error = 19.0mV
• Verr due to Offset 1 = 145.6mV
• Verr due to Offset 2 = 1mV
Answer: Worst Case Total Error = 165.6mV (when Rf = max, Rp = min)
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318-595 Capstone
Design
Analog Design for Production
Operational Amplifier
Gain vs Bandwidth Tradeoff
Rf
Ri
Vin
Vout
Rp
Av = - Rf/Ri = Nominal Closed Loop Gain
Ad (Op-amp) = Open Loop Gain
• Ad rolls off with frequency, 20db/dec, after first pole (~ 1 to 100 Hz)
• Bandwidth of Closed Loop Gain, Fcl, limited by Ad(f)
• Av <= Ad (fcl)
• Ad(0) = Typically 60dB to 140dB or higher
• When Ad(f) = 1, f = Unity Gain Freq
• Above fcl, Av will fall at 20db/dec (8db/oct)
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318-595 Capstone
Design
Analog Design for Production
Common Sensor Interface Requirements
(EDN)
42
318-595 Capstone
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Analog Design for Production
Filters
43
318-595 Capstone
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Analog Design for Production
Filters
Critical Factors:
1.
Passive Component Tolerances
2.
OpAmp Input Offset Voltage (Vio), worse for high gain
3.
Input Bias Current (Ib), Input Offset Current (Iio)
4.
Loading effects of input source, output loads
5. Output Slew Rate and Output Vp-p at Maximum Frequency
Worst Case Analysis:
• Transfer Function Analysis
• Total DC Offset error in Volts (1,2,3)
• Mag (dB) & Phase (deg) vs Frequency Plots (1,4)
• Power Bandwidth for Application (1,5)
• Pulse Response (topology, 4)
44
318-595 Capstone
Design
Analog Design for Production
Filter Basics
Linear Operation Must Be Maintained:
• Gain is Frequency Dependent but ….
• No New Frequencies are Created
45
318-595 Capstone
Design
Analog Design for Production
Basic Low Pass Filter
Potential Filter Shapes
46
318-595 Capstone
Design
Analog Design for Production
Basic High Pass Filter
Potential Filter Shapes
47
318-595 Capstone
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Analog Design for Production
Basic BandPass Filter
Potential Filter Shapes
48
318-595 Capstone
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Analog Design for Production
Basic BandStop Filter
Potential Filter Shapes
49
318-595 Capstone
Design
Analog Design for Production
Filter Basics
General 2nd Order Transfer Function
where;
Filter Passband Shaping:
• Q = Quality (Shape) Factor For Filter
• Q is related to the damping factor Q = 1/2a
Put Xfer Function into form with D(s) above
Find expression for Wo, then find Q or a
50
318-595 Capstone
Design
Analog Design for Production
Lowpass
Bandpass
Effect of Shape Factor on Filters
Highpass
Bandstop
51
318-595 Capstone
Design
Analog Design for Production
Filter Scaling
Filter Scaling:
• All filter coefficients and polynomials are
normalized to Wo = 1 rad/sec
• To rescale, replace S with S/Wo(new)
• Given an RC implementation circuit, Wo may also
be moved by rescaling the Capacitors
52
318-595 Capstone
Design
Analog Design for Production
Basic 2nd Order Implementations - Hambley
Lowpass
Highpass
Bandpass
53
318-595 Capstone
Design
Analog Design for Production
Example
C
+15V
4R
R
0.1uF
TLO72C
Vi(s)
Vo(s)
0.1uf
C
•
•
•
•
-15V
Find the circuit transfer function Vo(s)/Vi(s)
Find the Frequency Response |Av(jw)| and /_Av(jw)
Find the Filter Type and Design Equations for Fc or Fo and Q
Start by assuming an ideal opamp is utilized
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318-595 Capstone
Design
Analog Design for Production
Example
C
+15V
4R
R
B
Vi(s)
0.1uF
TLO72C
Vo(s)
0.1uf
A
C
Analysis
-15V
• At Node B:
(Vb = Vo)
(Va-Vo)/4R = VosC   Va = Vo(1 + 4sRC)
Vo
• At Node A:
Looks like a Lowpass Filter Transfer Function
At F = 0hz  Av = 1
At F =
(Vi-Va)/R = (Va-Vo)sC + (Va-Vo)/4R
hz  Av = 0
Substitute and solve for Vo/Vi = Av(s)
Av(s) = 1 / {(2RC)s2 + (5RC)s + 1}
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318-595 Capstone
Design
Analog Design for Production
Example
C
+15V
4R
R
Vi(s)
B
0.1uF
TLO72C
Vo(s)
0.1uf
A
C
Av(s) = 1 / {(2RC)2s2 + (5RC)s + 1}
-15V
Av(jw) = 1 / {-(2RC)2w2 + (5RC)jw + 1}
Vo
| Av(jw)| = 1 / sqrt {Real2 + Imag2}
| Av(jw)| = 1 / sqrt { [1-(2RCw)2]2 + [5RCw]2 }
Example: R = 10K, C = 0.01uF
/_ Av(jw) = Tan-1(Num) - Tan-1(Den)
F = 100Hz  |Av| = 1.0  |Av|dB = -0.28
/_ Av(jw) = 0 - Tan-1(Imag/Real)
F = 1Khz  |Av| = 0.31  |Av|dB = -10.09
F = 10Khz  |Av| = 0.006  |Av|dB = -44.08
1 Decade = -40dB
F = 100Khz  |Av|dB = -88
2nd Order Lowpass Filter
/_ Av(jw) = 0 - Tan-1{[5RCw]/ [1-(2RCw)2]}
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318-595 Capstone
Design
Analog Design for Production
Example
C
+15V
4R
R
Vi(s)
B
0.1uF
TLO72C
Vo(s)
0.1uf
A
C
-15V
Av(s) = 1 / {(2RC)2s2 + (5RC)s + 1}
Vo
Av(s) = 1/(2RC)2 / {s2 +(5/4RC)s + (1/(2RC)2)}
In the 2nd order form of …
Av(s) = G wo2 /{s2 + (wo/Q)s + wo2}
Example: Design a 2nd order lowpass filter with Fo = ~800hz
Fo = 1/(4p(10k)(0.01uf))  795 hz
Let R = 10K, 4R = 40K, C = 0.01uf
wo2 = 1/(2RC)2 =  wo = 1/2RC  Fo = 1/(4pRC)
wo/Q = 5/4RC  (1/2RC)/Q = 5/4RC
Q = 10
G wo2 = 1/(2RC)2  G = 1
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318-595 Capstone
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Multi-Function Filter Design
Summing
Inv Amp
Vout BP
Vin
-1
R1
-1
C1
R2
+
C2
A1
-1
Vout HP
A2
Vout LP
Rp
Rp
Inv Amp
-B
See: http://www-k.ext.ti.com/SRVS/Data/ti/KnowledgeBases/analog/document/faqs/spexpert.htm
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318-595 Capstone
Design
Analog Design for Production
Summary of Basic Biquadratic
Filter Transfer Functions T(s):
Note: Many texts will define Fo
as the –3dB frequency or corner
frequency.
However, it is really just the
“peak” of the transition band
range of the filter as shown on the
response curves. The actual value
of Av (or T) depends on the
damping factor Q of the filter.
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318-595 Capstone
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Analog Design for Production
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318-595 Capstone
Design
Analog Design for Production
Filter Simulation of Component Tolerances
Worst Case Analysis:
• Transfer Function Analysis
• Total DC Offset error in Volts
• Mag (dB) & Phase (deg) vs Frequency Plots
• Power Bandwidth for Application
• Pulse Response
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318-595 Capstone
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Analog Design for Production
Linear
Oscillators
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318-595 Capstone
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Analog Design for Production
Critical Factors:
Oscillators
1.
Passive Component Tolerances
2.
Loading effects of output loads
3.
Output Slew Rate and Output Vp-p at Frequency of Oscillation
Worst Case Analysis:
• Transfer Function Analysis of any Linear Feedback Circuit
• Forward path gain Analysis at 0 or 180 deg phase response
• Mag (dB) & Phase (deg) Margins vs Frequency Plots (1,2)
• Variation of Fo (1,2)
• Power Bandwidth (3)
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318-595 Capstone
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Oscillation Crition:
Oscillators
1. The open loop gain (gain around the loop) must be exactly = 1.0
2. The open loop phase (phase around the loop) must be exactly =
0o
Typically 2 types of amplifiers are utilized
Non-Inverting: Phase contribution = 0o = 360o
Inverting: Phase contribution = 180o
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318-595 Capstone
Design
Analog Design for Production
Wein Bridge Oscillator
Operational amplifier gain
G
V1( s )
Vs ( s )
1
R2
R1
RC Feedback Network Gain
R // (1/sC)  R / (1 +
sCR)
R//(1/sC)
R//(1/sC) + R + 1/sC
R / (1 + sCR)
R/(1 + sCR) + R +
1/sC

sCR
(sCR)2 + 3sCR + 1
Total Loop Gain Ab(s)
(1 + R2/R1)(sCR)
(sCR)2 + 3sCR + 1
65
318-595 Capstone
Design
Analog Design for Production
Wein Bridge Oscillator
Total Loop Gain – Steady State Analysis
(1 + R2/R1)(sCR)
(1 + R2/R1)(jwCR)

(sCR)2 + 3sCR + 1
- (wCR)2 + 3jwCR +
1
Total Loop Gain – Magnitude |Ab(jw)|
(1 + R2/R1)(wCR)
SQRT {[1 - (wCR)2]2 + [3wCR]2}
Total Loop – Phase /_Ab(jw)
90o – TAN-1
3wCR
1 - (wCR)2
Total Loop Phase /_Ab(jw) including
inverting amplifier must be 0 to satisfy
criterion #2
3wCR
270o – TAN-1
= 0o
1 -
(wCR)2
66
318-595 Capstone
Design
Analog Design for Production
Wein Bridge Oscillator
Total Loop Phase /_Ab(jw) including
inverting amplifier must be 0 to satisfy
criterion #2
3wCR
- TAN-1
= 90o
1 -
(wCR)2
Can only occur, when;
1 - (wCR)2 = 0
w= 1/RC

Total Loop – Magnitude |Ab(jw)| @ w =
1/RC Must be = 1.0 to satisfy criterion #1
(1 + R2/R1)
= 1.0

(R2/R1) = 2.0
SQRT {[3]2}
If R2/R1 = 2, oscillations occur
If R2/R1 < 2, oscillations attenuate
If R2/R1 > 2, oscillation amplify and then saturate
67
4.0V
A=3
0V
-4.0V
0s
0.2ms
0.4ms
0.6ms
0.8ms
1.0ms
0.6ms
0.8ms
1.0ms
V(R5:2)
Time
4.0V
A = 2.9
0V
-4.0V
0s
0.2ms
0.4ms
V(R5:2)
Time
20V
A = 3.05
0V
-20V
0s
100us
V(R5:2)
200us
300us
Time
400us
500us
600us
Analog Design for Production
Ideal vs. Non-Ideal Op-Amp
318-595 Capstone
Design
• Red is the ideal op-amp.
• Green is the 741 op-amp.
4.0V
0V
-4.0V
0s
V(R1:2)
0.2ms
V(R5:2)
0.4ms
0.6ms
Time
0.8ms
1.0ms
69
Analog Design for Production
Making the Oscillations Steady
318-595 Capstone
Design
• Add a diode network
to keep circuit
around A = 3
• If A = 3, diodes are
off
70
Analog Design for Production
Making the Oscillations Steady
318-595 Capstone
Design
• When output voltage is
positive, D1 turns on
and R9 is switched in
parallel causing G to
drop
71
Analog Design for Production
Making the Oscillations Steady
318-595 Capstone
Design
• When output voltage is
negative, D2 turns on
and R9 is switched in
parallel causing G to
drop
72
318-595 Capstone
Design
Analog Design for Production
Results of Diode Network
• With the use of diodes, the non-ideal op-amp
can produce steady oscillations.
4.0V
0V
-4.0V
0s
0.2ms
0.4ms
0.6ms
0.8ms
1.0ms
V(D2:2)
Time
73
318-595 Capstone
Design
Analog Design for Production
Frequency Analysis
• By changing the resistor and capacitor values in
the positive feedback network, the output
frequency can be changed.
R  10kW
w 
f 
1
RC
w
2 p
C  1nF
5 rad
w  1  10
sec
f  15.915 kHz
74
318-595 Capstone
Design
Analog Design for Production
Frequency Analysis
Fast Fourier Transform of Simulation
4.0V
(15.000K,2.0539)
2.0V
0V
0Hz
10KHz
20KHz
30KHz
40KHz
V(D2:2)
Frequency
75
318-595 Capstone
Design
Analog Design for Production
Comparators & Timers
Definition 1: A class of circuits in which 2 analog voltages are compared and the
output is a digital signal indicating > or <
Definition 2: An integrated circuit which has a high gain differential amplifier input
stage similar to an op-amp but an output stage which is only capable of driving
a digital signal corresponding to the > or < condition of the inverting and noninverting inputs
76
318-595 Capstone
Design
Analog Design for Production
Comparators
Critical Factors:
1.
Passive Component Tolerances, Diode Clamp Tolerances
2.
Input Offset Voltage (Vio)
3.
Input Bias Current (Ib), Input Offset Current (Iio)
4.
Voh, Vol clamping voltages
5.
Output Slew Rate and Delay
6.
Vref Tolerance
Worst Case Analysis:
• Vutp and Vltp (upper and lower trip points, 1,2,3,4,6)
• Total hysteresis voltage (1-4,6)
• Max switching frequency (5)
77
318-595 Capstone
Design
Analog Design for Production
Comparator Circuit
Vcc
Vcc
Rb
-
Non-linear opamp output
--
Vin
Vout
+
Rf
Vout = Vh or Vout = VL
Vh < Vcc, VL > -Vcc
Vh and VL values typically 0.5 to 3V below Vcc
V+ = {(Vout – Vref) (Ri) / (Ri + Rf)} + Vref, V- =
Vin
Ri
Positive Feedback
Hysteresis Resistor
Vref
When V+ > V-, then Vo = Vh
When V+ < V-, then Vo = VL
Vin is compared against Vref
Assume Vo = Vh and V+ >V- but Vi is increasing
If Vi > (Vout – Vref) (Ri) / (Ri + Rf) + Vref, Vo 
VL
The upper trip point (Vutp) is found as;
Vutp = {(Vh – Vref) (Ri) / (Ri + Rf)} + Vref
78
318-595 Capstone
Design
Analog Design for Production
Comparator Circuit
Vcc
Vcc
Rb
-
Non-linear opamp output
--
Vin
Vout
+
Rf
Ri
Positive Feedback
Vout = Vh or Vout = VL
Assume now Vo = VL and V+ <V- but Vi is
decreasing
If Vi < (VL – Vref) (Ri) / (Ri + Rf) + Vref, Vo 
Vh
The lower trip point (Vltp) is found as;
Hysteresis Resistor
Vref
Vltp = {(VL – Vref)(Ri) / (Ri + Rf)} + Vref
When V+ > V-, then Vo = Vh
When V+ < V-, then Vo = VL
Vin is compared against Vref
79
318-595 Capstone
Design
Analog Design for Production
Comparator Circuit Example
+Vcc
-Vcc
Rb
--
Vin
Vout
Vltp = {(VL – Vref)(Ri) / (Ri + Rf)} +
Vref
+
Rf
Vutp = {(Vh – Vref)(Ri) / (Ri + Rf)} +
Vref
Vh
Ri
Vref
Vref
Vltp
Vutp
The rectangular shape is known as a
Hysteresis Diagram
Vl
80
318-595 Capstone
Design
Analog Design for Production
Comparator Circuit Example
+15V
-15V
10K
--
Vin
Vout
+
100
K
Vh = ~13V
VL = ~-13V
Vltp = {(-13 – 5) (10k) / (10k + 100k)} + 5
Vltp = 3.36V
Vutp = {(13 – 5) (10k) / (10k + 100k)} + 5
Vutp = 5.73V
13v
10K
5v
Vref = 5V
3.36v
5.73v
Vhyst = Vutp – Vltp = 2.37V
-13v
81
318-595 Capstone
Design
Analog Design for Production
Controlling Vh and VL voltages
Vcc
Vcc
Rb
-
--
Vin
Vh or VL
+
Rf
Ri
Must have current limiting
Resistor RL when using a
Voltage Clamp
RL
Vout
(Vh-Vout)/RL < Imax for
opamp
Imax (typical) = ~ 5mA
Voltage
Positive Feedback
Hysteresis Resistor
Clamp
Vref
Controlling Vh and VL give greater utility for Comparator
82
318-595 Capstone
Design
Analog Design for Production
Controlling Vh and VL voltages
RL
D1
Vout
D1
D4
D4
Z1
Z1
Voltage
Clamp
D2
D5
Z2
D2
D3
D3
Diode String Clamp
Vh = Vd1+Vd2+Vd3 = ~2.1v
VL = -Vd4-Vd5 = ~-1.4v
Stacked Zener
Clamp
Vh = Vd1+Vz2
VL = -Vz1-Vd2
Zener Bridge Clamp
Vh = Vd1+Vd2+Vz1
VL = -Vd3-Vd4-Vz1
Vh = -VL
Types of Voltage Clamps
83
318-595 Capstone
Design
Analog Design for Production
Controlling Vh and VL voltages
Vcc
Vcc
Rb
-
--
Vin
Vh or VL
+
Rf
RL
Vout
Vh
Ri
Voltage
Positive Feedback
Hysteresis Resistor
Clamp
Vref
Vref
Vutp
Vltp
NOTE: If Vh < Vref, Vref may be
outside of Vltp-Vutp window
But hysteresis will still work
Vl
84
318-595 Capstone
Design
Analog Design for Production
Schmitt Trigger - Comparator
Vcc
Vcc
Rb
-
--
Vin
Vout
Vltp = (VL) (Ri) / (Ri +
Rf)
+
Rf
Vutp = (Vh) (Ri) / (Ri +
Rf)
Ri
Vref = 0
In a Schmitt Trigger, Vref = 0V
85
318-595 Capstone
Design
Analog Design for Production
Comparator – RC Oscillator
R2
D2
D1
R1
Vcc
Vcc
Rb
Vin
RL
--
Vout
+
C
Rf
Ri
Voltage
Clamp
Vref = 0
Schmitt Trigger used in a Relaxation Oscillator
86
318-595 Capstone
Design
Analog Design for Production
Comparator – RC Oscillator
R2
D2
D1
R1
Vcc
Vcc
Rb
Vin
RL
-
Vout
Th = -(R1C) ln{(Vutp-Vh-Vd1)/(VltpVh+Vd1)}
+
C
Rf
Ri
Vref = 0
TL = -(R2C) ln{(Vltp-VL-Vd2)/(VutpVL+Vd2)}
Voltag
e
Clamp
Note:
For Ri = Rf = Rb, R1//R2 = R, No Diodes & Vh = VL
Vutp = -Vltp = 1/2Vh
Th = -(RC) ln {(Vutp-Vh)/(Vltp-Vh)} = -RC ln (1/3)
TL = - RC ln (1/3)
F = -1 / {2RC ln (1/3)} = 0.455/RC
Individual High and Low Times can be set with Th & TL
87
318-595 Capstone
Design
Analog Design for Production
Comparator – RC Oscillator
R2
D2
D1
R1
Vcc
Vcc
Rb
Vin
RL
-
Vh
Th
Vout
+
C
Vutp
Rf
0
Ri
Vref = 0
Voltag
e
Clamp
Vltp
TL
VL
Capactor Voltage & Output Waveforms
88
318-595 Capstone
Design
Analog Design for Production
555 Timing IC
In early bipolar versions, R = 5K, hence the “555” name
89
318-595 Capstone
Design
Analog Design for Production
555 Timing IC
Pulse Generator Application of Typical 555 Timer IC
90
318-595 Capstone
Design
Analog Design for Production
555 Timing IC
Relaxation Oscillator Application of Typical 555 Timer IC
91
318-595 Capstone
Design
Analog Design for Production
Voltage Regulators, Power Supplies
Critical Factors:
1.
Passive Component Tolerances (voltage set resistors)
2.
Loading effects
3.
Input voltage DC, AC and noise levels
4.
Filtration Capacitors
5. Ambient Temperature
Worst Case Analysis:
• DC Output voltage variation (1,2,3)
• AC Output ripple, noise (2,3,4)
• Critical device power dissipation, Junction Temp (2,3,5)
• Startup Output voltage vs Input voltage vs Time (2,3,4)
• Safety Considerations
92
318-595 Capstone
Design
Analog Design for Production
Analog Analysis DFM Plan
93
318-595 Capstone
Design
Analog Design for Production
Passive Component Specifications
Passive Discrete Specifications
Nominal
Adjustment
Value or
Range,
Max Value
%/Turn
Tolerance
Around
Nominal
Derated
Pow er
Capacity
Maximum
Working
Voltage
Maximum
Constant
Current
Maximum
Surge
Current
Composition Q Factor or
Dielectric or Frequency
Form
Variation
Package
Component
Resistor
Potentiometer
Fixed Capacitor
Variable Capacitor
Fixed Inductor
Variable Inductor
Key:
Mandatory
Recommended
Not Applicable
94
318-595 Capstone
Design
Analog Design for Production
Analog Circuit DFM Analysis
95