Download Low Power Design in CMOS

Low Power Design
in CMOS
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Why worry about power?
-- Heat Dissipation
microprocessor power dissipation
source : arpa-esto
DEC 21164
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Evolution in Power Dissipation
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
BATTERY
(40+ lbs)
Nominal Capacity (Watt-hours / lb)
Why worry about power —
Portability
50
Rechargable Lithium
40
Ni-Metal Hydride
30
20
Nickel-Cadium
10
0
65
70
75
80
85
90
95
Year
Multimedia Terminals
Laptop Computers
Expected Battery Lifetime increase
over next 5 years: 30-40%
Digital Cellular Telephony
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Short Circuit Currents
Short Circuit Path between Supply Rails during Switching
•Leakage
Leaking diodes and transistors
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Dynamic Power Consumption
Vdd
Vin
V out
CL
E n e r g y / t r a n s i t i o n = C L * V d d2
Power = Energy/transition * f = C L * V dd 2 * f
Not a function of transistor sizes!
Need to reduce C L , V dd , and f to reduce power.
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Dynamic Power Consumption - Revisited
Power = Energy/transition * transition rate
= CL * Vdd 2 * f0→ 1
= CL * Vdd2 * P0→ 1* f
= CEFF * Vdd2 * f
Power Dissipation is Data Dependent
Function of Switching Activity
CEFF = Effective Capacitance = CL * P 0→ 1
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Power Consumption is Data Dependent
Example: Static 2 Input NOR Gate
Assume:
P(A=1) = 1/2
P(B=1) = 1/2
Then:
P(Out=1) = 1/4
P(0→ 1)
= P(Out=0).P(Out=1)
= 3/4 × 1/4 = 3/16
CEFF = 3/16 * CL
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Transition Probabilities for Basic Gates
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Transition Probability of 2-input NOR Gate
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Problem: Reconvergent Fanout
A
X
B
Z
Reconvergence
P(Z=1) = P(B=1) . P(X=1 | B=1)
Becomes complex and intractable real fast
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
How about Dynamic Circuits?
VDD
φ
Mp
Out
In1
In2
In3
PDN
φ
Me
Power is Only Dissipated when Out=0!
CEFF = P(Out=0).CL
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
4-input NAND Gate
Example: Dynamic 2 Input NOR Gate
Assume:
P(A=1) = 1/2
P(B=1) = 1/2
Then:
P(Out=0) = 3/4
CEFF = 3/4 * CL
Switching Activity Is Always Higher in Dynamic Circuits
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Transition Probabilities for Dynamic Gates
Switching Activity for Precharged Dynamic Gates
P0→ 1 = P0
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Glitching in Static CMOS
also called: dynamic hazards
X
A
B
Z
C
ABC
101
000
X
Z
U nit Delay
Observe: No glitching in dynamic circuits
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Example 1: Chain of NOR Gates
out1
out2
out3
out4
out5
1
...
6.0
V (Volt)
4.0
out2
2.0
0.0
0
Digital Integrated Circuits
out1
1
out4
out3
out6
out5
t (nsec)
out8
out7
2
Low Power Design
3
© Prentice Hall 1995
Example 2: Adder Circuit
Add0
Cin
Add1
Sum Output Voltage, Volts
S0
Add2
Add14
S2
S14
S1
4.0
Add15
S15
4
S15
6
2.0
3
S10
Cin
5
S1
2
0.0
0
5
10
Time, ns
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
How to Cope with Glitching?
0
F1
0
1
F2
0
0
2
F3
0
0
F1
1
F3
0
0
F2
1
Equalize Lengths of Timing Paths Through Design
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Short Circuit Currents
Vdd
Vin
Vout
CL
I VDD (mA)
0.15
0.10
0.05
0.0
Digital Integrated Circuits
1.0
2.0
3.0
Vin (V)
4.0
5.0
Low Power Design
© Prentice Hall 1995
Impact of rise/fall times on short-circuit
currents
VDD
VDD
ISC ≈0
Vin
ISC ≈IMAX
Vout
CL
CL
Large capacitive load
Digital Integrated Circuits
Vout
Vin
Small capacitive load
Low Power Design
© Prentice Hall 1995
Short-circuit energy as a function of slope
ratio
∆E / E
8
7
6
5
4
3
2
1
0
VDD = 5 V
W/L| P = 7.2 µm/1.2 µm
W/L| N = 2.4µ m/1.2µm
VDD = 3.3 V
0
1
2
3
4
5
r
The power dissipation due to short circuit currents is
minimized by matching the
rise/fall times of the input and output signals.
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Static Power Consumption
Vdd
Istat
V out
V in=5V
CL
Pstat = P(In=1) .Vdd . Istat
•Dominates over dynamic consumption
•Not a function of switching frequency
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Leakage
Vdd
Vout
Drain Junction
Leakage
Sub-Threshold
Current
Sub-Threshold Current Dominant Factor
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Sub-Threshold in MOS
√ ID
VT =0.2
VT =0.6
VGS
Lower Bound on Threshold to Prevent Leakage
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Power Analysis in SPICE
V DD
i DD
+
-
Circuit
Under Test
Pav
k i DD
C
R
Equivalent Circuit for Measuring Power in SPICE
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Design for Worst Case
V DD
VDD
1
A
1
F
2
CL
4
C
4
2
A
B
B
2
D
B
F
2
A
A
D
2
1
B
2C
2
Here it is assumed that Rp = Rn
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
NORMALIZED POWER-DELAY PRODUCT
Reducing Vdd
1.5
P x td = E t = CL * Vdd 2
1.00
0.70
0.50
0.30
0.20
quadratic dependence
0.15
E(Vdd=2)
E(Vdd=5)
0.1
2
(CL) * (2)
=
2
(CL) * (5)
51 stage ring oscillator
0.07
E(Vdd=2) ≈0.16 E(Vdd =5)
0.05
8-bit adder
0.03
1
2
5
Vdd (volts)
Strong function of voltage (V 2 dependence).
Relatively independent of logic function and style.
Power Delay Product Improves with lowering VDD.
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Lower Vdd Increases Delay
7.50
7.00
multiplier
2.0µ m technology
clock generator
NORMALIZ ED DELAY
6.50
6.00
5.50
5.00
Td
CL * V dd
=
I
I ~ (V dd - V t)2
4.50
4.00
3.50
ring oscillator
3.00
Td(Vdd=2)
2.50
2.00
1.50
1.00
microcoded DSP chip
Td(Vdd=5)
adder
adder (SPICE)
2.00
4.00
V dd (volts)
(2) * (5 - 0.7)2
=
(5) * (2 - 0.7)2
≈ 4
6.00
Relatively independent of logic function and style.
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Lowering the Threshold
Delay
I
2V t
Vdd
D
Vt = 0
Vt = 0.2
V GS
Reduces the Speed Loss, But Increases Leakage
Interesting Design Approach:
DESIGN FOR PLeakage == PDynamic
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Transistor Sizing for Power Minimization
Lower Capacitance
Higher Voltage
Small W/L’s
Large W/L’s
Higher Capacitance
Lower Voltage
Larger sized devices are useful only when interconnect dominated.
Minimum sized devices are usually optimal for low-power.
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Transistor Sizing for Fixed Throughput
Cg = W/L CMIN
I ∝ W/L CMIN
CMIN = Minimum sized gate (W/L=1)
W /L after sizing
CP = Cwiring + CDF
α = CP / (K CMIN)
HIGH PERFORMANCE
W/L >> C P / (K CMIN)
LOW POWER
W/L = 2 CP / (K CMIN)
(if CP ≥ K CMIN )
ELSE W/L = 1
NORMALIZED ENERGY
10
7
α=0
5
4
3
α = 0.5
2
1.5
α=1
adder
1.0
0.7
α = 1.5
α=2
0.5
1
3
10
W/L
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Reducing Effective Capacitance
Local bus architecture
Global bus architecture
Shared Resources incur Switching Overhead
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Summary
• Power Dissipation is becoming Prime Design
Constraint
• Low Power Design requires Optimization at all Levels
• Sources of Power Dissipation are well characterized
• Low Power Design requires operation at lowest
possible voltage and clock speed
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995