Download 10 - Electrical and Computer Engineering

UCONN ENGR_ECE 4243/6243 HW11 FET-I & Solution 11152016 F. Jain
QUIZ 2 part B Take Home will be like Q.6. It will be given on 11/22/16
Q.1. (a) Find the work functions for n and p-type Si for the doping levels given below. Show
them in relation to vacuum energy level being zero as the reference.
The electron affinity of Si is qχSi = 4.15 eV.
p-side: Acceptor concentration NA=1015 cm-3, n=10-5 sec. Dn=40 cm2/sec.
Effective mass: electrons me=mn=0.26mo, holes mh=mp= 0.64 mo,
Junction area A=10-3 cm-2, ni (300K) =1.51010 cm-3. r(Si)=11.8, 0=8.8510-14 F/cm,
s=r0. Assume all donors and acceptors are ionized at T=300 K. Eg = 1.1eV,
Boltzmann Constant k= 8.65x10-5 eV/K.
n+-side: Donor concentration ND=1018 cm-3, minority hole lifetime p=210-6 sec.
Minority hole diffusion coefficient Dp=12.5 cm2/sec.
(b) Compute the work function difference nSi-pSi (=nSi - pSi) and show that it is equal to the builtin voltage.
Solution Q1(a) Work function is expressed as
qnsi  q si  Ec  Ei   E f  Ei   4.15  0.55  0.4666  4.2334eV
E c  Ei  E g / 2  0.55eV
Ef - Ei is obtained from the definition of intrinsic Fermi level Ei:
E  E / kT
n  ni e f i , if we take natural log (ln) we get
n
E f  Ei  kT ln 
 ni

N
  kT ln  D

 ni
 1018 


  0.0259 ln 
 1.5  1010   0.4666 eV



Work function of p-Si: Doping NA=1015cm-3
Intrinsic concentration pi  ni
q psi  q si  E g / 2  Ei  E fp   4.15  0.55  0.2876  4.9876 eV
Ei  E f
p  pi e
kT
Ei  E f
 ni e
kT
Ei  E f
or e
kT

p
ni
  Ei  E f  E  E f 
P
N 
Taking log (ln) we get, ln  e kT  
  ln    ln  A 

kT 
 
 ni 
 ni 


N 
 1015 
  0.2876eV
Ei  E f  kT ln  A   0.0259 ln 
20 
 1.5  10 
 ni 
Note Ei - Efp = q B
Q1(b) Work function differences are negative values


 q p  si  q n si  4.9876  4.2334  0.7542eV
Vbi   n   si  0.754V
Same as we calculated from the well-known Vbi expression for p-n junctions.
 1018 *1015 
 =0.754V
Vbi  0.0259 ln 
20 
 2.25  10 
1
Q.2 Compute the flat band voltage Vfb and threshold voltage VT (or VTH) for an Al-SiO2-pSi
MOS capacitor having the following parameters: T=300K.
Qox = 2.103 x 10-8 C/cm2
Si = 11.8
-8
Oxide thickness = d = 1000Å (1Å = 10 cm),
ni = 1.5x1010 cm-3
qSiO2 = electron affinity of SiO2 = 0.9 eV
NA = 1016 cm-3
ox = 3.9, o = 8.854x10-14 F/cm
qχSi = 4.15 eV (affinity of Si)
Intrinsic Fermi level is Ei ~Eg/2, Eg (Si) = 1.1eV
qAl = 4.1 eV (work function of Al).
Assume Qox to be located in the SiO2 near the Si interface.
HINT set: VFB= ms – Qox/Cox ( Qox assumed to be located in SiO2 near the SiO2-Si interface).
VFB= ms if there is no oxide charge. ms = m -s = Al - pSi . Find the work functions and compute
ms.
Solution Q.2
Evaluation of Flat Band voltage: Vfb=VFB=Flat band voltage
Q
Q
VFB  ms  ox   Al   pso   ox
Cox
Cox
 1016 
q Al  4.1eV and q psi  4.15  0.55  0.0259 ln 
 5.0473eV
10 
1.5  10 
 ms   Al   psi  4.1  5.0473  0.9473
Qox  2.103  10 8 C / cm 2 , and
C ox 
 sio2  0
d
F / cm 2 
3.9  8.854  10 13
 3.453  10 8 F / cm 2
8
1000  10
Thus, VFB  0.9473 
2.103 10 8
 0.9433  0.609 = -1.552V
3.453 108
Evaluation of threshold voltage VTH:
Q
VTH  VFB  sc  2 B where
Cox
N 
 1016 
  0.3475 or 2 B  0.3473 V  2  0.6946V
q B  Ei  E f  kT ln  A   0.0259 ln 
20 
 1.5 10 
 ni 
Qsc  qN AWm  1.6 10 19 1016  3.0110 5  4.816  10 8 C/cm2
Wm 
and
2 si 0 2 B

qN A
2  11.8  8.854  10 14  0.69
 90.7  10 11  3.01  10 5 cm
19
16
1.6  10  10
Qsc  4.816 108

 1.394 V. Substituting in threshold expression, we get
Cox
3.453 108
VTH  VFB 
Qsc
 2 B  1.552  1.394  0.6946  0.5366V
Cox
2
****
****
****
****
New Q.3(a). The threshold voltage is altered by: Circle correct answers
Gate metal
charge in the gate oxide
source doping
substrate doping
(b) For a given metal-oxide-pSi MOS capacitor, which one will have higher threshold? Circle
Al-SiO2-psi
or
Au-SiO2-pSi
(c) What is the advantage in replacing gate metal by doped poly Si layer as the gate layer?
Adjustment of threshold voltage,
Enabling deposition of oxide for gate isolation in ICs
(d) Why in 22 nm FETs poly Si is not used and TaN or TiN metals are used?
Because of lower threshold so that devices can use VDD ~ 0.5V.
Q.4 (a) Compute the drain current for VD=0.5V and VD=2.5V at VG=2V and 4V.
First, we need to find the saturation voltage VD (set) for VG=2V and for VG=4V.
VD (sat) ≈ VG-VTH using Case I Approximation.
N A  10 16 cm 3
ni  1.5  10 cm
10
Given: Channel length L = 10 μm, channel width
Z = 40 μm, operating temperature T = 300K, and
channel mobility μn = 800 cm2/Voltsec., Qox =
2.103 x 10-8 C/cm2, Si = 11.8, Oxide thickness = d
= 1000 Å (1 Å = 10-8 cm), ni = 1.5x1010 cm-3, qSiO2
= electron affinity = 0.9 eV, NA = 1016 cm-3, ox = 3.9,
qχSi = 4.15 eV, o = 8.854x10-14 F/cm, qAl = 4.1 eV
3
d  1000 
C ox 
3.9  8.854  10 14
 3.45  10 8 F / cm
8
1000  10
 ms  0.6 
kT N A
ln
q
ni
 0.6  0.0259 ln
The intrinsic Fermi level Ef= Ei ~Eg/2.
10 16
1.5  1010
 ms  0.947V
V FB   ms 
Qox
C ox
2.103  10 8
 1.557V
3.45  10 8
 B  0.347V
 0.947 
Wm 
2 s  0 2 B
 3.01  10 5 cm
qN A
3
VTH  VT  V FB 
 1.557 
Qsc
 qN AWm
 2 B  1.557 
 2 B
C ox
C ox
1.6  10 19  1016  3.01  10 5
 2  0.347  1.557  1.396  0.694  0.533 V
3.45  10 8
CASE I:
For VG  2V , V D Sat  VG  VTH  2  0.533  1.467V
For VG  4V , V D Sat  4  0.533  3.467V
Therefore, for VG  2V , V D  0.5V is belowVD sat  of 1.467V
& V D  2.5V  V D sat  of 1.467V
Linear regime : I D   n C ox
V D2 
Z
VG  VTH V D 
 is OK for V D  0.5V
L
2 
Saturation regime : I D ( sat)   n Cox
2
Z VD sat  

 is OK for VD  1.467V
L 
2

VG  2V, and VD  0.5V
I D  800  3.45  10 8 
40 m 
0.5 2 
 2  0.533 0.5 

10 m 
2 
0.25 

 1.104  10  4  1.467  0.5 
 1.104  10  4  0.6085  6.718  10 5 
2 

VG  2V, and VD  2.5V
 2  0.5332 
 1.467 2 
4
I D sat   1.104 10  
  1.104 10  

2


 2 
I D sat   1.187 10 4 
4
Similarly , VG  4V , VD  0.5V and 2.5V are below VD sat .
Hence, VD sat   3.467V , VG  4V , VD  0.5V

0.52 
I D  1.104 10  4  0.533 0.5 

2 

0.25 

4
 1.104 10  4  3.467  0.5 
  1.775 10 
2


4
We use the linear regime ID equation for VD < VD(sat)
4
VG  4V , VD  2.5V

2.5 2 
4
I D  1.104  10  3.467  2.5 
  6.118  10 
2 

4
Summary Table
ID
VG
VD
6.718x10-5A
2V
0.5V
1.187x10-4A
2V
2.5V
1.775x10-4A
4V
0.5V
6.118x10-4A
4V
2.5V
Q.4(b) Find saturation current and voltage VD(sat) at the VG = 4V.
ID(sat) at VG=4.0 V
Using Case-I definition of VD(sat)
VD = VD(sat) = VG – VTH =4.0-0.533=3.467 volts
I D (sat )   n C OX
3.467  6.63 * 10 4 Amp
Z VD (sat ) 2 
4

  1.104 * 10 *
L
2
2

2
Q.4(c) Calculate the channel conductance gD and the transconductance gm at the following drain
voltages VD = 0.5 V and VD = 2.5 V.
gm at VD=0.5 V,
VD=2.5 V,
VG=4.0 V (likes part b)
Find gd at VD=0.5 V,
VD=2.5 V
VG=4.0 V
gm for VG =4.0 V:
VD(sat) = VG –VTH = 4.0 – 0.533 = 3.467 V.
So both VD=0.5 V & VD=2.5 V will give unsaturated linear regime values.
gm 
I D
Z
40
  n * C OX * (VD )  800  3.45  10 8   VD  1.104 * 10 4 VD
VG
L
10
g m (at V D  0.5)  1.104  10 4  0.5  0.552  10 4 Mho, g m (at V D  2.5)  1.104  10 4  2.5  2.76 * 10 4 Mho
Drain conductance; g D  I D |V   n C OX Z (VG  VTH )  VD 
VD
G
L
For VG=4.0 , VD(sat)=3.467 V(VD=0.5 V, 2.5 V are below Saturation )
5
g D |VD 0.5  1.104 *10 4 * (4  0.533)  0.5  3.275 *10 4 Mho
g D |VD 2.5  1.104 *10 4 * (4  0.533)  2.5  1.06 *10 4 Mho
Q.4(d) If the gate is n+ poly Si (ND = 1x1019cm-3), calculate the flat band and threshold voltage
assuming the same Qox as in part (a).
Gate is n+ poly Si , ND=1019 cm-3
qms  qn  Poly-pSi  qn  Poly - qpSi

1019  
1016 
 4.15  0.55 - 0.0259  ln(
)  4.15  0.55  0.0259  ln(
)  (4.1738  5.0473)eV
1.5 *1010  
1.5 *1010 

qms  0.8735V
VFB  ms 
QOX
2.103 *10 8
 0.8735 
 0.8735  0.609  1.4825V
C OX
3.45 *10 8
Note: In Part Q4(a), VFB = -1.557 V, and in part Q1(d) VFB =-1.4825 V
VTH  V FB 
Qsc
 2 B
C OX
VTH  V FB 
(q * N A * Wm )
 2 B
C OX
VTH  1.4825 
(1.6 * 10 19 * 1016 * 3.01 * 10 5 )
 0.694  1.4825  1.3959  0.694  0.607 V
3.45 * 10 8
The parameters used are from Q4(a).
kT  N A 

ln 
q  ni 
Q4(e) Calculate the transconductance gm in the linear regime. From Q1(c) we have
N A  1016 cm 3 , Qsc = q * N A * Wm , and  B 
gm 
I D
Z
40
  n * C OX * (VD )  800  3.45  10 8   VD  1.104 * 10 4 VD . It depends on VD.
VG
L
10
Q4(f) What is the cut off frequency fT (= gm/(2 Cg)) of this FET? Cg is the gate capacitance which
varies between Cox and Cox/3 depending on the depletion width variations. It also depends on the
drain and source to body capacitance.
Using gm =2.76*10-4 from part Q1(d) at VD = 2.5V, and Cg = Cox/3 = 3.45*10-8/3=1.15*10-8 F/cm2.
Here we have used the capacitance of unit area (L*Z = 1 cm2).
fT =2.76*10-4/(2 *1.15*10-8) = 3819.71 Hz for a 1cm2 gate area FET.
For FET with dimensions L=10 m and Z=40 m,
fT = 3819.71/(10m * 40m) =9.54*108 Hz.
6
Q.5(a) The resistance of load transistor is 4 to 6 times higher than of the driver transistor
resistance. Resistance is inversely proportional to (W/L) ratio.
As a result, (W/L) Driver = 4 to 6 * (W/L) Load.
D
10/10
or
G
S
Depletion MOS
OUTPUT
T1
20/5
T2
40/5
40/5
D
G
or
T3
40/5
S
Enhancement
MOS
Fig 1. Schematic of an NMOS logic gate. W/L (or Z/L) ratios are shown.
Justification: When there are more than one transistor is in series on the driver side (i.e. below
the output), we increase the (W/L) ratio by the number of transistors in series. Two transistors T1
and T3 are in series with size = 2*20/5=40/5.Similarly, T2 and T3 are in series with same sizing.
Q5(b) The PMOS-FET (W/L) is made 2.5 times larger than (W/L) of NMOS. This is done to
charge and discharge the load capacitor CL (at the output of a CMOS gate). When input voltage
goes from low to high, discharging of CL (which was at VDD) takes place through NMOS FET.
Similarly, charging happens through PMOS FET when the input changes from high-to-low.
W
W
  P * C OX *  

 L  n  MOS
 L  P  MOS
 n * C OX * 
W
W
Since  n   p * 2.5,  
 2.5 *  
 L  n  MOS
 L  P  MOS
Fig.2 shows the topology of this CMOS inverter.
7
Source contact
Wp=25m
p diffusion for Source
Lp=5m
Polysilicon
Drain of PMOS
n- well
Drain of NMOS
Wn
Ln
Ln=5m
Wn=10m
gate contact
Source contact
n diffusion for source
Fig.2 CMOS Inverter on p-Si substrate
Q.5(c) Justify the W/L ratios shown for CMOS NOR and NAND gates in Fig.3.
A)
VDD
B)
VDD
W 50 m 

 PMOS
L
5 m 
25
5
25 m
5 m
Vout
Vout
20m
5m
W 10m 

 NMOS
L 5m 
20m
5m
CMOS NAND gate
CMOS NOR gate
Fig. 3 W/L ratios for CMOS NOR and NAND gates.
NOR gate Fig.3(A). Here two P-MOS FETs are in series. When both are “ON”, we need to
reduce their total series resistance to equivalent of one transistor.
The W/L ratio is multiplied by number of FETs in series.
(W/L) P-MOS when two in series =2*(W/L) P-MOS when single =2*(25/5)=50/5
Fig.3 (B) is a NAND. This gate has two NMOS in series. Therefore,
(W/L)N-MOS when two in series(NAND) =(10/5) *2# FET in series =20/5
Q.6. NANOFET Design:
(a) Outline the steps used in scaling a FET from 1.3 micron to 0.25 micron is described in
Baccarani et al (1984 paper) and shown in Table I below.
Design steps: 1. Find the dimensional scaling factor l which is L/L’ or W/W’ or Tox/Tox’.
8
2. Find the V’TH for the new scaled down FET including process variations, masking registration
errors, doping changes. Find V’TH= 4 V’TH. Find V’DD = 4 V’TH.
Calculate scaling factor for voltages and potentials: k = VTH/ V’TH
3. Find 
4. Compute new substrate doping N’A = NA/ = (2/k) NA
Table I Hint set for 25nm FET design
Parameters
LATV
1.3micron
Channel
Length L(m)
Gate Insulator
Oxide tox (nm)
Junction
Depth xj(nm)
VTH (V)
VTH 4xVTH
0.25 micron
QMDT* (IBM)
25nm SiGe
Scaling
(Home work)
factor
1.3
0.25
0.025
=10
25
5.0 (SiO2)
0.5 (SiO2)
10
350
70-140
7-14
10
0.6
0.06
V’TH 4xV’TH V’TH
=0.015
0.25
=4
Comments
0.5(HfO2 /SiO2)
= 1.7nm
Gives high Rs and
Rd
VTH=0.015V
VDS = VDD (V)
VDD = 4 x VTH
Band Bending (V)
2.5
0.25
V’TH 4xV’TH
V’TH =0.06
1.0
1.8
0.8
0.3
?
Doping NA (cm-3)
3x1015
N’A =31016
N’A=7.51017
NA x 2/=25
(Rs + Rd)ID
IR Drop (mV)
RC Delay  (ps)
NA
< 10mV
< 1mV
??
How to solve this
Not appl. (NA)
100ps
2-5 ps??
??
How to solve this
Scaled down FET
1. Dimensions
L’, W’, Tox’
=4
Original FET
𝐿⁄ 𝑊⁄ Tox⁄
𝜆,
𝜆,
𝜆
𝜆>1
2. Voltages
VGS’, VDS’ ,VTH’
V𝐺𝑆 V𝐷𝑆 V𝑇𝐻⁄
⁄𝑘,
⁄𝑘,
𝑘
𝑘>1
N𝐴 N𝐷⁄
⁄δ,
δ
δ<1
3. Doping Levels
NA’, ND’
Since δ = 𝑘⁄𝜆2 and (1/= 2/k, substrate doping NA’ is higher. [Pages 579-580 Notes III]
Q6(b) Scale down a 0.25 micron FET to design the 0.025 micron (25nm) transistor following the
10-fold scaling. Given VTH = 0.015V for 25 nm process. Justify the values given in Table I.
For 0.025micron FET, use VTH = ¼ of VDD. Assume VDD of 0.4 Volt. Obtain gate oxide
thickness, Si doping levels, source and drain thicknesses and doping etc. The three design steps
to obtain 0.25μm FET from 1.3μm FET are shown below
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1.3 μm channel length L
FET
L = 1.3 μm
Tox = 25 nm
0.25 μm FET channel length L’
Scaling factor
L’ = 0.25 μm
Tox ’ = 5 nm
L’= 𝐿⁄𝜆, 𝜆 = 1.3⁄0.25 = 5
VDD = 2.5 V
VTH = 0.6 V
VDD ’ = 1 V
VTH ’ = 0.25 V
VDD’=
Substrate doping NA
Scaling factor δ
NA’ = NA
𝜆2
𝑘
= NA
/δ
𝑉𝐷𝐷
⁄𝑘, 𝑘 = 2.5⁄1 = 2.5
25
NA’ = NA 2.5
=
NA * 10
N’A =31016 cm-3
δ = k / 𝜆2
These parameters are given in Reference 1, Pg 591
Now our task is to scale 0.25μm to 0.025 μm FET
0.25 μm channel
length L FET
0.025 μm channel length L’ FET
Scaling factor
L = 0.25 μm
L’ = 0.025 μm
L’= 𝐿⁄𝜆, 𝜆 = 0.25 ⁄ 0.025 = 10
Tox = 5 nm
Tox’ =5⁄10 =0.5 nm = 5Å
VDD = 1.0 V
VDD’ = 0.25V (given). VDD’ = 4* VTH’
VTH’ = 4 VTH’=4*0.015 = 0.06V
k = VDD/ VDD’= 1.0/0.25 = 4
VTH = 0.25 V
NA = 3 * 1016 cm-3.
NA’ = NA/(1/= 2/k= 100/4=25.
NA’= 3*1016 *25 = 7.5*1017 cm-3.
VDD’=
𝑉𝐷𝐷
⁄𝑘, 𝑘 = 1.0⁄0.25 = 4
k =4
NA’ = 3 * 1016 *
102
4
= 7.5* 1017 𝑐𝑚−3
Certain issues following scaling:
1. Oxide thickness in 0.25 μm ≈ 50 - 60 𝐴𝑜
Tox’ in 0.025 μm ≈ 5 𝐴𝑜 is too small and permits tunneling.
2. Tunneling from source to drain when L’ = 25nm and lower.
3. ID * ( R S + RD ) voltage drop is < 1 mV.
Q.6 (c) Generalized scaling (GS, Table IV) is better than constant electric field (CE) scaling
(Table–II) and constant voltage (CV) and Quasi constant voltage (QCV) in (Table-III) as it permits
different scaling for voltages/ potential, dimensions (L,W,Tox ) and doping. GS is based on
preserving Poisson’s equation. GS gives relationship for NA’ and ND’ with NA and ND multiplied
by 1/δ.
Constant electric (CE) field scaling: All dimensions, voltages are divided by k (or scaling factor).
Doping levels are multiplied by k.
10
Quasi Constant Voltage (QCV) Scaling: All dimensions are divided by k (or scaling factor).
Doping levels are multiplied by k. The voltages are divided by (1/k)1/2 which is less than k.
Constant Voltage (CV) Scaling: All dimensions are divided by k (or scaling factor). Doping
levels are multiplied by k. The voltages are not changed.
Most difficult parameters are:
(i) Gate Insulator. Solution is to increase Tox‘ = 5 𝐴𝑜 by using HfO2 which has a higher
dielectric constant ɛHf O2 ≈ 13.7 and dielectric constant for SiO2 is 3.9.
ɛ HfO2
Tox’ for HfO2 as gate insulator is = ɛ SiO2 * Tox’(SiO2),
=
13.7
3.9
* 5 𝐴𝑜 = 17.5 𝐴𝑜 = 1.75 nm
Eg for Hf O2 = 5.7 eV and electron affinity qHf O2 = (2.0 ± 0.25 ) eV
The other parameter is the voltage drop in R S + RD
(ii) Source and Drain resistances and voltage drops for a 25nm FET are calculated below.
Xj
N+
L=22nm
Ls
Ls= 22nm (contact) +11nm +11nm=44nm
= 0.07 – 0.14 µm
RS = RD =ρn*
10

0.14 µm
𝑋𝑗 ∗𝑊
ρs = 7 * 10−4 Ω-cm. Given W=44nm,
10
= 0.007 µm 0.014 µm
= 7 nm
𝐿𝑠
For 1020 n+ doping the resistivity s is
Xj’ for 0.025 µm NanoFET
0.07
W gate
width
Ld
Xj for 0.25 µm FET (Baccarani et al Table II)
=
N+
RS = RD =
7 ∗ 10−4 ∗44 𝑛𝑚
0.007 ∗ 10−4 ∗44 𝑛𝑚
 14 nm
= 1.0 kΩ
If the drain current is I D ≈ 1mA or 0.1 mA. Taking 0.1mA or 100 microamp, we get
I D * (R S + RD) ≈ 0. 2V =200mV, which is too high.
How can we reduce RS and RD ?
Method # 1 Increase the thickness Xj of source or source contact Tsource above the implanted
14 nm region.
11
Growth of n+ epi layer
1020 cm-3
Tsource
140 nm
14 nm
Extension
154nm
Xj
New source resistance RS’ = Rs *[Xj/(Xj + Tsource]
7 ∗ 10−7
=
154 ∗ 10−7
*1.0 kΩ
= 45.45Ω
The new IRs’ drop is
I *RS’ = 100 µA * 45.45Ω = 4.5mV. This value is still higher than 1mV.
Method 2: (a) Increase W of the channel, and (b) further increase thickness of source TSource.
Both are not desirable as they increase the area of FET (option a) and make processing difficult
when using masks or metal contacts (option b).
Method 3. Use metal silicides for vertical extensions in place of n+ Si which have reduced
resistivity.
What is done is to replace Tsource contact with lower resistivity silicides or TiN or TaN.
RS (with silicides) is reduced by a factor of 10. The new drop is 0.45mV.
Reduce RS from 45.4Ω to approximately 4.5 Ω.
12