Download COMP 103 Lecture 05: CMOS Inverter

COMP 103
Lecture 05: CMOS Inverter
[All lecture notes are adapted from Mary Jane Irwin, Penn State, which were
adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
COMP103.1
CMOS Inverter:
A First Look
•
Full rail-to-rail swing ⇒ high noise
margins
•
Always a path to Vdd or GND in
steady state
•
No direct path steady-state
between power and ground ⇒ no
static power dissipation
•
Propagation delay function of load
capacitance and resistance of
transistors
VDD
Vin
Vout
CL
• Logic levels not dependent upon
the relative device sizes ⇒ ratioless
COMP103.2
CMOS Inverter:
Steady State Response
VOL = 0
VDD
VDD
VOH = VDD
VM = f(Rn, Rp)
Rp
Vout = 1
Vout = 0
Rn
Vin = 0
Vin = V DD
COMP103.3
Review: Short Channel I-V Plot (NMOS)
X 10-4
2.5
VGS = 2.5V
VGS = 2.0V
1.5
1
VGS = 1.5V
0.5
VGS = 1.0V
Linear dependence
ID (A)
2
0
0
0.5
1
1.5
2
2.5
VDS (V)
NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
COMP103.4
Review: Short Channel I-V Plot (PMOS)
z
All polarities of all voltages and currents are reversed
-2
VDS (V)
-1
0
VGS = -1.0V
-0.2
VGS = -1.5V
-0.4
-0.6
ID (A)
0
VGS = -2.0V
-0.8
VGS = -2.5V
-1 X 10-4
PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V
COMP103.5
Transforming PMOS I-V Lines
z
Want common coordinate set Vin, Vout, and IDn
IDn
IDSp = -IDSn
VGSn = Vin ; VGSp = Vin - VDD
VDSn = Vout ; VDSp = Vout - VDD
Vout
Vin = 0
Vin = 0
Vin = 1.5
Vin = 1.5
VGSp = -1
VGSp = -2.5
COMP103.6
Mirror around x-axis
Vin = VDD + VGSp
IDn = -IDp
Horiz. shift over VDD
Vout = VDD + VDSp
CMOS Inverter Load Lines
PMOS
2.5
NMOS
X 10-4
Vin = 2.5V
Vin = 0V
2
IDn (A)
Vin = 0.5V1.5
Vin = 2.0V
Vin = 1.0V 1
Vin = 1V
Vin = 1.5V
Vin = 2V
0.5
Vin = 0.5V
Vin = 1.0V
Vin = 1.5V
Vin = 2.0V
Vin = 1.5V
Vin = 0.5V
0
Vin = 2.5V 0
0.5
1
1.5
Vout (V)
2.5 Vin = 0V
2
0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V
COMP103.7
CMOS Inverter VTC
2.5
Vout (V)
2
1.5
1
0.5
0
0
0.5
1
1.5
Vin (V)
COMP103.8
2
2.5
CMOS Inverter VTC
NMOS off
PMOS res
2.5
NMOS sat
PMOS res
Vout (V)
2
1.5
NMOS sat
PMOS sat
1
NMOS res
PMOS sat
0.5
NMOS res
PMOS off
0
0
0.5
1
1.5
2
2.5
Vin (V)
COMP103.9
CMOS Inverter:
Switch Model of Dynamic Behavior
VDD
VDD
Rp
Vout
Vout
CL
Vin = 0
COMP103.10
CL
Rn
Vin = V DD
CMOS Inverter:
Switch Model of Dynamic Behavior
VDD
VDD
Rp
Vout
Vout
CL
Vin = 0
CL
Rn
Vin = V DD
z Gate response time is determined by the time to charge CL
through Rp (discharge CL through Rn)
COMP103.11
Relative Transistor Sizing
‰
When designing static CMOS circuits,
balance the driving strengths of the
transistors by making the PMOS section
wider than the NMOS section to
z
z
COMP103.12
maximize the noise margins and
obtain symmetrical characteristics
Switching Threshold
‰
VM where Vin = Vout (both PMOS and NMOS in saturation
since VDS = VGS)
‰
Equate NMOS/PMOS saturation currents, VM =Vout, solve
for Vm
z
VM ≈ rVDD/(1 + r) where r = kpVDSATp/knVDSATn
‰
Switching threshold set by the ratio r, which compares
the relative driving strengths of the PMOS and NMOS
transistors
‰
Want VM = VDD/2 (to have comparable high and low
noise margins), so want r ≈ 1
‰
In general:
(W/L)p
=
kn’VDSATn(VM-VTn-VDSATn/2)
(W/L)n kp’VDSATp(VDD-VM+VTp+VDSATp/2)
COMP103.13
Switch Threshold Example
‰
In our generic 0.25 micron CMOS process, using the
process parameters from slide L03.25, a VDD = 2.5V, and
a minimum size NMOS device ((W/L)n of 1.5)
NMOS
PMOS
(W/L)p
(W/L)n
COMP103.14
=
VT0(V)
0.43
-0.4
γ(V0.5)
0.4
-0.4
VDSAT(V)
0.63
-1
k’(A/V2)
115 x 10-6
-30 x 10-6
λ(V-1)
0.06
-0.1
Switch Threshold Example
‰
In our generic 0.25 micron CMOS process, using the
process parameters from slide L03.25, a VDD = 2.5V, and
a minimum size NMOS device ((W/L)n of 1.5)
VT0(V)
0.43
-0.4
NMOS
PMOS
γ(V0.5)
0.4
-0.4
k’(A/V2)
115 x 10-6
-30 x 10-6
VDSAT(V)
0.63
-1
λ(V-1)
0.06
-0.1
(W/L)p 115 x 10-6 0.63 (1.25 – 0.43 – 0.63/2)
=
(W/L)n
x
x
-30 x 10-6 -1.0
(1.25 – 0.4 – 1.0/2)
= 3.5
(W/L)p = 3.5 x 1.5 = 5.25 for a VM of 1.25V
COMP103.15
Simulated Inverter VM
VM is relatively
insensitive to variations in
device ratio
‰
1.5
1.4
1.3
setting the ratio to 3, 2.5
and 2 gives VM’s of 1.22V,
1.18V, and 1.13V
z
VM (V)
1.2
1.1
Increasing the width of
the PMOS moves VM
towards VDD
1
‰
0.9
0.8
0.1
1
(W/L)p/(W/L)n
Note: x-axis is semilog
COMP103.16
~3.4
10
Increasing the width of
the NMOS moves VM
toward GND
‰
CMOS Process at a Glance
Define active areas
Etch and fill trenches
‰
One full photolithography
sequence per layer
(mask)
‰
Built (roughly) from the
bottom up
Implant well regions
Deposit and pattern
polysilicon layer
Implant source and drain
regions and substrate contacts
5
4
2
3
1
metal 2
metal 1
polysilicon
exception!
source and drain diffusions
tubs (aka wells, active areas)
Create contact and via windows
Deposit and pattern metal layers
COMP103.17
Simplified CMOS Inverter Process
cut line
p well
COMP103.18
P-Well Mask
COMP103.19
Active Mask
COMP103.20
Poly Mask
COMP103.21
P+ Select Mask
COMP103.22
N+ Select Mask
COMP103.23
Contact Mask
COMP103.24
Metal Mask
COMP103.25
A Modern CMOS Process
Dual-Well Trench-Isolated CMOS
gate oxide
field oxide
Al (Cu)
SiO2
TiSi2
tungsten
p well
SiO2
n well
p-epi
n+
p+
p-
COMP103.26