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Copy of: IEEE 2004 Int. Conference on Microelectronic Test Structures, Vol. 17, March 2004
Test Structures and Analysis Techniques for Estimation of the Impact of
Layout on MOSFET Performance and Variability
Sharad Saxena, Seán Minehane, Jianjun Cheng, Manidip Sengupta, Christopher Hess,
Michele Quarantelli, Glenn M. Kramer and Mark Redford
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Email: {saxena, seanm, jianjun, sengupta, hess, micheleq, gmkramer, markr}@pdf.com
ABSTRACT
The performance and variability of transistors with
nanometer-scale feature sizes is sensitive to their layout style
and environment. This paper describes the use of an
enhanced MOS array test structure to provide accurate and
precise estimates of the impact of layout on transistor
characteristics for an advanced 130nm CMOS technology.
Enhanced MOS arrays, combined with statistical analysis of
the measurements, provide reliable information on the impact
of layout on the transistor characteristics. This can then form
the basis for technology development, design rule
development and modeling.
I. INTRODUCTION
Layout style and environment impact the performance and
variability of transistors with nanometer scale features [1].
There are many reasons for the increase in the sensitivity of
transistor characteristics to its layout. The different forms of
resolution enhancement required to print nanometer scale
feature sizes with existing lithography are one dominant
cause. They make the final printed patterns dependent on its
shape and neighborhood. Examples of other causes include
the impact of mechanical stress due to trench isolation on the
mobility [1][3][4][5].
There are two approaches to address the layout dependence
of transistor characteristics. One is to optimize the technology
to minimize the impact of layout; for example, by optimizing
the OPC and assist feature insertion algorithms. The other is
to manage the impact of layout on performance through
design rules and models that include the impact of layout
[4][5]. Both approaches require reliable and statistically valid
characterization of the impact of layout on device
performance and its variability. A key challenge is to design
test-structures and analysis techniques that can separate the
systematic change in performance introduced by layout
dependence from performance changes caused by
manufacturing variations such as across-wafer nonuniformity and wafer-to-wafer variation. Making statistically
valid conclusions about the impact of layout on device
performance is critical for a technology: accurate and reliable
estimates are required to determine the corrective measures
required during technology development and provide the data
necessary for design rule development and modeling.
Section II describes the test structure and measurement
requirements for evaluating the layout dependence of
transistor performance. The test structure has to separate
layout-induced variation in performance from other sources
of variation. We have found that MOS arrays are an effective
test structure for this purpose. They provide an efficient
means of measuring a large sample of devices with identical
size, layout and environment [6-8]. A design-of-experiment
(DOE) with different layout styles and environments results
in devices with identical dimensions but with different layout
attributes. The large sample of measurements on these
identical devices, differing only in layout features, forms the
basis for reliable, statistically valid and accurate
measurement of the impact of layout on transistor
performance and variability.
The transistor array test structure used to study the impact of
layout on transistor performance has been described before
[8], and a brief review of its operation is presented in Section
III. Section IV provides an example of the use of these
structures in estimating the impact of layout on the
performance of core MOSFETs in a state-of-the-art 130nm
technology. This section also shows the advantage of using a
transistor array for evaluation of layout dependence over
comparison of devices from a large number of die. Section V
concludes the paper and suggests typical applications of
reliable data on the layout sensitivity of device performance.
II. TEST STRUCTURE AND MEASUREMENT
REQUIREMENTS
A key issue in evaluating layout dependence of transistor
performance is to minimize the confounding of layout effects
with other sources of manufacturing variation. Examples of
such sources of variation are across-chip and across-wafer
non-uniformity, wafer-to-wafer variation, and lot-to-lot
variation.
The need to minimize the impact of these confounding
sources of variation places the following requirements on test
structure design:
•
The structure should provide a large sample of
measurements for devices with a given layout so any
•
•
•
•
layout effects can be estimated with high statistical
confidence.
The layout should ensure that the devices have
identical neighborhood and environments.
The layout should be compact to minimize the
impact of across-wafer variation.
The test structure should minimize both the testing
and pad overhead associated with obtaining a large
sample of measurements.
The test structure should have a regular layout that
can be easily developed from layout generators.
Layout generators facilitate instantiation of layout
design of experiments (DOE) to systematically
investigate the impact of layout on device
performance.
substrate configuration has been used. For technology nodes
where the gate leakage is negligible, this solution remains
very attractive, since it reduces the required number of pads
for accessing the array columns. Moreover, it uses a small
number of pads for the control circuitry that, in turn, is also
shared with the other arrays on the same pad frame.
Transistor arrays can be designed to satisfy all these
requirements. Their regularity makes them suitable for the
development of layout generators. In addition, they provide a
large sample of measurements for devices placed in close
proximity. The multiplexing methods used to reduce the pad
requirements for arrays also helps in reducing the test time
required for testing a large sample of devices.
Another important consideration is the minimization of test
time, since a large number of devices per die are measured
from device arrays. Measuring complete current-voltage (IV) sweeps for each device on every die, and a large number
of die, is prohibitive. Instead, a carefully selected set of point
measurements on the I-V curve is preferred. The exact choice
of the measurement points can be application dependent. In
this study we measured three points on the I-V curve, off-sate
current (Ioff), drive current (Idrive) and threshold voltage (VT)
using a constant current criterion. Other measurements
schemes that allow efficient extraction of key device
parameters using a small set of measurements are also
suitable, for example the 3-point method for measurement of
Idrive, threshold voltage and transconductance [7][8].
III. ENHANCED MOS ARRAY TEST STRUCTURE
The need for both large sample size and minimal area
consumption suggests the use of the transistor array structure,
such as that illustrated in Fig. 1. The basic structure is
arranged in a 32 rows by 4 columns array of identically
drawn MOSFETs, giving a total of 128 samples per die. The
core array is surrounded by an extra row/column of dummy
elements required to preserve the uniformity of the device
neighborhood.
Each device is placed at the minimum distance allowed by
the routing constraint. The complete test vehicle has been laid
out by using a regular 2x16 pad frame. Each frame hosts six
arrays controlled by the same decoding logic.
The decoding scheme has been chosen to trade-off accuracy,
sample size and testing speed. For these reasons, a partial
shared drain, multiplexed gate and common source and
Figure 1: Schematic of a Transistor Array.
Each array column is directly connected to an external pad
that allows direct control of the device drain terminal, while
removing the need for an additional and more complex
decoding. Rows are then multiplexed by using a simple selfresetting scheme that uses rail-to-rail selection switches
controlled by an externally clocked, flip-flop based, shiftregister.
An additional criteria for the choice of such decoding
architecture is related to its intrinsic flexibility and
modularity. The use of a flip-flop based shift register,
coupled with the self resetting switches can be easily scaled
up or down to multiplex a different number of rows without
any constraint. This is an advantage when the test structure
layout is generated automatically. The basic layout structures
(e.g. the master slave flip-flop, self resetting switches, device
array, etc.) are generated by using a technology-independent
code that can be quickly adapted to different array and pad
frame configuration with almost negligible effort.
IV. EXAMPLES
To investigate the impact of layout style and environment on
transistor performance, a layout DOE was designed and
implemented using enhanced MOS array test structure
described in the previous section. Table 1 lists one such
DOE, implemented to assess the impact of poly proximity on
device behavior. Poly proximity is defined as the distance
between neighboring poly-silicon lines. For example, poly
lines in stacked gates, which are common in digital standard
cell libraries. In this example, MOS arrays with three
different poly-to-poly distances were designed: X = 0.16µm,
0.18µm and 0.2µm.
Table 1: DOE Description.
L
W
X
(a)
W (µm)
10
10
10
L (µm)
0.13
0.13
0.13
X (µm)
0.16
0.18
0.20
Fig. 2 shows an example of the impact of poly proximity on
drive current (Idrive) and the threshold voltage (VT) of a core
(thin-oxide) NMOS transistor in a state-of-the-art 130nm
CMOS technology. This figure demonstrates that the average
drive current of identically sized transistors varies inversely
with poly proximity, with closer poly lines resulting in higher
Idrive. This is also consistent with the observed impact of poly
proximity on the threshold voltage, VT, of the transistor;
closer poly lines result in smaller VT. The root cause of this
behavior could be that poly lines print narrower in a dense
environment (smaller proximity), compared to a sparse
environment.
The advantage of using a transistor array for the purposes of
estimating the impact of layout on device performance can be
seen by comparing Fig. 3 with Fig. 2. Instead of a MOS
array, each mean point (•) in Fig. 3 is obtained by measuring
one device per die, and calculating the average from 27 die.
The 95% confidence intervals are also presented, as in Fig. 2.
The comparison of Figs. 2 and 3 show that MOS arrays have
two advantages in estimating the layout dependence of
performance: precision and accuracy. In Fig. 2, the 95%
confidence intervals do not overlap, providing strong
statistical validity to the conclusions regarding the impact of
poly proximity on transistor performance. In contrast, in Fig.
3 the confidence intervals overlap, reducing the confidence in
the conclusions. Moreover, the MOS array provide a more
accurate estimate of the impact; the slope of the regression
lines through the points is much larger in Fig. 3 than Fig. 2
(the Y-axis scales are different). Consequently, if the
measurements shown in Fig. 3 were used for modeling the
impact of poly proximity on transistor performance for this
technology, it would result in an overestimate of the impact.
(b)
Figure 2: Impact of poly proximity on (a) Idrive and (b) VT of
W/L = 10/0.13 nMOSFETs from a 130nm CMOS technology.
The plots show the mean (•) and the 95% confidence interval
around the mean. The data is obtained from a 4 X 32 MOS
array.
The reason for the overestimation is that when the estimate is
obtained from measurements from multiple die and wafers,
the change in performance due to layout is confounded with
other sources of performance variation: e.g. across-wafer
non-uniformity and wafer-to-wafer manufacturing variations.
Enhanced MOS arrays also provide measurements to estimate
the impact of layout on variability of performance with high
statistical confidence. For variability estimation, it is even
more critical that all other sources of variation be minimized
to provide a reliable measure of impact of layout on
performance variation.
V. CONCLUSIONS
This paper described the use of a transistor array test
structure to evaluate the impact of layout on device
performance. An important consideration for assessing the
impact of layout is the ability to minimize the confounding of
performance variation caused by layout from other sources of
manufacturing variation. This requires compact test structures
that can provide a large sample of measurements. Transistor
arrays meet these requirements.
used to estimate the change in gate-length and form a
statistically valid motivation for OPC improvement.
We believe that continued technology scaling will increase
the sensitivity of transistor performance to the layout style
and environment. This will require that technology
development, device modeling, and circuit design will all
have to be aware of the impact of layout attributes beyond
just device dimensions. Test structures and analysis
techniques for accurate determination of the impact of layout
will be essential for driving this development.
REFERENCES
(a)
(b)
Figure 3: Impact of poly proximity on (a) Idrive and (b) VT of
W/L = 10/0.13 nMOSFETs from a 130nm CMOS technology.
The plots show the mean (•) and the 95% confidence interval
around the mean. In this case, the impact of poly proximity is
obtained by measuring one device from every die.
The use of transistor arrays for evaluating the impact of
layout was illustrated for a 130nm CMOS technology. It was
shown that for this technology reducing the distance between
neighboring poly lines of transistors with identical
dimensions results in a statistically-significant reduction in
the threshold voltage (VT) and increase in the drive current
(Idrive). The advantage of MOS arrays in providing
statistically-significant information about the impact of
layout was demonstrated by comparing the confidence
interval of MOS array measurements with those obtained by
measuring one device per die.
A test structure that allows statistically-significant
determination of the impact of layout has many applications.
It can provide data for parameter extraction in compact
models that support layout dependence of device
performance, for example the parameters related to impact of
mechanical stress on mobility [4]. Another application is to
define design-for-manufacturability (DFM) rules and
guidelines. For example, Fig. 2 can be used to restrict poly
proximity to a small range to minimize variation in device
characteristics over that region. Finally, statistically valid
information on the impact of layout can be used to drive
process improvement. For example, a likely reason for the
change in drive current seen in Fig. 2 is the gate length
variation due to OPC. The change in drive current can be
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