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S!LK
Capstone Design Ⅰ
1. CMOS Inverter
2. SONOS Memory
2014. 3. 13
Dae Hwan Kim
Jungmin Lee
Seungguk Kim
silk.kookmin.ac.kr
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<1>
CMOS Inverter
Basic Theory
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<2>
Basic Theory
CMOS inverter:
• Most basic element of digital static CMOS circuit
• Combination of an N-MOSFET and P-MOSFET
• One of the transistors is “ON” in the steady state, there is no static
current or static power consumption.
• Power dissipation occurs only during switching transient when a
charging or discharging current is flowing through the circuit.
VDD
S
PMOS
WP
LP
B
+
I DP  I DN
D
Vin
+
Vout
D
-
NMOS
B
S
• Drain terminal of nMOS and pMOS are common and
connected to the output terminal.
• Source terminal of nMOS is connected to the ground.
• Source terminal of pMOS is connected to the VDD.
WN LN
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<3>
Basic Theory
CMOS inverter I-V Characteristics:
Case 1) Vin= 0
Vgsn= 0 → nMOS “OFF”
Vgsp= -VDD → pMOS “ON”
⇒Vout= VDD by current path through pMOS as a pull-up transistor
Case 2) Vin= Vdd
Vgsn= VDD → nMOS “ON”
Vgsp= 0 → pMOS “OFF”
⇒Vout= 0 by current path through nMOS as a pull-down transistor
One transistor is “ON”, there is no direct current from VDD to the GND
⇒ No static power consumption
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<4>
CMOS Inverter
Structure & Reference
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<5>
CMOS Inverter (Reference)
CMOS inverter : cross-sectional view & circuit
(VDD = 1.2V, VIN = 0 ~ VDD)
n-type dopant : Arsenic
p-type dopant : Boron
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<6>
Reference Parameters
Geometric
parameters
Value
Process
parameters
Value
The other
parameters
Value
Ltotal [μm]
1.1
Nsub [cm-3]
7x1017
VDD [V]
1.2
Lg [nm]
65
Npg [cm-3]
1x1020
Cload [fF]
2.1
Lsp [μm]
0.1
NS or ND [cm-3]
1x1020
Cmos [fF]
2.1
Tox [nm]
1.5
Nhalo [cm-3]
3x1017
Hsub [μm]
1
 ox
3.9 (SiO2)
0.2
nMOS (pMOS)
gate type
n+ (p+)
polysilicon
Xj,SD [μm]
0.12
nMOS (pMOS)
source/drain
type
n+ (p+)
polysilicon
Wn orWp
1
nMOS (pMOS)
substrate type
p (n)
silicon
Hpg [μm]
[μm]
Xj,SD
<nMOSFET structure>
 ox
*nMOSFET/pMOSFET/MOS-cap :
 Type을 제외한 모든 parameters 값은 같음
 MOS-cap은 nMOSFET type
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<7>
Parameter Variables
Variables
Nsub
[cm-3]
Reference
𝟕 × 𝟏𝟎
𝟏𝟕
Npg [cm-3]
𝟏 × 𝟏𝟎𝟐𝟎
Xj,SD [nm]
120
Data #1
Data #2
𝟏𝟕
𝟏𝟖
1× 𝟏𝟎
𝟏 × 𝟏𝟎𝟏𝟗
60
1× 𝟏𝟎
Reference
Data #1
Data #2
Wn : Wp
1 : 2.5
1:1
1:4
Cload
1 × CMOS
0.1 × CMOS
10 × CMOS
εox
SiO2
HfO2
Si3N4
Gate
material
(qφm)
(nMOS : 4.05
pMOS : 5.16)
𝟏 × 𝟏𝟎𝟐𝟏
180
Nhalo [cm-3]
𝟑 × 𝟏𝟎𝟏𝟕
Tox [nm]
1.5
3
6
Lg [nm]
65
40
200
Wn : Wp
1 : 2.5
1:1
1:4
Cload
1 × CMOS
0.1 × CMOS
10 × CMOS
εox
SiO2 (3.9)
HfO2 (22)
Si3N4 (7.5)
𝟎
Variables
1 × 𝟏𝟎𝟏𝟖
Xj,SD
Polysilicon
nMOS : Molybdenum (4.53)
pMOS : Copper (4.7)
(CMOS = 2.1fF)
 ox
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<8>
Electrical Parameters
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<9>
Definition of Electrical Parameters
From transfer curve (IDS-VGS)
 Threshold voltage (VT)
 The boundary of on/off switching in transistor
 Subthreshold slope (SS)
 The variation of gate bias needed for increase
of 10 times drain current in subthreshold region
 Off current (Ioff)
 Drain current when VGS=0V
 GIDL current (IGIDL)
(Gate-induced drain leakage current)
 Drain current when VGS=-1V
 On current (Ion)
 Drain current when VGS=VDD
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<10>
Definition of Electrical Parameters
 DIBL factor (𝛿)
(Drain-induced barrier lowering factor)
 The variation of threshold voltage according to
the variation of drain bias

VT (VDS )
[mV/V]
VDS
What is DIBL?
 Condition : -short channel length
-High drain bias
 The decrease of energy barrier in
channel & source junction with
the increase of drain bias
 The increase of leakage current
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<11>
Definition of Electrical Parameters
What is GIDL current?
 Condition : VGS << VFB , VDS > 0
 Leakage current of drain-substrate junction
 Band-to-Band tunneling current of
duplicated region of gate-drain
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<12>
Circuit Performance
Index
(1) Voltage Transfer Characteristics
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<13>
Voltage Transfer Characteristics (VTC)
I= IP-IN
IDS
NMOS
Vin=VDD
Vout point: intercept
point of IP(Vin)=IN(Vin)
III
IV
PMOS
Vin=0
II
NMOS PMOS
Vin=0
Vin=VDD
V
I
Vout
VDD
0
 Operation mode
I.
pMOS linear 영역
Vout
IDN
=IDP
VOH
=Vdd
III
I
Slope
= -1
nMOS sat.
pMOS lin.
Both sat.
II
I
0 VTN
IV
V
Vdd - |VTP |
nMOS cut-off 영역,
nMOS lin.
pMOS sat.
V
Vin VOL= 0
VTN VIL VIH
Vdd
Vdd - |VTP |
II.
II
III
IV
Vin
nMOS saturation 영역,
pMOS linear 영역
III. nMOS & pMOS saturation 영역
IV. nMOS linear 영역,
pMOS saturation 영역
V.
nMOS linear 영역,
pMOS cut-off 영역
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<14>
Voltage Transfer Characteristics (VTC)

The ideal gate should have
•
•
•
•
Infinite gain in the transition region
Gate threshold located in the middle of logic swing
High and low noise margins equal to half the swing
Input and output impedances of infinity and zero, respectively
Vout
Ri = 
Ro = 0
g=-
Fanout = 
NMH = NML = VDD/2
Vin
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<15>
Voltage Transfer Characteristics (VTC)
V(y)
VOH
VOU
Slope = -1
H
VS
Slope = -1
VOU
LVOL
VI VI
L
H
V(x)

Voltage gain : AV= (∂Vout/ ∂Vin)

Vout= VOUH (output high voltage) when (∂Vout/ ∂Vin)= -1

Vin= VIL (input low voltage) when (∂Vout/ ∂Vin)= -1

Vout= VOUL (output low voltage) when (∂Vout/ ∂Vin)= -1

Vin= VIH (input high voltage) when (∂Vout/ ∂Vin)= -1

VS (switching voltage) when Vin= Vout

NMH= VOH - VIH : noise margin high

NML= VIL - VOL : noise margin low
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<16>
Noise Margin

Allowable noise level which does not hurt the logic operation.

For robust circuits, want the “0” and “1” intervals to be as large as possible.
VDD
VDD
VOH
"1"
NMH = VOH - VIH
Noise margin high
Undefined region (forbidden)
VIL
Noise margin low
VOL
VIH
NML = VIL - VOL
"0"
GND
Gate output
GND
Gate input
 Large noise margins are desirable, but not sufficient requirement.
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<17>
Circuit Performance
Index
(2) Delay Calculation
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<18>
Delay Definition
Vin
Vout
Vin
Propagation delay
Input
signal
50%
tp = (tpHL + tpLH)/2
tpHL
Vout
t
tpLH
90%
Output
signal
90%
50%
10%
Falling time tf
10%
tr
t
Rising time
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<19>
Delay Calculation
Propagation delay
① tpHL: pull-down delay time
Vin switches from 0 to VDD, Vout decreases with time
nMOS is at the saturation when Vout changes from VDD to VDD/2
② tpLH: pull-up delay time
Vin switches from VDD to 0, Vout increases with time.
pMOS is at the saturation when Vout changes from 0 to VDD/2.
I  CL
dV
dt
 t 
CL V
I DS
 t pLH 
CL (Vdd / 2)
( I DS , SAT ) p
, t pHL 
CL (Vdd / 2)
( I DS , SAT ) n
Propagation delay
Simple timing model
tp 
t pLH  t pHL
2
Simple inverter model
Reff ; effective on-resistance of transistor
CL ; load capacitance
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<20>
Switching Time Analysis (1)
VDD
VDD
tPLH
VOLè VDD/2
VOH
Vin
Iout
Vout
VOH è VDD/2
ILH
VOL
CL
CL
tPHL
VOH
IHL
CL
VOL
 Assumption
dV
C L dV
I  CL
 dt 
dt
I
⇒ rising & falling time of input signal is zero.
VDD 2
C L dV
 dt   I  t PHL  CL VDD dV I
VDD 2
 t PLH  CL 
dV I
0
t PLH t PHL
t P
2
Average propagation delay
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<21>
Switching Time Analysis (2)
I  CL
dV
C V
 t  L
dt
I avg
C L VDD 2
I HL
C V 2 
 L DD
I LH
 t PHL 
 t PLH

I avg ; charging or discharging average current
t P
t PLH t PHL
2
For deep submicron device, nMOS and pMOS remain in saturation region for all
times during switching VDD → VDD /2 and VDD/2 → VDD, respectively.
CL VDD 2
CL VDD 2
 t PHL 
, t PLH 
I Dsat,n
I Dsat, p

If we model a transistor as a resistor, tPHL = 0.69RNCL and tPLH = 0.69RPCL.
 RN 
V 2
VDD 2
L
L
, RP  DD
 RN  Reqn   , RP  Reqp  
0.7 I Dsat, p
0.7 I Dsat,n
W p
 W n
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<22>
Circuit Performance
Index
(3) Power Consumption
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<23>
Power Dissipation of CMOS VLSI
 Power Dissipation
P  I VDD
Ptotal  Pstatic  Pdynamic
2
C VDD
2
Pdynamic 
 C  VDD
f
T
[ J / s]  [W ]
Due to the charging and discharging of capacitances
Power dissipation increases linearly with switching
frequency.
Pstatic  I DC  I leakage  VDD
(T. Sakurai, ISSCC2003)
Due to subthreshold leakage , pn junction leakage, etc
; Cannot be ignored in VLSI containing millions of transistors
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<24>
Dynamic (switching) Power (1)
Total charge supplied by VDD and drained to GND ;
Average current ; I avg  Q Tavg  C L  VDD  f avg
Q  CL VDD
2
 Pdynamic  I avg  VDD  C L  VDD
 f avg
2
 Pdynamic   01  C L  VDD
 f CLK
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<25>
Dynamic (switching) power (2)
VDD-VT
Vin
Ishort

Practical dynamic power is larger than

Due to the short circuit power dissipation
t sc  t scr  t scf
PSC  I SCVDD
t
I SC  sc I SC ,avg
T
PSC 
t sc I SC ,avg
VDD  t sc I SC ,avgVDD f CLK
T
2
t sc I SC ,avg  CscVDD  PSC  CscVDD
f CLK
2
Csc   scCL  PSC   scC LVDD
f CLK
2
2
2
Pdynamic  01CLVDD
fCLK   scCLVDD
fCLK  CLVDD
fCLK
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<26>
Static (standby) Power


Critical in low-power battery-operated portable devices
Sources of static power dissipation

q V V V
• Subthreshold leakage

I sub  I s e
•
•
GS
T
nkT
o ffset
1  e



qVDS
kT
Junction leakage
DC current flow in ratioed logic such as pseudo-nMOS logic




Pstatic  I leak  VDD  I subthreshold  I juncton  VDD for CMOS

Subthreshold leakage can be reduced by
• Dynamically controlling VT ; by controlling the substrate bias,
higher VT during standby and normal VT during normal operation
• Reduction of VDS during standby ; series transistor to the pull-up
and pull-down paths for smaller VDS across each transistor, called
source degeneration
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<27>
TCAD
simulation
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<28>
TCAD simulation
n-MOSFET
device structure
MOSCAP
structure
n-MOSFET circuit
:transfer curve
p-MOSFET
device structure
p-MOSFET circuit
:transfer curve
Inverter circuit Inverter circuit
: VTC
: Transient curve
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<29>
Structure file
tdr file
<n-MOSFET structure>
MOSFET information
(Ex : electric field,
doping concentration,
EBD, etc…)
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<30>
2-D structure information
<Total current density>
<Electric field
& mesh information>
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<31>
1-D structure information
Dimension
cutting
Doping
concentration
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<32>
1-D structure information
Electric
field
Energy band
diagram
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<33>
Data export
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<34>
Data export
<Xftp>
Server connection
 STDB folder
 Saved folder
 Data export
to my computer
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<35>
Homework
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<36>
CMOS Inverter
Example #1. Nsub, Lg variation
1. [Table #1]에 주어진 공정변수 변화(Nsub, Lg)에
따라 아래의 소자변수를 비교하고 이유에 대해
논하시오.
(Lg variation : short channel effect 관점)
(1) Threshold voltage (VT)
(2) Subthreshold slope (SS)
(3) On current (Ion)
[Table #1]
Process
variations
Nsub [cm-3]
Reference
𝟕 × 𝟏𝟎𝟏𝟕
Data #1
𝟏 × 𝟏𝟎𝟏𝟕
Data #2
1× 𝟏𝟎𝟏𝟖
Process
variations
Lg [nm]
Reference
𝟔𝟓
Data #1
𝟒𝟎
Data #2
𝟐𝟎𝟎
(4) Off current (Ioff)
(5) GIDL current (IGIDL)
(6) DIBL factor (𝛿 )
(VDS=0.2, 1.2V)
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<37>
CMOS Inverter
2. 소자변수 변화의 관점에서
아래의 회로 성능지수를
비교하고 이유에 대해 논하시오.
(1) Noise margin (NM)
- VIL, VIH, NML, NMH
(2) Propagation delay
- tpHL, tpLH, tp, tf, tr
(3) Power consumption
- Pdynamic, Pstatic
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<38>
CMOS Inverter
Example #2. Npg variation
[Table #2]
1. [Table #2]에 주어진 공정변수 변화(Npg)에 따라
아래의 소자변수를 비교하고 이유에 대해
논하시오.
Process
variations
Npg [cm-3]
Reference
𝟏 × 𝟏𝟎𝟐𝟎
Data #1
𝟏 × 𝟏𝟎𝟏𝟗
Data #2
𝟏 × 𝟏𝟎𝟐𝟏
(1) Threshold voltage (VT)
(2) Subthreshold slope (SS)
(3) On current (Ion)
(4) Off current (Ioff)
(5) GIDL current (IGIDL)
2. 소자변수 변화의 관점에서
아래의 회로 성능지수를 비교, 설명하시오.
(1) Noise margin (NM)
- VIL, VIH, NML, NMH
(2) Propagation delay
- tpHL, tpLH, tp, tf, tr
(3) Power consumption
- Pdynamic, Pstatic
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<39>
CMOS Inverter
Example #3. Xj,SD, Lg variation
1. [Table #3]에 주어진 공정변수 변화(Xj,SD, Lg)에
따라 아래의 소자변수를 비교하고 이유에 대해
논하시오.
(Lg variation : short channel effect 관점)
(1) Threshold voltage (VT)
(2) Subthreshold slope (SS)
(3) On current (Ion)
(4) Off current (Ioff)
(5) GIDL current (IGIDL)
(6) DIBL factor (𝛿 )
(VDS=0.2, 1.2V)
[Table #3]
Process
variations
Xj,SD [nm]
Reference
𝟏𝟐𝟎
Data #1
60
Data #2
180
Process
variations
Lg [nm]
Reference
𝟔𝟓
Data #1
𝟒𝟎
Data #2
𝟐𝟎𝟎
2. 소자변수 변화의 관점에서
아래의 회로 성능지수를 비교하고 이유에 대해 논하시오.
(1) Noise margin (NM)
- VIL, VIH, NML, NMH
(2) Propagation delay
- tpHL, tpLH, tp, tf, tr
(3) Power consumption
- Pdynamic, Pstatic
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<40>
CMOS Inverter
Example #4. Nhalo, Lg variation
[Table #4]
Process
variations
Nhalo [cm-3]
Reference
3× 𝟏𝟎𝟏𝟕
Data #1
0 (No halo)
Data #2
𝟏 × 𝟏𝟎𝟏𝟖
Process
variations
Lg [nm]
Reference
𝟔𝟓
(2) Subthreshold slope (SS)
Data #1
𝟒𝟎
(3) On current (Ion)
Data #2
𝟐𝟎𝟎
1. [Table #4]에 주어진 공정변수 변화(Nhalo, Lg)에
따라 아래의 소자변수를 비교하고 이유에 대해
논하시오.
(Lg variation : short channel effect 관점)
(1) Threshold voltage (VT)
(4) Off current (Ioff)
(5) GIDL current (IGIDL)
(6) DIBL factor (𝛿 )
(VDS=0.2, 1.2V)
2. 소자변수 변화의 관점에서
아래의 회로 성능지수를 비교하고 이유에 대해 논하시오.
(1) Noise margin (NM)
- VIL, VIH, NML, NMH
(2) Propagation delay
- tpHL, tpLH, tp, tf, tr
(3) Power consumption
- Pdynamic, Pstatic
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<41>
CMOS Inverter
Example #5. Tox, Lg variation
1. [Table #5]에 주어진 공정변수 변화(Tox, Lg)에
따라 아래의 소자변수를 비교하고 이유에 대해
논하시오.
(Lg variation : short channel effect 관점)
(1) Threshold voltage (VT)
(2) Subthreshold slope (SS)
(3) On current (Ion)
(4) Off current (Ioff)
(5) GIDL current(IGIDL)
(6) DIBL factor (𝛿 )
(VDS=0.2, 1.2V)
[Table #5]
Process
variations
Tox [nm]
Reference
𝟏. 𝟓
Data #1
3
Data #2
Process
variations
6
Lg [nm]
Reference
𝟔𝟓
Data #1
𝟒𝟎
Data #2
𝟐𝟎𝟎
2. 소자변수 변화의 관점에서
아래의 회로 성능지수를 비교하고 이유에 대해 논하시오.
(1) Noise margin (NM)
- VIL, VIH, NML, NMH
(2) Propagation delay
- tpHL, tpLH, tp, tf, tr
(3) Power consumption
- Pdynamic, Pstatic
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<42>
CMOS Inverter
Example #6. Wn : Wp variation
1. [Table #6]에 주어진 공정변수 변화(Wn : Wp)에 따라
아래의 소자변수를 비교, 설명하시오.
(1) Threshold voltage (VT)
[Table #6]
Process
variations
Wn : Wp
Reference
𝟏 ∶ 𝟐. 𝟓
Data #1
1:1
Data #2
1:4
(2) Subthreshold slope (SS)
2. 소자변수 변화의 관점에서
아래의 회로 성능지수를 비교, 설명하시오.
(3) On current (Ion)
(1) Noise margin (NM)
(4) Off current (Ioff)
(5) GIDL current(IGIDL)
- VIL, VIH, NML, NMH
(2) Propagation delay
- tpHL, tpLH, tp, tf, tr
(3) Power consumption
- Pdynamic, Pstatic
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<43>
CMOS Inverter
Example #7. Cload variation
[Table #7]
1. [Table #7]에 주어진 공정변수 변화(Cload)에 따라
아래의 소자변수를 비교, 설명하시오.
Process
variations
Cload
Reference
1 × CMOS
Data #1
0.1 × CMOS
Data #2
10 × CMOS
(CMOS = 2.1fF)
(1) Threshold voltage (VT)
(2) Subthreshold slope (SS)
(3) On current (Ion)
2. 소자변수 변화의 관점에서
아래의 회로 성능지수를 비교, 설명하시오.
(4) Off current (Ioff)
(1) Noise margin (NM)
(5) GIDL current(IGIDL)
- VIL, VIH, NML, NMH
(2) Propagation delay
- tpHL, tpLH, tp, tf, tr
(3) Power consumption
- Pdynamic, Pstatic
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<44>
CMOS Inverter
Example #8. εox variation
[Table #8]
1. [Table #8]에 주어진 공정변수 변화(εox)에 따라
아래의 소자변수를 비교, 설명하시오.
(1) Threshold voltage (VT)
Process
variations
Oxide material (εox)
Reference
SiO2 (3.9)
Data #1
HfO2 (22)
Data #2
Si3N4 (7.5)
(2) Subthreshold slope (SS)
2. 소자변수 변화의 관점에서
아래의 회로 성능지수를 비교, 설명하시오.
(3) On current (Ion)
(1) Noise margin (NM)
(4) Off current (Ioff)
(5) GIDL current(IGIDL)
- VIL, VIH, NML, NMH
(2) Propagation delay
- tpHL, tpLH, tp, tf, tr
(3) Power consumption
- Pdynamic, Pstatic
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<45>
CMOS Inverter
Example #9. qφm variation
[Table #9]
1. [Table #9]에 주어진 공정변수 변화(qφm)에 따라
아래의 소자변수를 비교, 설명하시오.
Process
variations
Reference
Data
(1) Threshold voltage (VT)
(2) Subthreshold slope (SS)
(3) On current (Ion)
(4) Off current (Ioff)
(5) GIDL current(IGIDL)
qφm
nMOS : Polysilicon (4.05)
pMOS : Polysilicon (5.16)
nMOS : Molybdenum (4.53)
pMOS : Copper (4.7)
2. 소자변수 변화의 관점에서
아래의 회로 성능지수를 비교, 설명하시오.
(1) Noise margin (NM)
- VIL, VIH, NML, NMH
(2) Propagation delay
- tpHL, tpLH, tp, tf, tr
(3) Power consumption
- Pdynamic, Pstatic
Semiconductor devices & !ntegrated circuits Lab. @ Kookmin Univ.
<46>