Download Vin[265Vac]

FL7733 EVT1 System
Verification Report
Oct.29.2013
Power Conversion Korea
Inki-Park
Company Confidential
Schematics[8.4W]
LF1/
10mH
L
MOV1
/470
CF1
/47nF
BD1
/MB6S
CF2
/47nF
C1
/68nF
N
F1
1A/250V
NS
Co1
/470uF
DS1
/RS1M
R2 /30kΩ
D2
/1N4003
C3
/10nF
C2
/10uF
U1/
FL7733 EVT0
C5 /2.2uF
8 HV
VDD 4
6 COMI
Gate 2
VS 5
7 NC
3 GND
NA
Q1/
FQU5N60C
R6
/10Ω
CS 1
R5
/30kΩ
Rcs1
2.0Ω
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Cy1
2.2nF
R4
/200kΩ
Rcomp
/220Ω
2
+
CS1
/20nF NP
R1 /30kΩ
Do1
/ES3D
T1
RS1
RS2
/100kΩ /100kΩ
Rcs2
1.5Ω
C4 /5pF
Co2
/NC
Ro1
/20kΩ
Transformer[8.4W]
 Transformer Core : RM6
 Inductance of Primary side : 1mH
5
4
RM6 (PC47)
NP1(1à2)
2
NS+
NA(5à3)
3
1
Top View
NP2
NS
NS-
NP1
6
5
NS + àNS -
3
NP1(6 à1)
6
NA
1
2
No
Winding
Pin(S → F)
Wire
Turns
Winding Method
1
NP1
6 à1
0.20φ
54Ts
Solenoid winding
2
3
Insulation : Polyester Tape t = 0.025mm, 2Layers
NS
4
5
8
3
0.25φ (TIW)
30Ts
Solenoid winding
Insulation : Polyester Tape t = 0.025mm, 2Layers
NA
6
7
NS + à NS-
5à 3
0.16φ
20Ts
Solenoid winding
Insulation : Polyester Tape t = 0.025mm, 2Layers
NP2
1à2
0.20φ
27Ts
Insulation : Polyester Tape t = 0.025mm, 6Layers
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Solenoid winding
1. Protection
1) SCP
2) SRSP
3) SROP
4) ODSP
5) VS OVP
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SCP
 Concept
VDD
10/19V
LED short
VIN
+
8
HV
VCS
+
200ms
SS Timer
SCP is disabled
for initial 14 ms
4 VDD
VDD
16V/
7.75V
14ms
Timer
0.2V
19V
VDD ON
S/H
SCP
5
VS
10V
VDD OFF
200ms JFET regulation
0.3V
Gate
14ms
 VS voltage at gate-off is close to zero when LED load is shorted.
 SCP is disabled for the initial 14 ms once VDD is higher than UVLO.
 200ms JFET regulation enlarges AR time during SCP.
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Company Confidential
14ms
SCP
 Test Results
 Test condition: CCOMI[2.2uF], CVDD[10uF].
Vin[90Vac]
Vin[265Vac]
Ch1[VGATE],,Ch2[VIN], Ch3[VVS], Ch4[IOUT]
 SCP de-bounce cycle is 4 and operated well.
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SCP
 Test Results
 Test condition: , Rstr[30k], CCOMI[1.0uF], CVDD[10uF].
EVT0
EVT1
TSCP.bnk:14ms -->OK
VJFET.HL : 19V
TSCP.bnk:16ms
Ch1[VDD],,Ch2[VIN], Ch3[VGATE], Ch4[IOUT]
 TSCP.bnk of EVT1 was larger than EVT0.
 JFET regulation is operated well.
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Company Confidential
VJFET.LL : 13V
Ch1[VGATE],,Ch2[VIN], Ch3[VDD], Ch4[IOUT]
Current-mode SRSP
 Concept
TVCS-BNK
Gate
Vcs
TVCS  BNK 
Current
Mirror
1
Normal
RS
0.1V
VIN . DET
NA
Vcs Blanking
Time
Ivs
VIN.DET
RS Short
SRSP
Rvs1
5
Low Ivs
VS
Shut
Down
Rvs2
First GATE signal
TVCS-BNK
Vcs
Gate
5
CS
RS
0.1V
Vcs
Normal
RS
0.1V
SRSP
RS Short
High Ivs
 Current-mode SRSP protects the condition that sensing resistor is short before VDD-ON.
 Vin level is be detected by Ivs and TVCS-BNK is inversely proportional to Vin level.
 Once VCS is maintained under 0.1V for TVCS-BNK, SRSP is triggered.
 Current-mode SRSP is monitored only for first switching cycle.
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Current-mode SRSP
 Test Results
 Test condition: CCOMI[2.2uF], CVDD[10uF].
Vin[265Vac]
Vin[90Vac]
TonSRSP: 4.2us
VJFET.HL : 19V
VJFET.LL : 13V
Vin[265Vac]
TonSRSP: 1.9us
Ch1[VDD],,Ch2[VIN], Ch3[VCS], Ch4[IOUT]
 SRSP is operated well.
 JFET regulation is operated well.
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Company Confidential
Voltage-mode SRSP
 Concept
Sensing
resistor
short
VIN.DET
VIN.DET.PK
Current
Mirror
4R
6R
VIN.DET.PK
60% VIN.DET.PK
VIN.DET peak
detection
SRSP
enabled area
NA
Ivs
VIN.DET
Rvs1
VCS
5
VS
Rvs2
Shut
Down
Vcs
0.1V
5
CS
RS
0.1V
Gate
 Voltage-mode SRSP protects the condition that sensing resistor is short after VDD-ON.
 SRSP monitoring is enabled when Vin is higher than 60% of peak Vin.
 Once VCS is maintained under 0.1V for SRSP monitoring time, SRSP is triggered.
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Company Confidential
Voltage-mode SRSP
 Test Results
 Test condition: CCOMI[2.2uF], CVDD[10uF].
Vin[90Vac]
a
Vin[265Vac]
b
A
B
Rcs Short
SRSP Trigger
SRSP Trigger
Rcs Short
a
A
 Vin: a<b
 Vcs: a>b
Vcs < 0.1V
Vcs < 0.1V
B
b
Vin: 83V[≈130V *0.6]
Ch1[VDD],,Ch2[VGATE], Ch3[VCS], Ch4[IOUT]
 Voltage mode SRSP is operated well
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Company Confidential
 Vin: a<b
 Vcs: a>b
Vin: 248V[≈368V *0.6]
SROP
 Test Results
 Test condition: CCOMI[2.2uF], CVDD[10uF].
1.0us/div
100ms/div
Ch1[VGATE],,Ch2[VDD], Ch3[VCS], Ch4[IOUT]
 SROP is operated well.
 JFET regulation is operated well.
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Company Confidential
OCP[ODSP]
 Test Results
 Test condition: Vin[265Vac], CCOMI[2.2uF], CVDD[10uF]. Csn[20nF], Rsn[100k]
1.0us/div
100ms/div
VJFET.HL : 19V
VJFET.LL : 13V
Ch1[VGATE],,Ch2[VCS], Ch3[VIN], Ch4[IOUT]
 OCP is triggered with just one pulse.
 JFET regulation is operated well.
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Company Confidential
OVP – VDD and VS
 Test Results
 Test condition: CCOMI[2.2uF], CVDD[10uF].
VDD OVP
VS OVP
LED Open
LED Open
VDD: 24.8V
VDD: 17.3V
VVS: 3.1V
VVS: 1.56V
Ch1[VGATE],,Ch2[VDD], Ch3[VVS], Ch4[IOUT]
 After LED opened, VDD OVP is triggered at 24.8V.
 VS OVP is also triggered at 3.1V after LED opened.
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Company Confidential
OVP – VDD and VS
 Test Results
 Test condition: CCOMI[2.2uF], CVDD[10uF].
VJFET.HL : 19V
VJFET.LL : 13V
Ch1[VGATE],,Ch2[VDD], Ch3[VVS], Ch4[IOUT]
 JFET regulation is operated well.
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2. System
1) CC
2) THD/PF
3) Overshoot
4) Startup
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CC
1. Test results
 Test condition: RVS1[200k], RVS2[30k], COUT[470uF], CCOMI[2.2uF]
Rcomp[200Ω]
Rcomp[220Ω]
±1.05%
±0.59%
265Vac[50Hz]
230Vac[50Hz] 180Vac[50Hz] 140Vac[60Hz] 120Vac[60Hz]
90Vac[60Hz]
Rcomp[200Ω]
±1.02%
±0.88%
±1.18%
±1.19%
±1.04%
±1.19%
Rcomp[220Ω]
±1.78%
±1.48%
±1.33%
±1.34%
±1.19%
±1.49%
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Company Confidential
CC
1. Test results
 Test condition: RVS1[200k], RVS2[30k], COUT[470uF], CCOMI[2.2uF]
EVT0
EVT1
±0.59%
±0.6%
 Load regulation of EVT1 is having different pattern a little from EVT0.
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Company Confidential
THD and PF
1. Test results
 Test condition: CCOMI[2.2uF]
Vin[90Vac]
Vin[265Vac]
Ch3[VIN], Ch4[IIN]
Samples
#01
#02
19
Io [mA]
90Vac
265Vac
336
339
334
335
PF
90Vac
0.997
0.997
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265Vac
0.904
0.901
THD[%]
90Vac
265Vac
3.65
7.73
3.53
7.96
Overshoot
 Concept
18ms SS
counter
+
13ms
counter
VDD = VDD_ON
4 VDD
16V/
7.75V
VIN
Ivs
NA
1.1V
Rvs1
VCOMI .M 
VCOMI
Modulator
VCOMI .M 
1
Ivs. pk
IVS peak
Detector
VCOMI
5
1
Ivs. pk
265Vac
VS
Rvs2
6
1.1 V
13ms
COMI
18 ms Startup Time
 Vin level is detected by Ivs and VCOMI is charged by VCOMI modulator output.
 VCOMI modulator output is inversely proportional to Vin level.
 Therefore, VCOMI is adjusted close to steady state level during softstart time.
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90Vac
Company Confidential
Overshoot – 8.4W
 Test Results
 Test condition: CCOMI[2.2uF], CVDD[10uF], CVDD[470uF], Lm[1mH].
Vin[277Vac]
Vin[90Vac]
VCOMI_INT.CLP: 2.1V
VCOMI_INT.CLP: 1.1V
Vin[265Vac]
VCOMI_INT.CLP: 1.5V
Ch1[VDD],, Ch2[VIN], Ch3[VCOMI], Ch4[IOUT]
 VCOMI clamped at startup is inverse proportional to Vin level and operated well.
à There are no overshoot even fast On & OFF of AC power.
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Company Confidential
Startup time
 Test Results
 Test condition: Vin[90Vac], COUT[470uF], CCOMI[2.2uF], Lm[1mH]
Rstr: 30kΩ
178ms
Ch1[VDD],, Ch2[VIN], Ch3[VOUT], Ch4[IOUT]
 Startup time can meet 0.2s.
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Company Confidential
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