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Rochester Institute of Technology RIT Scholar Works Theses Thesis/Dissertation Collections 6-1-1986 CMOS analog transmission gate design Cynthia S. Bell Follow this and additional works at: http://scholarworks.rit.edu/theses Recommended Citation Bell, Cynthia S., "CMOS analog transmission gate design" (1986). Thesis. Rochester Institute of Technology. Accessed from This Thesis is brought to you for free and open access by the Thesis/Dissertation Collections at RIT Scholar Works. It has been accepted for inclusion in Theses by an authorized administrator of RIT Scholar Works. For more information, please contact [email protected]. CMOS ANALOG TRANSMISSION GATE DESIGN by Cynthia S. Bell A Thesis Submitted in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCE in Electrical Engineering Approved by: Prof. _Ly.::.-n_n_F_e_Fu_I_1e_r_ _ ._N_a_m_e_lIl_e-=g~ib_le___ Prof ._N_a_m_e_lIl_e-=g~ib_le___ Prof Prof. ____________________________ DEPARTMENT OF ELECTRICAL ENGINEERING COLLEGE OF ENGINEERING ROCHESTER INSTITUTE OF TECHNOLOGY ROCHESTER, NEW YORK JUNE, 1986 Title of Theda CMOS ~J~ Tmtls.OIt~'7i\ &w.l~§~ C_y___n_t_h_ia_S_u_e_B_e_II________ bereb~. I __ (grant , deny) permission to the Wallace Memorial L1braryl of R.I'-T. , to , reproduce my thesis in whole or in part. not be tor commercial use or profit. Any reproduction will -XI- ABSTRACT CMOS the technology has conventional CMOS analog with noise provided integrated electromechanical transmission due an to gate for the gates clock switch: degrade Eastman Kodak model developed and timing requirements for typically structured transmission gate An alternate proposed. device structure for the signals feedthrough parameter circuit transmission passed transients. CMOS process feedthrough devices improved for equivalent has gate. through SPICE A been cancellation have been performance them is in studied. -iii- OF TABLE CONTENTS Page LIST OF FIGURES LIST OF TABLES LIST OF SYMBOLS iv V vi INTRODUCTION BACKGROUND & 1 2 THEORY DISCUSSION Transmission Gate Test Transistor Evaluation A. B. 1 Experimental . a b I-V . Test Structure 17 Procedures 18 Procedures 19 gjj Test Procedures . 2. 7 Test Procedures Modified Gate and Channel 3. CMOS c . 12 Evaluation VT . , Process 20 . Transistor Characterization 22 Evaluation 24 Measurements RESULTS A . CMOS Process B. Transmission C. Proposed 29 Parameters Gate Model for Structure and Timing Improved 33 Requirements 39 Performance 41 CONCLUSIONS APPENDIX A APPENDIX B APPENDIX C APPENDIX D - - - - Modified CMOS Gate Process Parameter Gate Clock and Channel Transistor Characterization Extraction Timing Calculations SPICE Data Transistor Simulations Data -iv- LIST OF FIGURES Figure 1 Figure 2. Improved Switch Figure 3. Improved Switch Figure 4. Schematic Figure 5. Clock-Phase Figure 6. Circular Figure 7. Ron Figure 8 . Transmission Gate Figure 9 . Alternative Figure 10. Transmission Figure 11. P- Figure 12. Transmission gate Figure 13. Asymmetrical Clock Figure 14. Drain Voltage and P Gate Clock 17 Figure 15. Drain Voltage and N Gate Clock 17 Figure 16. Typical I-V Figure 17. Typical gM Figure 18. Typical VT Figure 19. Flared Figure 20. Segmented Figure 21. Photomicrograph Figure 22. Die Position Figure 23. I-V Curve: Model and Data T2 6u 31 Figure 24. I-V Curve: Model and Data T2 80u 31 . Simple FET vs. and 2 Switch 4 Cross-Section 5 Transmission Gate 6 Controller Pass 8 Transistor 8 9 Vin Leakage Transmission Gate Test Ron n-channel 10 Gate 10 Structure Vs Ron Model . 13 14 Vin Vin vs. vs. VG Circuit 16 19 curve 21 curve J , 21 curve Buried Channel FET 22 Drain FET vs. 14 of 23 Segmented Drain VT Device 24 26 -v- Figure 25. I-V Curve: Model and Data T4 6u 32 Figure 26. I-V Curve: Model and Data T4 80u 32 Figure 27. SPICE Transmission Figure 28 . Model of N-channel Transient 35 Figure 29 . Model of P-channel Transient 35 Figure 30. Model with Misaligned Figure 31. Model with Aligned Figure 32. Model with Retarded Figure 33. Model with .03 Figure 34. Model with .04 Figure 35. Model with .05 Figure 36. New Transmission LIST Gate Circuit Gate Gate 36 Clocks 37 Clock Slope Nanosecond N-channel Clock Lag.. 37 Nanosecond N-channel Clock Lag.. 38 Nanosecond N-channel Clock Lag.. 38 OF N-channel Gate 40 Structure TABLES Voltage 15 Width 15 1. Resistance Variation with Gate Table 2. Resistance Variation with Device Table 3. Agreement Table 4. SPICE Simulated Parameters 36 Clocks Table of 33 Model for and CMOS Measured Process I-V Curves... 29 30 -VI- LIST SYMBOLS OF Symbol Definition, Nsub Substrate (or ni Intrinsic carrier units dopant tub) concentration, t Thickness, *f Fermi U Micron P Mobility, W Device channel width, L Device channel length, 7 Body A Channel vG Gate vD Drain vs Source Vin Input VT Threshold VT0 Zero Q Resistance, Ohms K Boltzmann's constant, Kilo atoms/cm3 atoms/cm3 Farads/meter Permittivity, vk concentration, meters potential (10-6 meters) centimeters2 effect voltage, (signal) Volts Volts voltage. voltage. (103) Charge, ys MOSFET Kelvin Coulombs gain factor Volts Volts threshold q factor Volts voltage. Temperature, meters modulation voltage, T meters factor length bias /Volt-second voltage, Volts 1.38*1023 Joules/0 Kelvin INTRODUCTION CMOS the conventional The use of and reduce can to-digital for signal The processing switch Since which designer must configuration this work, switch transmission the are a Eastman that most signals Kodak improving into signals a circuit analog- isolate to gate. layouts efficient become sections building major data conversion, filtering, result of of their is gate is their resistive own. An and ideal by performance placed with meets and other minimum Company is the using suitable sought . They nature. semiconductor on-resistance no circuit switch requirements. gates which In rapidly distortion. Further, for process the no , power. integrated the circuit signal they have consume transmission on configuration zero would ideal, not closely but functions, many capacitance, optimize gate has transmission and and infinite off-resistance, emphasis small size lines, gate benefit can transmission the more for equivalent circuits. parasitic no the multiplex tristate data capability have would leakage, to to used often transmission gates drive no is to reducing die thus circuit switch: lead can gates logic design, limitations have logic, converters, Transmission integrated an electromechanical gate circuits. block provided transmission This speed. of has technology CMOS a at 2 BACKGROUND AND The simplest the Field can be switch THEORY switch to transfer currents charge, implementation is Effect Transistor used as - with (FET) between two switched in nodes figure filters, 1. large with loops, alternative capacitor transistor, pass shown to voltage a or where to such FET as switches impedances, to transfer charge is conserved. ^ l 1 <R Figure The signal at the 1. Simple Vout output, Vout depends on the iDsat where JS is composed the of = With the VGS, controls This switch first is appropriate a the = result of the the (D device, - / 2toxL( the or has passage requirement , (2a) and geometrical 1 AVDS) voltage three ID VT)2 fabrication biases, implementation IdR ;8(Vgs //OXW blockage Switch , = through current FET of + on the (2b) gate of the device, signals. important for parameters, limitations. conduction: The the voltage 3 - the on gate This voltage. device the state must limits for also as a strongly dependent channel the third Qsat When an to state the the tend will drain. The the voltage change of the small A is a by out. in the device high reduction the node be can However, for high and time the may is signals the by in paths that the all to conducting is toward follows from For of the and potential the signal small . signal noise. Low gate voltage feedthrough has gate operation rapidly an abrupt switch to delay lost in the can be realized error but source the and in given the available be decreased directions, source the after (3) relation output. frequency can feedthrough by controlled the by slowing required not gate-to- VT ) - voltage gate this with signal voltage is the at the gate is limiting its the indistinguishable sampling frequency of deal from VD/2 - significant a conducting voltage, from charge ghost be the switched potential becomes this through passing on-resistance channel diffuse can channel clock can arises diminishes gate threshold . to low signal the in Its -C'oXWL(VGs electrons of circuits and settled part levels, frequency ramps, The output result = is channel follow the to The toward the (3). equation in nonconducting state, in charge VGS ch device n-channel An FET and the signals resistor. charge voltage, of swing limitation The by source voltage. temperature capacitance. gate-to-source gate nonlinear on The applicability. the of the voltage fixed a acts that exceed - the sampling. gating state Thus feedthrough. with the 4 - configuration current flows in the inverted channel (holes) will clocks of sacrifice the the cancel for improvement increasingly is additional control gate complex ^ M Figure The appropriate geometry for from equation (3). determined transistor dummy will consist amount Vq and of of are channel area is of are channel chosen charge, half that that then of the all will charge so the conduction the p-channel n-channel gate voltage The noise. area an for the FET extra circuitry. Switch to the the the of depend each the additional Both connected virtually have no Vo^ Improved 2. with scheme, ^ T ir> does the from the feedthrough reduce can it from transient transistors complementary phase When state. transient the connection but transistor, conducting opposite this Using this feedthrough the Thus, 2.1 figure additional ideally (electrons). and in is switched, state in shown - channel the transistor dummy switch source output on FET FET. transistor and node, charge. level develops should drain so be of be can of its transient The total VGS. the scaled the if same so vG amount that its 5 - This is structure still limited to gate voltage less below the on-state An additional is switch process the As The p-channel signal the in depletion effect can and that voltage be charge no circuits, the with as the tub additional input diffusion be must shift the body figure in an turn to 3. to In to tub the will the the difference exists This CMOS or well. n-well This change. transistor body diffusion. source voltage. the in threshold due fall not effect. n-type respect increase level signal the do which threshold depletion offset VT voltage in with an to to built changes represented by tying minimized insure cross-section are device the introduced due FET's swings signal n-well-to-input-dif fusion In unidirectional be is illustrated in input voltage, shift problem shown, - voltage. effect This between the 'Jî V/ J] fcodi^ Figure A further Improved 3. improvement complementary FET's over the connected Switch simple Cross-Section switch in parallel, as consists shown in of figure can will changes. <^^, on. 4 tub - 6 - A \fc MooV A Figure is There no longer because one matched FET's the of Schematic 4. with a Transmission limitation transistors 2v the on can threshold Gate voltage always [(Vn -lOv [ 5 -5v [ 5 Ov [ 5 +5v [ 5 +10v [ 5 - - p-channel 2] = on [-5 ( -5) > 2] = on [-5 0 > 2] = on [-5 +5) > 2] = off [-5 (+10) > 2] = off [-5 ( and the of levels known, (3). With primarily signals positive The device. resistance are are signals are partially FET transistor this are voltages. - - is scaling the can n) vTl? < (-2)] = off ( -5) < (-2)] = off 0 < (-2) ] = on +5) < (-2)] = on (+10) < (-2) ] = on ( the through at through the otherwise Once n- conducted greatest conducting; Vj < - - ~ (-10) primarily dominates. structure, - conducted on-resistance conducting the gate HVn VTl? > > transistors both equation Vfp> (-10) - device channel when - input Negative the - - signal p-channel n-channel iin 5v and the Consider conduct. voltages, of swing the gate points the on- voltage be determined using transistors should be scaled 7 - so their The with gate-to-channel problem of feedthrough in transients moment and the level. the device and threshold This cancellation. with a For some applications, and also tracks with circuit.2 employs an extra The integrated the p-channel technique is converters . a steeper will gate be shift with in processing a operational as other shortens the which signal, are such n- mobilities and signal requirements. concerns clock-phase figure those transmission circuits static in shown to a it 5, controls. on-period gates. with of This clocked as same holes the these includes the at of temperature identical signal the addresses circuit, the applicable of variations gate node before off be must feedthrough the Further, ramp. To clocks gate output turned which in that eliminated clocks. lower mobility The solution feedthrough the the reach ideally voltage insure set transmission be also nontrivial control transistor most device processing The gate while repeatedly a voltages presents control electrons p-channel equal. circuits, to necessary and accurate that requires channel holes of for is This adjustable. critical are can (opposite phase) complementary minimize capacitances feedthrough gating - A/D 8 - DUMMY CONVERSION UNIT FEEDTHOUGH ERROR SIGNAL INTEGRATOR In rectangular device the either gate back one Clock-Phase FET's, the channel state. The of the toward device, The result has been is a charge input, signal making shown equivalent channel from from source source very large the transistor, error the provides wedging reduce OCL1 charge a or and j more Circular Pass modifying conducive the output. drain has by the as shown by 60S in over Transistor path In been drain very the D 6. be had can asymmetric toward to when symmetrically device. 3 rectangular Figure and region than the /$ channel arises OCU1 AM improvement rather semi-circular to splits charge A potential improvement asymmetric by maximized Controller 5. asymmetrically doping the distribution PHASE SHIFTER Figure changes geometry. CLOCK 4M figure the small. 6. It 9 - Dependence these for Transmission the standard gates exhibit is varied. voltage and signal Figure configurations. dependence gate temperature on The - 7, voltage G. by Bouhasin, configuration a given impedance nonlinear nonlinearity still is more exists in illustrates in figure as the pronounced all of this 4.4 signal with lower supply voltages. Voo*V*Z5*C Ron *15V<5>2SC Figure CMOS switches technologies of may the 5 8 when However, of Vs Vs is illustrates transmission gate Ron less exhibit polarity leak; Figure . 7. . vs. current When Vs in will than occur other and fabrication it is negative, the the n-channel device may off-state diagrammed leakage leakage some positive, the Vjn leakage figure 4. model will p-channel for the depend device leak. 10 - - y ?- cV\Of*v?i ~\\ (?, f 1 V Figure A number 8. designers of have developed circumvent the techniques include connecting feedback with a pair gain unity the reducing where a of temperature loop for low configuration provides which impedance the of is are in shown gain 6-13 transmission high bipolar, DMOS incorporated. I3-15 in a buffering impedance, In . Such gate and series nonlinearity required, figure . compensation, a to techniques limitations always-on stage transistors is an and on-resistance CMOS impedance and Model application temperature effect Leakage Transmission Gate , One situations or another such 9. ?\ JL .vW LfL <^> jf % vV Figure To reduce added in the 9. Alternative on-resistance, parallel. Another a FET Transmission second pair insures of that Gate transistors the structure has been will be - held in cutoff device built Vinf a leakage in result connected in to the of Vin the A discussion presented. since of the in it is p-well body the - may turn effect. it Is structures to likely on-state; off -state, the more 11 off To to leak. for early minimize the reduce connected examined in to The n-channel low this, values the of p-well is sensitivity to V-.4.16 this study will now be 12 - - DISCUSSION The Eastman Kodak CMOS channel devices devices are devices previously structure are built Finally, could deals the with discussion be the of transmission n- parallel Since tests modulates in gather gate TEST test gate containing geometries on both which part of also and shorter modeling discussion the is It then and was long CMOS structure. transistors structure, FET's p-channel The p-channel same width of larger the source, the source-to-channel the source in shown the followed by CMOS test structure (T12, source depletion serves interface. a and region to 10, holding laid was T13, depletion due the figure to connected geometries between difference a structure gain process STRUCTURE source-to-n-well the test test from test A examined. of to first The types evaluated performed extracted. p-channel several project, channel data the n- was gates and were modified this and hence wafers, tests. and different the to p-type bulk Another gate on Kodak were at problem. follower. FET variation In n-well. transmission GATE TRANSMISSION three an modified characterization an the length FET's parameters and in the of evaluated. of fabricated processed with The based in transistors a is containing transmission understanding channel process T14) the n-well to body reduce the The result is with offset the effect. voltages net a capacitor out symmetrically to consists around modulation transistor at which 13 - less exhibits in shift VT with - Vln Ml M2 M3 W/L W/L W/L T12 40u/10u 40u/10u T13 44u/10u T14 50u/10u Test Structure N< rvu "V ^ lTT. 120u/10u <oi 4=^F mi Figure The test structure resistance p-channel this The the . 6v was was typical behavior, reaches -.7 volt. junction becomes as At Next, the varies . for at shown this test structure Over a the was This it in working test range was signal and p-channel The 7, is of performed until not to 10 for 5 Vjn and follow Vin another available dependence the 0 to curves that and devices tied probable for of was figure n- voltages. VG with 11. Information evaluated on- voltages p-channel n- figure is signal volts and The previously point, +20 The n-well in in change previously discussed, n- volts. biased. standard considerably. -7 the positive to -5 individually forward determination. VG voltages biased exact with from Structure negative for primarily swept As for respectively. shown are primarily conduct Vin Vin. Test for evaluated voltage, conduct -l.Ov. substrate first was threshold and resistances Transmission Gate signal devices test, volts. were with devices channel For 10. volts, gate of for Ron Ron voltages of GRAPHICS xxxxxx PLOT xxxxxx GATE T12 TRANSMISSION RON Var laolei: (0 VIN ) -Ch Linear 1 sweep Start -B.OOOOV 20.000V Stop Step 10.00 1260V . E+03 Constanta: VDD -Ch2 vsua -Ch4 -7.oooov VN -Val -S.OOOOV VP -Vs2 -S.OOOOV .0000V 1.000' /div f\~ p eM - orvLu c_k o\U, .0000 20.00 -5.000 P- Figure 11. aoi- (o ) - xxxxxx ( V) 2.500/div VIN n-channel and R vs. on V, in (VOD-VIN! /I3Q GRAPHICS PLOT TRANSMISSION T12 xxxxxx GATE RON to ) CURSOR (.7160V i 19. . verlablel: VIN -Chi 541E+00 Linear < sweep Stert -5.0000V 20.000V Stop Step 5.000! E+03 . Constants: VOD -Ch2 VSUB ,5000 /d i v i \t, \). ' - \Ov ,0000b= 20.00 -5.000 VIN Figure 12. PON (O ) - 2.500/div Transmission Gate (VOD-VIN)/IO0 ( V) RQn vs. Vln vs. V -Ch4 . 1260V 0000V -7.0000V VN -Vsl 10. 000 V VP -Vs2 -10.000V 15 - lOv. 5v, reduces range the are volts. in variation the of variation data 2.5 and gate and higher The use of Ron and also transmission with - voltage signal supply increases Typical gate. gate are functional the the of curves resistance figure in shown voltages The 12. below. summarized Resistance Device Gate Voltacres T14 10 T14 T14 Table The effect p-channel resistance of device 1.4 KG KG 2.8 KG 1.1 KG 3.4 KG 5.2 KG 1.8 KG Resistance device size width decreases on variation Ron was decreases Ron. approximately 35 P-Width Voltage Gate Device 1. KG KG 1.7 .75 5 2.5 Change Max Min .65 with Gate G/u increase An examined. For Voltage gate -7v voltages, Resistance, -7v 40u 2.6 KG -7v 44u 2.45 KG T14 -7v 50u 2.25 KG Also of clock the interest correction. transient . is Resistance Vari the feedthrough gating Simultaneous analysis. The gate clock clocks circuit that were is occurs used given the maximum T12 2 the width. additional T13 Table in in without to gate examine figure 13. 16 - f wv- ?> Figure The clocks delays, logic well were node voltage, the amount of time investigated in aspects voltage allowed the gate but held for gate The with and with the a the is and 500 is clock slow and n- 300 shown in are n-channel of from the were likely the quick G, transient waveforms later. a capacitor pF, arrival This These described / waveforms capacitor discharge. for characteristics transient the 1 n-channel magnitude. simulations P6056 clock The substrate, drain the turn-off falls on source, shows increases then transient. the The clock. voltage and 14 filtered and Tektronix a p-channel drain all previous with levels inverter circumvent simultaneously. occurred test, Figure p-channel abrupt n-channel in this ground. device, drive to For to microprocessor transmission an p-channel repeatable of the Clock Circuit switching buffered measured The clock. delayed at The for by the fall. as and 15. pictured gate slow held probe, figure the a that were and Asymmetrical generated insuring rise MHz 13. were levels - the result indeterminate were 17 - - nsu 14 Figure Drain Voltage geometries of transistors because of their interest were 15. and used devices to were Parameter the tested a I-V on Three curves, curves. discussion using the An were modified characterize Analyzer. transistor: voltage and / Clocks Gate EVALUATION TRANSISTOR Seven 560 rvfcii/j.V Kodak geometries CMOS tests transconductance explanation several of devices. the and process. Hewlett-Packard standard Three evaluated. 4145 were of remainder All of these Semiconductor performed curves, test the were and procedure on every threshold precedes the 18 - I-V TEST This test also determines the typical curve voltage for held ground at voltage is and presence in shown This figure test gate is the drain drain biased bias reverse current substrate is with is ID the sweeping and to related located are drain are source the the A highest In substrate. to the gate-to- by voltages *D by The n-well data additional and performed The maintaining the 16 A. parameter, modulation It behavior. transistor normal voltages. potential. region, of length channel various used, linear source the verifies in Appendix B. the - = (4a) VT)VDS - y8(VGS where >8 The threshold typically drain rather more voltage, defined current as z/OXW VT the flows. arbitrary, commonly = and applied. . / can be voltage However, as 2toxL(l a + AVDS) measured at the result, which choice other with a of (2b) this test. predetermined current measurement level It is amount of is techniques are 19 - xxxxxx GRAPHICS - PLOT xxxxxx T2. N-CH ENH. POLY 2. B0X6um (IDA) Variable 1: VDS MARKER f 4.5000V ? RPRmA -Ch3 Linear sweep Start 3.000 0000 V 7.5000V . Stop Step .0750V Verleble2: VG Start -cn2 . Stop Step 3000! /div 0000 V 4.0000V 1.0000V Constants: vs -cm .oooov VSB -Ch4 .OOOOV .0000 0000 VDS Figure Typical 16. 7.500 7500/div I-V ( V] Curve gM TEST The varying VG and constant gM The test provides various held a at are is in to ability I Vds in mobility the of performed voltages. potential typical located / dVGs measurement test ground device's vary ID with VDS. changes precise A the dins drain-to-source potential. data = reflects transconductance are is transconductance curve Appendix and is B. constant with applied Again, shown The fields threshold voltage. by sweeping the (5) the n-well in at figure threshold the gate substrate a 17 and The voltage and for source positive and voltage additional is measured 20 - by extrapolating along transconductance Vf down curves the to the of edge rising family voltage gate of axis. Gamma , As the - previously discussed the threshold voltage, effect factor, 7, transmission gates. voltage the gate well the with and drain biased This the the the accurate for for root of V>S (VGS of by sweeping or substrate voltages The body threshold performed various the and in shift drain the , modeling region. saturation square is drain and gate the test together voltages in for accounts bias. Sweeping against plotted Gamma substrate biases. device important are VT together gate current n- keeps voltage is for since saturation, ^Dsat the Extrapolating voltage, VT for a Vf , number calculation substrate A typical contained for of curves a of the doping, curve in is = back particular substrate desired to - the VG substrate biases on parameters (6a) VT) axis gives bias, each even the Vge- device with threshold Measurement allows accurate uncertainty in Nsutj. shown Appendix B. in figure 18 and additional data of are -21- xxxxxx GRAPHICS T2 N-CH PLOT ENH xxxxxx 80X6UM 2 POLY gm Var labial: (/n) CURSOR ( 1.4500V rliARKEBJ._1^4500.V. i . 470E-06 . 285E-Q6 -Cn2 VG Linear sweep Start Stop Step .ooo; E-03! . 0000 v 5.0000V .0500V Variables VD -Ch3 Start .5000V 2.5000V Stop Step .5000V Constanta: VS -Chi .0000V VSB -Crt4 .oooov .0000 5.000 0000 VG 1 6RAD CNEli i - 5000/div . "Txin'tercept! 1/GRAD 1.96E+03: 511E-06 ( V) Yintercept j 529E-03 -270E-06 p . (/n) AID/AVG - Typical Figure 17. xxxxxx GRAPHICS g^ curve PLOT xxxxxx T2. N-CH ENH. POLY 2. 80X6um SID Ia verleblel: j CUF SUH ( MAF KER 2..5200 V 7650 V . . 17. J 5E-0 3. VG 967E :-06 Llneer -A / / / / [/ /> / / / / / onpn / ,/ s t J 1- -> /^ VS y/ VV /, </ y / ; i 3.000 .0000 VG GRAD . 3000/div 1/GHAD Yintercept1 13.1E-03 76.1E+00 765E-03 :iE2. 13.7E-03. 73.0E+00, 1 sio (a ) - (V) Xintcrcept ,,E1 . 25E+00 "-10".~0E-6"3~~i , -17 .1E-03 /ID Figure 18. Typical V 7p curve .OOOOV -4.0000V -1. OOOOV Conetante: /}. / / .0300V Stop Step /\ ./ . 3.0000V Variables: vsb -en 4 Start /r\ 2.911 div ,0000V Stop Step A / swoop Start PS.'.P E-03 -Ch2 j -Ch 1 .OOOOV 22 - - MODIFIED GATE AND CHANNEL TRANSISTORS A test structure Three devices examined. An unmodified channel device devices are device and were The is of flared same buried nonrectangular the channel other digitated this test as reference a contact on rather The structure for various the variation is channel length and channel implant device, area device narrows 19. the than shown Flared in microns. fabricated As figure intentional Channel with the three The in drain edge the channel separations. mask figure 19, connection. FET laid The devices a was 20. the the reduce could drain FET, along of geometries illustrated at interest. feedthrough charge, two Buried uniform The symmetry. was of was flared buried a and mask. segmented a gating significantly drain-to-channel was area width, channel for modifications the and were structure drain device. segmented buried Figure The served a dependent the in transistors n-channel modified important because both channel-to-drain which containing device The misalignment out design means with a boundary. provided provided for during fabrication, 23 - Figure The tests Typical Appendix A. The the normal examination, reasonable the data to no sign of complete not of the expect were from with the slightly is slight under the drain. any of thirty on are drain in the was 21. from Unfortunately, these in Upon devices, It close A apparent. figure these performance currents. variation of contained mimicked reduced shown the characterization. tests segmented device on performed the that available Drain FET drain devices segmented segmentation were curves devices, photomicrograph to Segmented previously described structures. of 20. - is normal is due processing precluding 24 - m - ^^^ 1 i hIbb Figure The data The I-V to be from do curves Lack explanation this 6u group and channel of 80u 84 nature, devices the expected slight a on these Drain devices channel with data Segmented of Device are more behavior. variation devices unusual They due to precludes . appear body an behavior. MEASUREMENTS standard for buried exhibit process CHARACTERIZATION A not in of of Micrograph flared the resistive effect. 21. ^vi* both are n- transistors and p-channel identified as of consisting T26 devices and were T280 channel lengths of The n- examined. (test structure 2) 25 - and the The previously described tests devices. Data D8319, wafer data channel presented. n- was voltage The which increase precision these The data. voltage can be increasing row and device matching, from these in variance device sets the threshold figure in seen 22. layouts In column. information may this n- interest possible The wafer the on only taking 25 data in of group, D8316, wafer Data . trend test T480. and therefore devices, significance A first The measurements points. with on data set, second no threshold location performed also in Appendix B. is data 10 T46 be . Modeling parameters design process from mobility, of gate, be noted. process pq junction , thickness, if data tox, dopant use data and design from derived were from both the drain specification depth, polysilicon from SPICE with the a process report specifications. the tpg; Important for measurements of combination wafer the its and require useful Data than as p-channel p-channel there identified wafers. The summarized that in voltages and and rather observed and were two on are indicates points taken were similarly nonfunctional presented data are had both contains are devices p-channel - xj gates device and run source concentration, lateral , Nsub. are low voltage diffusion, used, process sheet were dopant sheet Ln and type polarity must were resistance, , gate Rsh# and oxide nominal D3 UAFER MAP <4in. > -26- TCSTi D3 i UM MO ft HO .Jl ZEi_n- tMTCi t'/\o r\ru2Jf V_^ imfxi ho , , 3. .31, MTI> t..i ,, m.^j .! i l j -1 1 J I 24.3I| It,],! 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M.w|-^j;!-j^;j ' J k.h; ji.jii j aJ,J| 14,10, 3S,J*|~34,1!*37.J*! J | ... ~ 1 \Q r rail r\-r j I t..tri M.w, ., ., . - "M , J5,ll| 24.1|| I * J <4in. > * j J MAP TMT Ito i FL4T LCFT I WAFER l) T/~> l j D3 vcy D 9, RUM HO, (n V_ IU >FE MO, FLI LEFT .. UAFER MAP <4in. > ^ eT, 1^ f- f i'Xir, ;. . , , , , I 24. 311 2S,3I| 24, J, , I I j , I m.3.1 jj.joi J 24.3.J 7io | "ilT^; ! "a^Tô J "aaTai | ;_ J__j j -,,-_.'__ >l I -I- l 33.321 24>I2| 37.22, J*. 33, I l.JII 34)31 I I 25.311 24.211 27.21 1 '21 | I I 1 1 I 31 |3<| 32, 3*1 33.3*1 24.3*1 2S,2<| 24.241 27,2*1 I I I I I 1 I I -3.,^.j^j^j^|---~,1--;--_;!__|.__; -I iHH^'i -! -j -i i^jiîirs! 3I,I*| 33,l| 2J.I| 34.l*| 2S.1*| 24.1*1 27.1*, I _ I I I , 1 1 I 1 I I 1 1 I 22,l*| 3J,I*| 34.1*, 2Sil*| 24.1*1 37,1*1 I I I I I I I ; 2t,1*| I I- , ,- I 1 1 23.-j .[lT7.J7rs{-i77^!-5TuJ I ' 25,I7| 34:171 I 22,,.! . -, 1 I 3-1.17, I I I >*.3*| , ( 2<H7| 25.17, 24,17, ! I V. In each case, Y_ increased with column and Figure 22. Die Position vs. Vn row number. ! I 1 27 - From the I-V determined From the derivative the in slope of the [pnyVI = _d_L / (1 (unvW A = / (1 curves Measurement for Ip of the with in uncertainty substrate any first the can be value VSb VT)2 (8) biases, substrate of algebraically. desired some Nsut>. VT can Vgg, on each parameters be even calculated from VT0 7{ >T(VSB - 4>f was 2*f) + calculated (9) >T(2*f)} - from KT/q ln(Nsub/ni) = of Nsub Then VT - AVDS)Z determined doping, substrate *t and of Vr)2) - AVDS) be calculation bias = can number iteration, specifications. measured a accurate allows A VDS, and for V^ of VT In slope of AVDS) + 2tnvL)(Vr,<; + (1- AID / = with the 2toxL)(VGs dVDS device (2) equation region as dID/dVDS Using saturation is A parameter modulation channel by evaluating operation. defined the curves, - taken by data as the performing pairs with (10) median a from linear the form the process regression on the - b = y - m{ 28 - (11) } x where VT for values = vT0 VT0 and - 7 7{ >T(VSB + result. Next, 2*{) - 7 ^(2*t)) was (9) to used determine Nsub from * The devices were it wafer, An for values is average Nsub = >T(2Nsubq45si) resulting compared. Since reasonable to value for Nsub procedure was iterated procedure was performed available equation-solving results are required cGDO' and contained - the assume was until on a the that then Nsub to settled software was to a computer Other such the stable using The SPICE as 80/l/ same recalculate package. calculation on neighbors were Nsub used personal (12) measurements devices in Appendix C. straight-forward PB from / C'ox Nss, <Pf the on for both. The . This value. a 6jj and readily worksheets and variables Cjsw, Cj , CGsO' 29 - - RESULTS CMOS PROCESS PARAMETERS From the test information, Kodak 4, CMOS for verify n- the parameters' 23-26. overlaid Semiconductor To and fit 4.7 The tests. current the resistances Device T280 T26 T480 at a given in the is Table 3. very than VGS VD and 5 the affects . and contact for were is and the curves, volts through the in actual the 4145 the bias n-well adjustment are Packard detailed the To simulated, between between spacing This in as 80u and factor- Hewlett agreement good 6u the in asterisks, the with in table given modulation tests in the Eastman table was device I-V curves, indicates tub diffusion that are . JVds. Va = 4v 3v 2v 4.5v .6* 2.1* 1.3* 7.5v .3* 1.6* .8* 4.5v 1.4* 11.8* 16.4* 7.5v 1.6* 8.5* 18.3* .7* 1.6* 1.3* 1.2* 1. 1* .8* 4.5v .1* 5.3* 11.4* 7.5v 2.8* 2.3* 9.3* 4.5v 7.5 T46 The . transistor rather identical curves, collected Analyzer parameters, curve simulation data bias n-well the significant volts I-V the device data p-channel are sheet process transistors length channel SPICE simulated These FET's, fit, Parameter the to adjusted The the on measured the for model derived. p-channel for A, and measurements parameter was and except figures 3. SPICE a process the devices transistor Percent Difference in Simulated and Measured I-V Curves - 30 - NAME T2 T4 TYPE NMOS PMOS LENGTH 6um 80um 6um 80um LEVEL 2.000 2.000 2.000 2.000 TPG 1.000 1.000 -1.000 -1.000 TOX 7.11D-08 7.11D-08 7.11D-08 7.11D-08 NSUB 4.01D+14 4.01D+14 3.70D+16 3.70D+16 XJ 5.00D-07 5.00D-07 8.00D-07 8.00D-07 LD 2.00D-07 2.00D-07 6.00D-07 6.00D-07 UO 610.000 610.000 178.000 178.000 KP 2.96D-05 2.96D-05 8.65D-06 VTO 0.530 0.604 -1.070 -1.009 GAMMA 0.223 0.251 0.665 0.774 PHI 0.529 0.529 0.763 0.763 1.75D-02 1.55D-03 2.75D-02 1.55D-03 0.871 0.871 0.719 0.719 48.920 48.920 285.600 285.600 CGSO 2.91D-10 2.91D-10 4.85D-10 4.85D-10 CGDO 2.91D-10 2.91D-10 4.85D-10 4.85D-10 CJ 1.77D-04 1.77D-04 9.58D-06 9.58D-06 CJSW 8.85D-11 8.85D-11 9.58D-12 9.58D-12 MJ 0.500 0.500 0.500 0.500 MJSW 0.300 0.300 0.300 0.300 4.76D+11 4.98D+11 1.29D+11 1.48D+11 LAMBDA PB RSH NSS Table 4. SPICE 2G.5 Parameters for 8 . 65D-06 EK CMOS Process -31- ^xxx)( GRAPHICS PLO/T ****** T2. N-CH ENH. POLY 2. 80X80um ID varlaolel: (UA) VDS .MARKER 1 \ i 175.0 155. 2VA. .4.50jQ0Y... ! ; l^L.*: j . ...i. i ; i rJ i 1 -Ch2 Start .OOOOV 4- OOOOV 1. OOOOV " VS -Chi .OOOOV VS8 -Ch.4 .OOOOV - i 4.1. !**> i_ i cv / i i 4A i - | It 1 - .0000 VG : Constants: r ! u-*~r T t Variable^ : " 1 .. .0750V Stop Step i ! i /div .OOOOV 7.S000V Stop Step |1 i u is^ sweep Start : I 17.50 j. . -Ch3 Linear WWSfiSW SSSP o ta ,n i 1 1 1 1 i i 7.500- ,0000 VDS Figure 23. ****** ( V) .7500/div I-V Curve: Model Data for T2 80um and ****** PLOT GRAPHICS T2. N-CH ENH. POLY 2. 80X6um Varlablel: ID VOS (mA) Linear MARKER. (. A I 1 R000V. . 2 sweep Start -560mA 1 i -Ch3 .OOOOV 7. 5000 V Stop Step 3.000 .0750V Variables: VG -Cn2 Start .OOOOV 4. OOOOV Stop Step 1. OOOOV Conatanta: ,3000 /div VS -Chi .OOOOV VSB -Ch4 .OOOOV 7.500 ,000 ( V) .0000 VDS Figure 24. .7500/div I-V Curve: Model and Data for T2 6um -32- PLOT GRAPHICS ****** ****** 14. P-CH ENH. POLY 2. 80X80um ID Varlablel: (UA) VDS MARKER t -A 56 53.UA - .5000V. . . eweep Start -60.00 < ? -Cn3 Linear r:."".T .OOOOV Stop -7.S000V Step - .0730V r- variables: VG ^V t , - \6.000 /div -ChS OOOOV Start -Z. Stop Step -6.0000V . -1. OOOOV I Conetenta: i 1 i ...J.... ' ' ' ' ! ', * * * : i 1 ' i - - .OOOOV 5. OOOOV s\ ! i \\ ,- -Ch4 ^v 1 - -Chi VNW v '* '-**.? i _ r VS ....!.... ' ' ! V ' i I i i i i NX .0000 -7.500 .0000 VDS Figure 25. ( V) ,7500/div Model I-V Curve: and Data for T4 80um GRAPHICS ****** PLOT ****** ENH. POLY 2. 80X6um J A. P-CH Varlablel: VDS -Ch3 (mA) MARKER. -4 -5000V. ..-. 1 . 203mA Linear - ) sweep Start .OOOOV Stop * -1.300 '-.J J^_j_. Step a 9 . 5000 V .0750V i Variables: VG -ChS ^*"s^ Conatanta: 4> .... 1 ? ? ? 1 i""""-^^ 11 f ! ! r i i .ooooii i I i VT"- j I fl I ^rrrrrr-r TT~r~>~ i 1 i _.!_ __L_ *\ | i i i_ \\ i " i _'_ . . J ! 1 -7.500 .0000 VDS Figure 26. .7500/div I-V Curve: ( V) Model and Data for T4 80um VS -Chi .OOOOV VNW -Ch4 5.0000V 33 - - TRANSMISSION GATE MODEL AND TIMING To the evaluate was REQUIREMENTS feedthrough transient, The simulated. circuit is model standard a figure in shown transmission gate 27. VU v0O" <S -75KSl< Figure A series of Transmission simulations here described 27. are the was of ^?f SPICE this with run result Gate t Model simulations figures The model. which documented are in Appendix D. First, given was at the the with the to drain The drain the channel p-channel node Ov. VG lv to -6.5v. plotted in figure In figure goes during off, negative and voltage held = n-channel VG = because 30, the the Again, 29. the both gate, clock positive device and device In held off, VG = -iv to pulse are plotted because turn-on. the this positive transistors drain 5v. gate are feedthrough The in figure are given the pulled initially the clock = was impulse, pulse voltage the VGP into device step node into off, a 28. pulled was and impulse step n-channel voltage are a the configuration, holes iv, = electrons Next, p-channel VG are goes channel. iv, VGN = 34 - then -lv, enabled magnitude structure cancel negative as the each gate other- by turning it the Reducing carrier in modelled of the 33-35 figure gate 35 magnitude is too also by be in should SPICE by demonstrate the of timing. clock nanosecond, .03 the of before of the are holes in to clock the that the creating p-channel a to device device. slow linear from been important is are clocks has the transients, the different both plot it earlier, should transients two the electrons, n-channel cancelling noted this the of n-channel be in test gate structure when effect scale mobility that the of the of rate as rise can of be seen the filters R-C used. commonly Figures off aids It time discussed was lower slope 32. As and migration figure clocks on The the shows tail the this of so adjusted by transmission operation early departure the the ideal 31 transient. for the Figure to compensate in are reduced positive earlier clocks simultaneously. show reduced The 5v. = VGN -6.5v. is The enabled = transient seen evaluation. when VGP sequentially, transient, positive occur the of - is lag 30 sensitive affected temperature. figure in to 50 for by .05 dB both effect figure In 34 the the 33 the lag is .04 nanosecond. can be practical A use. in The gate the clock nanosecond, but the amount and high sensitivity n-chanhel reduction realized, fluctuations and in the clock of signal and lags by in transient placement reduction voltages, will and -p C o H (0 M o o o 8 o in a o z a ON CM z c i C! tn r- - u r - tn z ai c c a. z i i i * ri N ^ ! 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O o I 35 O c co c p o 39 - PROPOSED STRUCTURE FOR The transmission through an opposite transient two alternative of balancing let to the charge switching charge devices for in . by an charge charge in shown its to be a be to node and conserve the the used notion capacitor channel and follow the to path transfer A registers. much like that storage gate should very The this controlled the storage not voltage level. output is add 36. transfer With clock aside the will output input on to signal between already figure (CCD's). fall. can are could on put adjacent channel enable transient to paths and at This this make gate technique the structure an begins transients to impractical to path devices coupled gate the this is favorable is is temperature problem it of feedthrough now is It a Similar for necessary possible photocapacitor followed enabled the A providing node. or clocking track charge there. configuration possible other go capacitor, output to channel problem limitation the removing the make by transferring By photodiode The the storage to charge contributed potential main FET single a feedthrough transients. effective. that approach them structure. this and circuitry charge channel The adjustments An the offering which of FET's from evolved channel cancellation practical control timing never dummy a functional while has structure cancellation. cancellation and gate with to swing, enough IMPROVED PERFORMANCE polarity for progressed signal FET - gate while technique, for many for be the the sizes amount of of - % ; 7 z : ' ' i 1 \ T6 3T Z L i i d U\Vxrr* Figure - c 5 ST 40 .-. 36. New sr_T D A Transmission Gate Structure - 41 - CONCLUSIONS The problem of gating been reviewed. accurate A variety for model developed. Using goodness fit typically of the within 2% requirements device turn-on that further enough data may saturated Since an problem study be devices model indicates application, sensitivity These for times. this the given provide available at curves and process were data. technique recommended. to the this time to of which also a but an test to clock relative in circumvents recommended transistors. there conclusion. is the is gate control channel benefit, base to is It modified additional agreement sensitivity difficult is to simulated The and has been has Analysis considerable this gates have been tested devices. alternate is transmission CMOS Kodak I-V model, between in CMOS structures of Eastman this timing practical feedthrough not REFERENCES "All-MOS 1. Charge Techniques Journal Part Solid of pp. 379-385 2. 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March Elements Passive Circuits, Joins DM0S Electronic "New High and Distortion", Electronique, 51, No. A/D 1984. Analogiques Electronigue "Lateral S. J. Circuits, Analog Dialogue, 1983, Switch 9, Analogiques Allias, Multiplexeurs Analog MOS CMOS August Design, P. "Analog Integrated Harmonic 18, Design, Commutateurs and Control", 105-111. pp. 182-188. pp. 20MHz 7-Bit, Circuits pp. 14. August Design, "Simple "Les 5, Whitmore, Cuts Switch Analog Electronic Mourier Arrays", G. Circuits, Vol. 2, 1980, Linear J. Symbol", Andrews, Whitmore, J. State Gate Small-Signal Fast 1970, W. Machine Charge", Solid 16-17. pp. Design Yields "Clever Process", 10. Switch for for Publishing, Electronic Tominaga, 9. the 1981, Error CMOS of Integrated August News, Considerations 7. 2, Semicustom Design Mactier Advantage an of "Rely Transient International 158-159. pp. Bouhasin, IEEE Journal No. 3, 1985, pp. 16-22. Bolger, 1986 the of P. pp. pp. D. Hodges, 14-18. Denham and D. 35-38. Switching Times", pp. 93-103. C. APPENDIX A MODIFIED GATE AND CHANNEL TRANSISTOR DATA 16. 55, "CMOS No. 8, Analog Switches", August 1984, pp. Grossblatt, R. Radio-Electronics , Vol 69-72. BIBLIOGRAPHY "Modeling and Simulation of Insulated-Gate Field-Effect Transistor Switching Circuits", H. Shichraan and D. Hodges, IEEE Journal of Solid State Circuits. Vol. SC-3, No. 3, September 1968, 285- pp. 289. The Solid Device H. Electronics John Kamins, Analysis Meyer, State, and John for & Wiley Design Wiley Rosenberg. & Oxford Integrated Sons, University Press, Circuits, R. Muller and T. 1977. Analog Integrated Circuits, Sons, 1977. of 1975. P. Gray and R. :> o * X crs ^ rvi _ r\> rj rn is CT> <?" (T> O "- 0"* Lm r-7. r-^ E C^ (J' in pn 0"* ~ * 5 E p o o o o !"-- O '- -0 c o o o o li"? "* '^ *0 C"- nj o O . m o o o CT> o \S U"' tO CO > o O O o .. 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( tD > i ~i i X\ ^*5aWV N Q fAJ 1 i - a i ;CD -1 1 o D! !5 I - ST ! xi i<iHI a: ; an i IcDiCn , ; o o OO OO o o i i i 1 \*i OJ UJ HI Z Z M _1 M J * > o o o o > > o o > > > o in o o in .. rl O a 0 01 0) x: 3c O 0) 1 1 c ro p r_ 0 C CO 0 > > 1 iH c a a .. OJ o 0 1 J3 "" CD OJ T x: -* P a a o o p 4J i-l 4-1 _J to CO CO l c a a CO CD O CD C CO -P -P 4J 0 > CO co to c a p o c to o > > o iH C 0 > o o o o o o o o o o o o o o o o o o a ro H p -p! D. cn cn 03 o o l CJ i C UJ HI 03 0) in cn 4J C N N > > 1 <H r-C I P o a! s 03 cn o u o + c i UJ n 03 HI N o v. o C OJ in "H o X O H -PI^T m o o o o a + + < HI UJ cn CD ^ CD \ in <H CD CD cd! i i > i H Q M cn cn o o Q UJ HI <icn cn cc (Dim CD in vH . 1 a M CO ! <H OJ J HI z i_ M M _J -J *******02/09/86 IDS ******** VS INPUT VDS SPICE FOR THE 2G.5 EK NMOS (10ADG81) ********16:07:10***** T2 6 TRANSISTORS LISTINC TEMPERATURE = 27.000 DEG C *************,*********,************************** ********************* * C S BELL * VSUB VDS 9 20 0 0 DC 0 VGS1 1 0 DC 0 VGS2 2 0 DC 1 VGS3 3 0 VGS4 4 DC 2 0 DC 3 VGS5 5 0 DC 4 Ml 11 1 0 9 T26 L=6U W=80D NRS=.l NRD=.l AD=1280P AS=1280P PD=192U +PS=192U 12 M2 2 0 9 T26 L=6U W=80D NRS=.l NRD=. 1 AD=1280P AS=1280P PD=192D 0 9 T26 L=6U W=80D NRS=.l NRD=.l AD=1280P AS=1280P PD=192D 0 9 T26 L=6U W=80U NRS=.l NRD=.l AD=1280P AS=1280P PD=192U 0 9 T26 W=80U NRS=.l PD=192U +PS=192U M3 13 3 +PS=192U M4 14 4 +PS=192U M5 15 5 L=6D NRD=.l AD=1280P AS=1280P +PS=192D 20 20 VID3 20 13 0 0 VID4 20 14 0 VID5 20 15 0 VID1 VID2 .MODEL +XJ=.5U 11 12 0 T26 NMOS LAMBDA=. 01750 DO=610 TPG=1 TOX=.0711D RSH=48.92 PB = CGSO=2 NSDB = 4.008E14 .871 +CCDO=2.91E-10 CJ=1.77E-4 +LD=.2D .MODEL +XJ=.50 LEVEL=2 T280 VTO=.53 MJ=.5 CAMMA = .91E-10 CJSW=8. 85E-11 MJSW = .3 NSS=4.758E11 .2232 LAMBDA=. 00155 UO=610 TPC=1 TOX=.0711U NMOS NSDB = 4.008E14 RSH=48.92 PB = .871 CGSO=2.91E-10 +CGDO=2.91E-10 CJ=1.77E-4 MJ=.5 CJSW=8. 85E-11 MJSW=.3 +LD=.2U LEVEL=2 VTO=.604 GAMMA = NSS=4.983E11 .2509 + .MODEL T46 +XJ=1D NSUB 03181 UO=595 TPG=-1 TOX=.0711U 3.695E15 RSH=285.6 PB = CGSO=4. 85E-10 LAMBDA PMOS = = . .719 +CGDO=4.85E-10 CJ=.958E-5 MJ=.5 CJSW=.958E-11 MJSW=.3 +LD=.6U LEVEL=2 VTO=-1.070 GAMMA = .6645 NSS=1.291E11 + .MODEL T480 PMOS LAMBDA = . 00184 +XJ=1U NSUB = 3.695E15 RSH=285.6 +CGDO=4.85E-12 *LD=. 6U LEVEL=2 .WIDTH CJ=.958E-5 VTO=-1.009 MJ = .5 UO=957 TPG=-1 PB = . 719 TOX=.0711U CGSO = 4. 85E-12 CJSW=.958E-11 MJSW = CAMMA = .7736 NSS=1.478E11 OUT=80 .OP DC VDS 0 7.5 .183 PLOT DC I(VID5) ICVID4) I(VID3) M0.3.3E-3) .PRINT .END DC I(VID5) I(VID4) I(VID3) I(VID2) I(VIDl) . 3 *******02/09/86 ******** SPICE 2G.5 (10ADG81) . ********16: 07: 10***** IDS.VS VDS FOR THE EK NMOS T26 TRANSISTORS MOSFET MODEL PARAMETERS TEMPERATURE = 27.000 DEC C ***************************************^^^^^^^^^^^^^^^^, TYPE T26 T280 T46 T480 NMOS NMOS PMOS PMOS LEVEL 2.000 2.000 VTO 0.530 0.604 -1.070 -1.009 2.96D-05 2.96D-05 2.89D-05 4.65D-05 GAMMA 0.223 0.251 0.665 0.774 PHI 0.529 0.529 0.644 0.644 1.75D-02 1.5 5D-03 3.18D-02 1.8 4D-03 0.871 0.871 0.719 0.719 GGSO 2.91D-10 2.91D-10 4.85D-10 4.85D-12 CCDO 2.91D-10 2.91D-10 4.85D-10 4.85D-12 48.920 48.920 285.600 285.600 CJ 1.77D-04 1.77D-04 9.58D-06 9.58D-06 MJ 0.500 0.500 0.500 0.500 CJSW 8.85D-11 8.85D-11 9.58D-12 9.58D-12 MJSW 0.300 0.300 0.300 0.300 TOX 7.11D-08 7.11D-08 7.11D-08 7.11D-08 NSUB 4.01D+14 4.01D+14 3.69D+15 3.69D+15 NSS 4.76D+11 4.98D+11 1.29D+11 1.48D+11 TPG 1.000 1.000 -1.000 -1.000 XJ 5.00D-07 5.00D-07 1.00D-06 1.00D-06 LD 2.00D-07 2.00D-07 6.00D-07 6.00D-07 UO 610.000 610.000 595.000 957.000 IKP LAMBDA :PB RSH 2.000 2.000 *******02/09/86 . **** ********* IDS ******** VS VDS -SPICE FOR THE 2G.5 (10AUG81) ********16:07:10***** EK NMOS T26 TRANSISTORS DC TRANSFER CURVES TEMPERATURE = 27.000 DEC C *******************,it^***************************************,v VDS 0. 000D+00 1.830D-01 3. 660D-01 5.490D-01 7.320D-01 9.150D-01 1.098D+0 0 1.281D+00 1.464D+00 1.647D+00 1. 830D+00 2.013D+00 2.196D+00 2.379D+00 2.562D+00 2.745D+00 2 9 2 8D +0 0 I (VID5) 1.368D-48 2.597D-04 5.058D-04 7.382D-04 9.570D-04 1.162D-03 1.353D-03 1.531D-03 1.694D-03 1.844D-03 1.979D-03 2.100D-03 2.206D-03 2.298D-03 2.376D-03 2.43 8D-03 (VID4) -3.867D-13 1.074D-04 1.070D-03 1.139D-03 1.193D-03 1.232D-03 1.255D-03 1.264D-03 1.269D-03 1.274D-03 2.632D-03 5.307D+00 2.642D-03 5. 490D+00 2.652D-03 1.349D-03 3.477D+00 3.660D+00 3.843D+00 4.026D+00 4.209D+00 4.392D+00 4.575D+00 4.758D+00 4.941D+00 2.612D-03 2.622D-03 (VID3) 1.839D-04 3.535D-04 5.089D-04 6.500D-04 7.76 8D-04 8.892D-04 9.871D-04 5.124D+00 3.111D+00 3.294D+00 I -4.947D-14 1.279D-03 1.284D-03 1.289D-03 1.294D-03 1.299D-03 1.304D-03 1.309D-03 1.314D-03 1.319D-03 1.324D-03 1.329D-03 1.334D-03 1.339D-03 1.344D-03 . 2.486D-03 2.518D-03 2. 535D-03 2.54 5D-03 2.554D-03 2.564D-03 2.573D-03 2.583D-03 2.593D-03 2.602D-03 I 1.999D-04 2.776D-04 3.403D-04 3.882D-04 4.210D-04 4.386D-04 4.427D-04 4.44 6D-04 4.465D-04 4.484D-04 4.502D-04 4.521D-04 4.539D-04 4.558D-04 4.576D-0 4 4.595D-04 4.614D-04 4.632D-04 4.651D-04 4.669D-04 4.688D-04 4.70 7D-04 4.725D-04 4.744D-04 4.763D-04 4.782D-04 4.801D-04 4.820D-04 4.840D-04 5.673D+00 2.662D-03 1.355D-03 4.859D-04 5. 856D+00 2.672D-03 1.360D-03 4.878D-04 4.89 8D-0 4 6.039D+00 2.682D-03 1.365D-03 6.222D+00 2.692D-03 1.370D-03 4.917D-04 6.405D+00 2.702D-03 1.376D-03 6.588D+00 2.713D-03 1.381D-03 4.937D-04 4.9 5 7D-0 4 6.771D+00 2.723D-03 1.386D-03 4.97 7D-0 4 6.954D+00 2.734D-03 1.392D-03 4.997D-04 7.137D+00 2.744D-03 1.397D-03 5.017D-04 7. 320D+00 2.755D-03 1.403D-03 5.037D-04 7.503D+00 2.765D-03 1.4 0 8D-0 3 5.058D-04 **** **** DC TRANSFER CURVES TEMPERATURE DEG C 27.000 = ***************i***t*lttAttttttttt4jtttttt4tltttjkjtjktjttt ************* LEGEND: *: +: = : I(VID5) I(VID4) I(VID3) $: KVID2) 0: I(VID1) VDS KVID5) oc r\T\ o n A H.zdUD- i,*4--<;n^ 0.000D+00 1.368D-48 X 1.83 0D-01 1.098D+00 2.597D-04 0$=+* 5.058D-04 0$ 7.382D-04 0$ 9.570D-04 0$ 1.162D-03 0$ 1.353D-03 0$ 1.281D 00 1.464D+00 1.647D+00 1.531D-03 1.694D-03 1.844D-03 1.830D+00 2.013D+00 1.979D-03 2.100D-03 2.196D+00 2.206D-03 2.379D+00 2.562D+00 2.745D + 00 2.298D-03 2.928D+00 3.111D + 00 3.294D+00 3.477D+00 3.660D+00 3.843D+00 2.486D-03 3.660D-01 5.490D-01 7.320D-01 9.150D-01 + 4.026D+00 4.209D+00 4.392D+00 4.575D+00 4.758D+00 4.941D+00 5.124D+00 5.307D + 00 5.490D + 00 = 2.376D-03 2.438D-03 2.518D-03 2.535D-03 2.545D-03 2.554D-03 2.564D-03 2.573D-03 2.583D-03 2.593D-03 2.602D-03 2.612D-03 2.622D-03 2.632D-03 2.642D-03 2.652D-03 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 5.673D+00 5.856D+00 6.039D+00 6.222D+00 6.405D+00 2.682D-03 6.588D+00 6.771D + 00 6.954D+00 7.137D+00 7.320D+00 7.503D+00 0$ 2.723D-03 0$ 2.734D-03 0$ 2.744D-03 0$ 2.755D-03 0$ 2.765D-03 0$ 2.662D-03 2.672D-03 2.692D-03 2.702D-03 2.713D-03 A *7 m o i c c f\r\ no l.bbOD U4 l)J Z.4/3U o i n j.jyj n -j uj * + *. + * + = * + = * = .+ = . * + . + = * + = . * + = = + = + = + * * . * * = + . . = + . *. . *r = + = + = * , + * , + = + * = + = + = , * * . * = + * = + * = , * + = + = + = , * * * + * + = = + * = + * + * , = , * = + = + * = + * = , = , = * + + * + A * = + = + * + * = t . ******** *******02/09/86 IDS **** VS VDS SPICE FOR THE OPERATING POINT 2G.5 (10AUG81) ********16:07:10***** EK NMOS T2 6 TRANSISTORS INFORMATION TEMPERATURE = 27.000 DEC C ************************ *********************************************** **** MOSFETS Ml M2 M4 M3 M5 MODEL T26 T26 T26 T2 6 ID 0.00D+00 0.0OD+00 1.000 1.19D-22 9.16D-2 4 3.16D-33 3.000 4.000 VGS 0.000 VDS GM 0.000 0.000 0.508 0.000 0.00D+0 0 GDS 0.00D+00 0.000 0.508 0.442 0.00D+0 0 2.08D-04 GMB 0.00D+0 0 2.44D-13 2.44D-13 T26 CBS 2.44D-13 CGSOVL 2.33D-14 2.44D-13 2.3 3D-14 CGDOVL 2.33D-14 2.33D-14 2.000 0.000 0.000 0.508 1.366 0. 00D + 00 6.31D-04 0.0 0D+0 0 2.44D-13 2.44D-13 2.33D-14 2. 33D-14 CGBOVL 0.00D+00 0.00D+00 0.00D+00 0.00D+00 0.00D+00 CCS 0.00D+00 1.09D-13 1.09D-13 1.09D-13 CGD 0.00D+00 1.09D-13 1.09D-13 1.09D-13 1.09D-13 1.09D-13 CCB 2.09D-13 0. 00D+0 0 0.00D+00 0.00D+00 0.00D+00 VBS VTH VDSAT CBD JOB 0.000 0.00D+00 CONCLUDED TOTAL JOB TIME 0.19 0.000 0.000 0.000 0.508 0.000 0.508 2.307 0. 00D + 00 1.05D-03 0. 00D+00 2.44D-13 2.44D-13 2.33D-14 3.256 0. 00D+00 1.4 8D-03 0.00D+00 2.44D-13 2.44D-13 2.33D-14 2.33D-14 2.33D-14 * . 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CD i n ro a M co <*H OJ HI HI Z Z M M JJ ******** *******02/09/86 IDS **** VS INPUT VDS SPICE FOR THE EK 2G.5 NMOS (10AUG81) ********i6:07 :17***** T280 TRANSISTORS LISTING TEMPERATURE = 27.000 DEG C 0****O*HU*****Ht***HH*****************O********lr**********H*t* * C S BELL * 0 9 20 VSUB VDS 0 DC 0 VGS1 1 0 DC 0 VGS2 2 0 DC 1 3 0 DC 2 0 DC VGS5 5 0 DC Ml 11 1 0 9 3 4 VGS3 4 VGS4 T280 L=80U W=80U NRS=.l NRD=.l AD=1280P AS=1280P PD=192U AS=1280P PD=192U NRD=.l AD=1280P AS=1280P PD=192U +PS=192U M2 12 2 0 9 T280 L=80U W=80U NRS=.l NRD=.l 0 9 T2 80 L = 80U W=80U NRS = 0 9 T280 L=80U W=80U NRS=.l NRD=. 1 AD=1280P AS=1280P PD=192U 0 9 T280 L = 80U W=80U NRS = NRD=. 1 AD=1280P AS=1280P PD=192U AD=1280P +PS=192U M3 13 3 .l +PS=192U M4 14 4 +PS=192U M5 15 5 .l +PS=192U VID1 20 VID2 20 VID3 20 11 12 13 0 0 20 20 14 0 15 0 VID4 VID5 .MODEL 0 UO=680 TPG=1 LAMBDA=. 02255 NMOS T26 TOX=.0711U 1E-10 CGSO =2 +CGDO=2.91E-10 CJ=1.77E-4 MJ=.5 CJSW=8. 85E-11 MJSW = NSS = 4.758E11 GAMMA = +LD=.2U LEVEL=2 VTO = +XJ=.5U NSUB = 4.008E14 PB = RSH=48.92 .871 .9 .3 .2232 .53 .MODEL NSUB +XJ=.5U = 4.008E14 +LD=.2U VTO = LEVEL=2 PB = RSH=48.92 GAMMA = .604 .871 CGSO TOX=.0711U =2 .91E-10 CJSW=8. 85E-11 MJSW = MJ=.5 CJ=1.77E-4 +CCDO=2.91E-10 UO=610 TPG=1 LAMBDA=. 00155 NMOS T280 .2509 .3 NSS = 4.983E11 + MODEL T46 +XJ=1U NSUB = 3.695E15 +LD .6U . 03181 RSH=285.6 2 VTO=-1.070 LEVEL = T480 PMOS UO=210 TPG=-1 PB = .719 GAMMA = .6645 TOX=.0711U CGSO = 4. 85E-10 CJSW=.958E-11 MJ=.5 CJ=.958E-5 +CCDO=4.85E-10 = LAMBDA = PMOS MJSW=. 3 NSS=1.291E11 + .MODEL +XJ=1U NSUB = +CCDO=4.85E-12 +LD=.6U .WIDTH LEVEL=2 OUT = LAMBDA 3.695E15 = . 00184 RSH=285.6 CJ=.958E-5 VTO=-1.009 MJ=.5 UO=210 PB = .719 TPG=-1 CJSW=.958E-11 CAMMA = .7736 TOX=.0711U CGSO=4. 85E-12 MJSW=.3 NSS=1.478E11 80 .OP .DC VDS 0 7.5. 183 DC KVID5) KVID4) .PLOT I(VID3) ?(0,192. 5E-06) .PRINT .END DC ICVID5) I(VID4>- KVID3) I(VID2) I(VID1) *******02/09/86 IDS **** VS ******** SPICE VDS FOR THE EK 2G.5 (10AUG81) ********16: 07: 17***** NMOS T280 TRANSISTORS MOSFET MODEL PARAMETERS TEMPERATURE = 27.000 DEC C *********************************************************************** TYPE T26 T280 T46 T480 NMOS NMOS PMOS PMOS 2.000 LEVEL 2.000 2.000 VTO 0.530 0.604 -1.070 -1.009 3.30D-05 2.96D-05 1.02D-05 1.02D-05 GAMMA 0.223 0.251 0.665 0.774 PHI 0.529 0.529 0.644 0.644 2.25D-02 1.55D-03 3.18D-02 1.84D-03 0.871 0.871 0.719 0.719 CGSO 2.91D-10 2.91D-10 4.8 5D-10 4.8 5D-12 CGDO 2.91D-10 2.91D-10 4.85D-10 4.85D-12 48.920 48.920 285.600 285.600 CJ 1.77D-04 1.77D-04 9.58D-06 9.58D-06 Mj 0.500 0.500 0.500 0.500 CJSW 8.85D-11 8.85D-11 9.58D-12 9.58D-12 MJSW 0.300 0.300 0.300 0.300 TOX 7.11D-08 7.11D-08 7.11D-08 7.11D-08 NSUB 4.01D+14 4.01D+14 3.69D+15 3.69D + 15 NSS 4.76D+11 4.98D+H 1.29D+11 1.48D+11 1.000 1.000 -1.000 -1.000 TPG XJ 5.00D-07 5.00D-07 1.00D-06 1.00D-06 2.00D-07 2.00D-07 6.00D-07 6.00D-07 LD U0 680.000 610.000 210.000 210.000 KP LAMBDA PB RSH 2.000 IDS **** VS VDS FOR THE.EK NMOS T2 8U TRANSISTORS DC TRANSFER CURVES TEMPERATURE 27.000 DEC C = ****************************** ***************************************** LEGEND: *: + : = : $: 0: I(VID5) KVID4) I(VID3) I(VID2) I(VID1) VDS I (VID5) i,*4--s,ni' A r> i 4 4.81ju-ud 0.000D+00 1.830D-01 3.660D-01 5.490D-01 7.320D-01 9.150D-01 1.098D+00 1.281D+00 1.464D+00 1.647D+00 1.830D+00 2.013D+00 2.196D+00 2.379D+00 2.562D+00 2.745D + 00 2.928D+00 3.111D+00 3.294D+00 3.477D+00 -2.826D-16 9.080D-05 +* + = 0$ 1.472D-04 0$ 1.510D-04 0$ 1.536D-04 0$ 1.553D-04 0$ 1.558D-04 0$ 1.559D-04 0$ 1.559D-04 0$ 1.560D-04 4.02 6D+00 1. 561D-04 4.209D+00 4.392D+00 4.575D + 00 4.758D+00 1.561D-04 * = 1.295D-04 1.424D-04 -+ . = + . = + = + = + = + * = + * = + * = + * = + * = + * + * = + * = + * = + * 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ = 6.771D+00 6.954D+00 7.137D + 00 7.320D+00 7.503D+00 1.567D-04 1.568D-04 1.568D-04 1.568D-04 1.569D-04 0$ 1.569D-04 0$ 1.570D-04 0$ * + 1.564D-04 1.566D-04 * . = = 1.567D-04 * . + 1.564D-04 1.565D-04 * . + = 1.563D-04 1.566D-04 * . + = 5.124D+00 5.307D + 00 5.490D+00 5.673D + 00 5. 856D+00 6.039D + 00 6.222D+00 6.405D + 00 6. 588D+00 1.565D-04 . + = 4.941D + 00 1.562D-04 1.563D-04 * + 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 1. 562D-04 * + = 0$ 1.021D-04 0$ 1.123D-04 0$ 1.214D-04 0$ 0$ 1.365D-04 0$ * + = = 1.560D-04 i.tmiv-vi .szdv-ud X 1.792D-05 X = 3.471D-05 0$ 5.039D-05 0$ 6.495D-05 0$ 7.842D-05 0$ 3.660D+00 3.843D+00 y = , , * * * * + * + * = + * . + * . + + * = , = = * = + * = + * = = , + * + * = + * = + * . = = = m . + * + * + * + * f\ ** 1.9^ *******02/09/86 IDS **** VS ******- VDS SPICE FOR THE OPERATING POINT (10ADG81) #5 EK NMOS ********16.07.17^*** T280 TRANSISTORS INFORMATION *********************** ****** **** 2G TEMPERATURE = ****************************************** MOSFETS Ml M2 M3 M4 M5 MODEL T280 T280 T280 T280 T280 ID 0.00D+00 1.000 0.000 0.000 2.4 4D-2 6 1.96D-25 5.41D-25 4.000 0.000 0.000 0.602 0.602 VDS AT 0.000 0.346 0.00D+00 1.18D-05 0.00D+00 2.44D-13 2.44D-13 2.3 3D-14 2.33D-14 0.00D+00 1.55D-12 1.55D-12 0.00D+00 0.000 0.602 2.170 0.00D + 00 7.14D-05 0.000 VTH 2.000 0.000 0.000 0.602 1.247 0.00D+00 4.16D-05 0.00D+0 0 2.44D-13 2.44D-13 2.3 3D-14 3.000 VBS 0.00D+00 0.000 0.000 0.000 VGS VDS GM 0.00D+00 GDS GMB 0.00D+00 CBD 0. 00D+00 2.44D-13 CBS CGSOVL CGDOVL 2.44D-13 2.33D-14 CCBOVL 0.00D+00 CGS 0.00D+00 CGD 0.00D+00 CGB 3.09D-12 2.33D-14 JOB TIME 0.00D+00 2.33D-14 2.44D-13 2.44D-13 2.33D-14 2.3 3D-14 0.00D 0.602 3.105 O.OOD+00 1.01D-04 0.00D+00 2.44D-13 2.44D-13 2.33D-14 2.33D-14 00 0.00D + 00 1.55D-12 1.55D-12 1.55D-12 1.5 5D-12 1.5 5D-12 1.55D-12 0.00D+0 0 0.00D+00 0.00D + 00 + JOB CONCLUDED TOTAL 27.000 DEC C 0.19 0.00D+00 ITl 3"' T< ro c IU c 0 -4 .. rs Vl o o L OJ p Z> -H w Vl co in o 03 i .ID + CM * UJ p i 01 ID 1 E ro 0.1 L U' ai ro e E ro CD fc 0 L X . ID O L ro a CO L (S * f X x L <4- a> X JZ p o . o 1 1 .4 x in CL Z a. 3 01 X <4- IS roro-^ro^ro OJ ID' * X ID ID CM -4OISG0 * IT' "- ID' x oj oj oj oj oj cm cm ro ro cm I I I I I 1 I I I 1 10 Z; "D 0 CO is oj in id x in in cm ro cm rjOHrHrtOo^rj^H u -3- O -f CM X -f ID CO X O id is co ro co is is. cd ro ro ro ii PX*'.'4.'~4'.<~4.-4-' -1 CM 3 10 Z> I I I I I ! I I 1 ! d ID d 1 X OJ X ro in t ID' o O .-4 ro x cm ro ro ro ro ro ro cm cm cm :> 3 i i i i i i j i i i v. O- X ro V 10 IS is id o ID' o O OI CO o (-1 d is. in m ro o *<r in o co o o . .f\J O . O 1 c 3 o in in IT' ELI I id r-. ro o x rs ro *r ix> ro. x Tf.jiHvDNOfrnijia:' is. id ro cd o ro ro ro ro ro ro ro ro id. uj ro in o -r *4--4-m^--'4--<i--i--j--4-m I I I I i I i I -<*- I o o I X -> 3 O CC' ocdxxcmocoxxx colors oo-^^rooo.' roroiso oo-o . . TO ID O O i^^ ID ID ID ID OJ ID ID ID ID |D I I I I I I I I I I Z> 0*1 I 01 E c: cn c ro x D ro^îDcnrMOir'rsT)- ^ -1 x I tn e ro co m in in ro co -* oj rs 0010-4 ~* -^ id * . -co . . in ID CO eo <w- S^ E 3 cn ->* ro X' it. oo--4. o p Z> 0 id -* UXCOCOCOCOCOCOCDCOCOrs o x ro x ' o o -* ** -4 > oj -h '-' cn o co id < m id o o o -" oj ro ro ro cm cm 00 ro cm oj I I I I I I I I I I z> > i in id id id is in IT' o in ro ro -< ro-*o'.-i^'Ooro o x is o IT' ro is ro rs rs ^-ec f|T^4^HÎ-H^H^H^H^Hr-.0 I I I I I I I I I I -cm o OJ o I -hoe^ cm x co o ' o o m I O O I r4 In id cc r o 0 tn-o > p > L 01 ro ccro.ro-> L41 iDiDrD-<-,ii-mininxx 01 TJ CM TO CM CM 00 CM cm cm cm cm <4- 0 <TJ o id in is x * id in is. x * 3T_J (MCMCMCMCMCMOJCMCMCM > o o o o > o o O in > o in N o > > > o o o o is ?. 0 .. h 0 1 CU 3t sz cu CJ a i , o m 1 C r-1 X) o (DP X) o c q a CO C 0 O 03 L P -H P 4J P 0 > CO CO to > _J D cH OI C0 -rt 11 in ,. H f x: x: a cj u -p a l 0 4J i I c ro +J rl L CD > > o o o o o o o o i1 , rH H o o o o 11 1 CO 0 x: o o o o a a a oj +> p m s 10 > co to CO c to z o > > > u P > > > > o o o o o o o o o o o o to o o o .. rt a I o Of CQ x: 3: a m i i o o o in oi i i > > o o o o o o o o in co sz cu CJ o I x: c 0 cj o i i c .. I o > > o o o o .. + c - XI (OP o l c 0 ^ C. CD 0 > a a o o rl 4J _J CO CO CO 4J 4J X) 0 p c. 0 a p n ^ c CO 2 o > > a a O 0 c. a + p p 0 > co to co *i > a X * X(D XCD X OJ Oo CDf too- Q_x o I UJ HI CO CO* ^T 01 CD t*CD Hi 1- CW <f- oo oo CDO LT -HO CD CD CD I X X X X X X I trix OHIJ Cfl^' txcri OCD o > O O-H O CD TJ OH! O m m > > > o o o o o o O O fs. o o o > > > ... ?i .. rt 0 a i 0 OI o x: z O 0 CO . . . w V x: w cj CJ c x> 0 p o 0 c a a H C 0 O 0 C Cfl 4-1 p JJ JJ 0 > co to to _J -n > o o o o i 1 t-l > T4 CO i > o o o o o o o o o o o o o o o 1 + p c a a X 0 o 0 L 2 p + p 0 > CO to to > 4H -h a 0 c rH X) UJ n sz 1 l r 0 p o c to CO o > > a ******** *******02/09/86 IDS. VS **** VDS INPUT SPICE FOR THE EK 2G.5 (10AUG81) TEMPERATURE **************************** C S 11***** PMOS T46 TRANSISTORS LISTINC * ********17: 23: = 27.000 DEC C ******************************************* BELL * 0 9 20 VSUB VDS 4.7 DC 0 VGS1 1 0 DC VGS2 2 0 DC -3 VGS3 3 4 5 0 DC -4 VGS4 VGS5 Ml 11 -2 0 DC -5 0 DC -6 1 0 9 T46 L=6U W=80U NRS=.l NRD=.l AD=1280P AS=1280P PD=192U NRD=.l AD=1280P +PS=192U M2 12 2 0 9 T46 L=6U W=80U NRS = AS=1280P PD=192U 0 9 T46 L=6U W=80U NRS=.l NRD=.l AD=1280P AS=1280P PD=192U 0 9 T46 L=6U W=80U NRS=.l NRD=.l AD=1280P AS=1280P PD=192U 0 9 T46 L=6U W=80U NRS=.l NRD=.l AD=1280P AS=1280P PD=192U .l +PS=192U M3 13 3 +PS=192U M4 14 4 +PS=192U M5 15 5 +PS=192U VID1 20 11 0 VID2 20 12 0 0 0 0 VID3 20 13 VID4 20 14 VID5 20 15 .MODEL +XJ=.5U +CCDO=2.91E-10 +LD=.2U .MODEL +XJ=.5U VTO=.53 NSUB = 01750 UO=610 TPG=1 TOX=.0711U CGSO=2.91E-10 PB = MJ=.5 4.008E14 . 00155 RSH=48.92 MJ=.5 CJ=1.77E-4 GAMMA = VTO=.604 LEVEL=2 .871 CJSW=8. 85E-11 MJSW=.3 NSS=4.758E11 CAMMA=.2232 LAMBDA = NMOS T280 . RSH=48.92 CJ=1.77E-4 LEVEL=2 +CCDO=2.91E-10 +LD=.2U LAMBDA = T2 6 NMOS NSUB = 4.008E14 PB = CGSO=2.91E-10 .871 CJSW=8 .2509 TOX=. 0711U TPG=1 UO=610 . 85E-11 NSS = MJSW = .3 4.983E11 + .MODEL +XJ=.8U T46 PMOS NSUB = 3.700E16 +CGDO=4.85E-10 +LD = LEVEL=2 .6U LAMBDA = . 02750 00=178 TPG=-1 TOX=.0711U CGSO = 4 85E-10 PB = RSH=285.6 MJ=.5 CJ=.958E-5 VTO=-1.070 . .719 CJSW=.958E-11 GAMMA = .6645 MJSW=. 3 NSS=1.291E11 + .MODEL PMOS T480 LAMBDA = . 00155 RSH=285.6 UO=178 PB = +XJ=.8U NSUB = 3.700E16 = +CGDO=4.85E-10 CJ=.958E-5 MJ=.5 CJSW LEVEL=2 +LD=.6U OUT .WIDTH = VTO=-1.009 .719 TPC=-1 CGSO = .958E-11 CAMMA=.7736 TOX=.0711U 4. 85E-10 MJSW=.3 NSS=1.478E11 80 .OP .DC VDS .PLOT + 0 DC -7.5 -.183 I(VID5) KVID4) (0,-1.43E-3) .PRINT .END DC KVID5) I(VID4) I(VID2) KVID3) I (VID3 ) I (VID2) I (VID1) ******** ,******02/09/86 IDS VS VDS FOR THE EK MOSFET MODEL TYPE spiCE 2Q5 PMOS aoADG8ir;;****^n7:23:11^^ T4 6 TRANSISTORS PARAMETERS TEMPERATURE T26 T280 T46 T480 NMOS NMOS PMOS PMOS LEVEL 2.000 2.000 VTO 0.530 0.604 -1.070 -1.009 2.96D-05 2.96D-05 8.65D-06 8.65D-06 0.223 0.251 0.665 0.774 0.529 0.529 0.763 0.763 1.75D-02 1.55D-03 2.75D-02 1.55D-03 0.871 0.871 0.719 0.719 CGSO 2.91D-10 2.91D-10 4.85D-10 4.85D-10 CGDO 2.91D-10 2.91D-10 4.85D-10 4.85D-10 48.920 48.920 285.600 285.600 CJ 1.77D-04 1.77D-04 9.58D-06 9.58D-06 MJ 0.500 0.500 0.500 0.500 CJSW 8.85D-11 8.85D-11 9.58D-12 9.58D-12 MJSW 0.300 0.300 0.300 0.300 TOX 7.11D-08 7.11D-08 7.11D-08 7.11D-08 NSUB 4.01D 14 4.01D+14 3.70D+16 3.70D+16 NSS 4.76D+11 4.98D+11 1.29D+11 1.48D+11 TPG 1.000 1.000 XJ 5.00D-07 5.00D-07 8.00D-07 8.00D-07 LD 2.00D-07 2.00D-07 6.00D-07 6.00D-07 UO 610.000 610.000 178.000 178.000 KP GAMMA ,PHI LAMBDA PB RSH + 2.000 -1.000 2.000 -1.000 = 27.000 DEC C ******** *******02/09/86 IDS **** VS VDS SPICE FOR THE EK 2G.5 (10AUG81) PMOS T46 TEMPERATURE ***************************************** I (VID5) I (VID4) I 27.000 = (VID3) I (VID2) 0.000D+00 -6.517D-12 -6.517D-12 -6.517D-12 -6 268D-12 -1.019D-04 -7.682D-05 -5.13 7D-05 -2 551D-0 5 !-3.660D-01 -1.996D-04 -1.492D-0 -5.490D-01 -2.931D-04 -2.170D-04 -9.796D-05 -4 -1.397D-04 -6 802D-04 -1.765D-04 -7 589D-05 10 7D-05 096D-05 -7.320D-01 -3.823D-04 -2. -9.150D-01 -4.672D-04 -3.38 8D-04 -2.083D-04 7.54 8D-05 -1.098D+00 -5.477D-04 -3.927D-04 -2.350D-04 7.614D-05 -1.281D+00 -6.237D-04 -4.417D-04 -2.565D-04 7.664D-05 -1.464D+00 -6.952D-04 -4.85 8D-0 4 7.715D-05 -1.647D+00 -7.621D-04 -5.250D-04 -2.837D-04 7.765D-05 -1.830D+00 -8.243D-04 -5.591D-04 -2.892D-04 7.817D-05 -2.013D+00 -8. 818D-04 -5.881D-04 -2.910D-04 7.868D-05 -2.196D+00 -9.344D-04 -6.119D-04 -2.9 2 8D-0 4 7.921D-05 -2.379D+00 9.822D-04 -6.304D-04 2.945D-04 7.973D-05 -2.562D+00 -1.025D-03 -6.435D-04 -2.9 6 3D-0 4 8.026D-05 5D+00 -1.063D-03 -6.511D-04 2.981D-04 8.079D-05 0D-04 -2.999D-04 8.133D-05 -2.74 -2 . 9 2 8D +0 0 -1. 095D-03 -6.55 8D-04 -2.72 -3.111D+00 -1.122D-03 -6.588D-04 -3.017D-04 8.187D-05 -3.294D+00 -1.144D-03 -6.627D-04 -3.036D-04 8.242D-05 -3.477D+00 -1.161D-03 -6.666D-04 3.054D-04 -3.660D+00 -1.172D-03 -6.706D-04 -3.073D-04 -3.843D+00 1.179D-03 -6.74 6D-04 -3.092D-04 -4.026D+00 -1.186D-03 -6.786D-04 -4.209D+00 1.193D-03 -6.82 3.131D-04 8.523D-05 0 -1.200D-03 -6.868D-04 -3.150D-04 8.581D-05 -4.392D+0 7D-04 -3.111D-0 4 8.2 9 7D-05 8.353D-05 8.409D-05 8.466D-05 -4.575D+00 1.207D-03 6.910D-04 3.170D-04 -4.758D+00 -1.214D-03 -6.952D-04 3.190D-04 8.639D-05 8.698D-05 -4.941D+00 -1.221D-03 6.995D-04 3, .210D-04 8.758D-05 -7.038D-04 3. .230D-04 -5.124D+00 -1.229D-03 1.23 -7.081D-04 -3, .251D-04 -5.307D+00 6D-03 -5.490D+00 -1.244D-03 -7.125D-04 3, .272D-04 8.940D-05 -5.673D+00 -1.251D-03 -7.170D-04 3.293D-04 9.002D-05 -5.856D+00 -1.259D-03 -7.215D-04 -3.314D-04 -6.039D+00 1.267D-03 -7.260D-04 -3.33 -7.306D-04 3.358D-04 .192D-05 7.352D-04 3.380D-04 .256D-05 7.399D-04 3.402D-04 .322D-05 -7.447D-04 3.424D-04 .388D-05 -7.495D-04 -3.447D-04 .454D-05 7.544D-04 3.470D-04 .522D-05 7.593D-04 -3.493D-04 7.643D-04 3.517D-04 -6.222D+00 -6.405D+00 -6.588D+00 -1.275D-03 1.282D-03 1.291D-03 -6.771D+00 1.299D-03 00 1.307D-03 -6.954D + -7.137D+00 1.315D-03 -7.320D+00 1.324D-03 -7.503D+00 1.332D-03 DEC C ****************************** -1.830D-01 4 3:11***** TRANSISTORS DC TRANSFER CURVES VDS ********17:2 6D-04 8.818D-05 8.879D-05 .064D-05 .12 8D-05 .590D-05 -9.659D-05 IDS **** DC VS VDS FOR THE EK PMOS T4 6 TRANSISTORS TRANSFER CURVES TEMPERATURE 27.000 DEC C = ***************************** ****************************************** LEGEND: *: +: = : I(VID5) I(VID4) I(VID3) $: KVID2) 0: I(VID1) VDS I(VID5) (*+=$0) 1.430D-03 0.000D+00 -6.517D-12 -1.830D-01 -1.019D-04 -3.660D-01 -1.996D-04 -5.490D-01 -2.931D-04 -7.320D-01 -3.823D-04 -9.150D-01 -4.672D-04 -1.098D+00 -5.477D-04 -1.281D+00 -7.621D-04 -1.830D+00 -8.243D-04 -6.952D-04 -2.013D+00 -8.818D-04 -2.196D+00 -9.344D-04 -2.379D+00 -9.822D-04 -2.562D+00 -1.025D-03 -2.745D+00 -1.063D-03 -2.928D+00 -1.095D-03 -3.111D+00 -1.122D-03 -3.294D+00 -1.144D-03 -3.660D+00 -1.179D-03 -1.186D-03 -4.209D+00 -1.193D-03 -1.200D-03 -4.575D+00 -1.207D-03 -4.758D+00 -1.214D-03 I-5.856D+00 -1.259D-03 * + * = . + * s + * $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ + * + * * = . + . + . = = + * + * * * * * * . = + , + . , + . , + . + . * = = = = + + * * + * + . = + + + * + * + * + * + * -6.039D+00 -1.267D-03 -6.222D+00 -1.275D-03 -6.405D+00 -1.282D-03 -6.588D+00 -1.291D-03 -7.503D+00 + m -1.244D-03 -1.251D-03 -7.320D+00 * * -5.673D+00 -7.137D+00 + ^ * -1.229D-03 -6.954D+00 $ $ $ $ $ $ = = .+ * = = -1.221D-03 -1.236D-03 00 * + + + . * -5.307D+00 + * m * -5.124D+00 -6.771D * * -4.392D+00 -5.490D+00 ^ * -1.172D-03 -4.026D+00 0.00( -3.575D-04 # -1.161D-03 -3.843D+00 -4.941D+00 -7.150D-04 -6.237D-04 1-1.464D+00 '-1.64 7D+00 -3.477D+00 -1.073D-03 + * + * + * + * + * + . . . . -1.299D-03 . -1.307D-03 * + * + . $ * + . $ . -1.315D-03 -1.324D-03 -1.332D-03 $ $ $ $ $ $ $ $ $ $ ****** *02/09/8 6 IDS **** VS ******** VDS - SPICE FOR THE OPERATING POINT EK 2Gi5 (10AUG81) ******* *17:23:11***** PMOS T4 6 TRANSISTORS INFORMATION TEMPERATURE = 2 7.000 DEG C *********************************************************************** ***'* MOSFETS Ml MODEL ID M2 T46 T46 M4 M3 T4 6 T46 M5 T46 -1.82D-12 -1.82D-12 -1.82D-12 -1.82D-12 -1.82D-12 VGS -2.000 -3.000 -4.000 -5.000 -6.000 VDS 0.000 4.700 0.000 0.000 0.000 0.000 4.700 4.700 4.700 4.700 -1.927 VBS VTH -1.927 -1.927 -1.927 -1.927 VDSAT -0.064 -0.953 -1.848 -2.748 -3.653 GM 0.00D+00 0.00D+0 0 O.O0D+00 0. OOD+0 0 0.00D+00 GDS 1.05D-05 1.5 5D-04 2.99D-04 4.43D-04 5.87D-04 GMB 0.00D+00 0. O0D+0 0 0.00D+0 0 0.00D+00 0.00D+00 CBD 5.47D-15 5.47D-15 5.47D-15 5.4 7D-15 5.47D-15 CBS CGSOVL 5.47D-15 3.8 8D-14 5.47D-15 3.8 8D-14 5.47D-15 5.47D-15 5.4 7D-15 3.8 8D-14 3.88D-14 3.8 8D-14 3.88D-14 0.0 0D+0 0 CGDOVL 3.88D-14 3.88D-14 3.88D-14 3.88D-14 CGBOVL O.OOD+00 0.00D+00 0.00D+00 O.OOD+00 1.18D-13 1.15D-13 6.42D-14 4.8 7D-14 0.00D+0 0 5.80D-14 1.13D-13 0.00D+00 O.OOD+0 0 CGS 1.24D-13 1.22D-13 CGD 3.3 0D-15 3.3 3D-14 CCB 0.00D+00 0.00D+00 JOB CONCLUDED TOTAL JOB TIME 0.20 cn u- in 4 . w ro -* ID V. o L 3"' .0 ro c ro CJ ro U 3> ^4 HI VI L 01 P -4 VI L 41- ro E e ro U) L fc U L X x ID is is o <4- l o i . ID OJ X p o . is ID E ro i. in Q. 0> 01 -" 0' 1 Ui co in o CD -4 ~H ID + CM * UJ .. o 0 o p L X -.4 n W CL Z Q. 3 4-1 0 OJ mrors\rs.*rm^--4^H X is X X "* in in in t * in x x in II ID X OJ OJ OJ CM ro OJ OJ cm oi CM Z> 3 I I I I I I I 1 I I Vl x id is 4e x in ^r o id i > i CM ID' ID 00 CM CM CO ->i- in Oi X CM Oi CM CM CM CM TO OJ OJ TO => 3 I I I 1 I i I 1 I 1 Vl is. ro' ID ID O 'T m X IT' O o o . . CM 00 1 o o id ro in ID. cm in x o . . o o CM CM I o o oj o ro ir< oj rs ro ro> ro ro ro ro rs jJriri^Wrt^rfHr4H ^ idi ro co co ro cc> ro II z> 3 Vl . 1 1 I I I 1 I I I I i id co co cn in co ro ro in in, > in co ro> id cr> -t ' ID' i o o o cm ro o oj cc .-i -i IT' ro ei >a- i m in in in in in in in i i i i i i i i in' i .TO o o cm in in id o o 1-4 . o tj- Tf ro ro -r id o . o o . . > o ro o in o i no o co x oj o o ro * i- -4- * xcocororscocorsxo o CO 01 c c ro X 0 I a. ....... 4J- Z> C*J ID ID ID ID ID ID ID ID ID I I I I I I I I I 's CMCD<-4|s-^rDCDCMC0 I x in o co ro ro < o -ID ID o I o --< e cn .-'Vi'-'CDmxroooinxcM XXID^ isxois . . roxrocDcocDCororococDCD ro x e ......... o ro -id o o eo X E 3 s-- cn x o ro n- ro ^ ro oj oj o i -> fD in in *- ro O CM O id r-- is. ^ 4f roi ~ > o cc' id ro oj oj id *-i ro oj oj oj ro oj ro oj cm ro i i i i i i i i i i +> r> 3, is. cc x id ro -i tT' in' 44- " i i rs \n -r rs m. cn id ro d V in rr ro -^ x in in in in * uj -r i i i i i i i o ^ cr. id id in oj o o ro o cm o oj o CM is x ^ -* o rs j m oj id. ro ^' iS ON J, > L > P 0' ro CC LO Q ^ P S CT'-D r 0 L4J oi re <4- n mo 3 _1 m in in X X cm ro ro cm ro cm ro ro ro ro ID ID IDi t 4J- , id in is x <* in is. x CM CM CM CM ro OJ ro OJ OJ CM idi * a. > > > > > > o o O o o o o in O fs in o o o o o o o o o o o o o is OJ CO 1 I T4 i i 0 .. .-1 O M ro 0 sz s CJ tn a p 0 c a H tO c 0 o c. a H p 4J o > CO CO -1 > r 01 u CO i c. in P CO 4J4J "<T sz sz , r-l a o p o a r_ a a H (DOE C. CD P P P ID > to CO to > > o o o o 1 01 , 1 S3 0 > o o o o 0 c 4V 1 1 c m -u 7Z 0) Cffi7. o > > u > o o O O a i 0 oi v sz x .. Ô ID O I c a 0 * C C9 m > > > o o o o O CD O o i > o o o o > > o o o o o o o o * t-I I I CO x: cu CJ o t ,. m p tf Jjj _i co co to P .p > o o o o * i 0 c a a c 0 o o > o o o o XI 0 41 p c a a 0 O 0 t_ Q P 4-> 0 > CO CO CO +J > in sz sz 0 CJ CJ P I 1 c a p m 3: c CO z o > > CJ CD I ! H ;0 ' ! a! hi G <j^H i CCICD CD i 1 CD vH OJ HI HI Z M _J H J > > > o o o o o o o o is o o o > O o o O ... H a i CO i > > O O o o o o O ri CO i ri > o o o o o o o o trl -H > . OJ a .. IV OJ x: 5 T x: 01 CJ O 1 O a 0 CJ > .. 01 1 ..t p r-t n 0 H a p o c c a X) a o. o o t_ LO 1+JU4J 0 > -1 > CO CO CO p 0 c. a a to O OJ C 2 p p > CO CO CO > +J 0 t4J 3: -p 1 I tn c tn m o > > U 4-> a m m OJ o Oj o i I 1 t_ HI hi! CD 01 î 4J in Nl C 1 -H m ^r! > > i i j 4-> . i a o o! Q) o o O + + f_ HI UJ OJ OJ in "O 4-> 00 ^r X o L_ <H -H OJ o s H o X 1 i N o o a o o < + + tx HI nil CD n CO \ o v-H CD in in i | ! > j cn 0)1 o o1 i Q HI 1 1 UJ! < 1-. m' <!rs tXiO, CD 1 H cn; j 1 CM! HI UJ Z z M M _J _J a M CO ******** >02/09/86 IDS ********_ SPICE- 2G. 5 VS INPUT VDS FOR THE EK (10AUG81) - ********17: 16: 33***** PMOS T4 80 TRANSISTORS LISTINC TEMPERATURE = 27.000 DEG C *******************^^^^^^^^^^^^^^^^^^^^^^^^^^ C S BELL i * 9 0 !VDS 20 0 jVSUB 4.7 DC VCS1 1 0 DC -2 VCS2 2 0 DC -3 3 0 DC -4 VGS4 4 0 DC -5 VGS5 5 0 DC -6 Ml 11 1 0 9 T480 L=80U W=80U NRS=.l NRD=.l AD=1280P AS=1280P PD=192U VGS3 +PS=192U M2 12 2 0 9 T480 L=80U W=80U NRS=.l NRD=.l AD=1280P AS=1280P PD=192U 0 9 T480 L=80U W=80U NRS=.l NRD=.l AS=1280P PD=192U 0 9 T480 L=80U W=80U NRS=.l NRD=.l AD=1280P AS=1280P PD=192U 0 9 T480 L=80U W=80U PD=192U +PS=192U M3 13 3 AD=1280P +PS=192U ,M4 14 4 +PS=192U M5 15 5 NRS=.l NRD=.l AD=1280P AS=1280P +PS=192U VID1 20 11 0 VID2 12 0 VID3 20 20 13 0 VID4 20 14 0 VID5 2 0 15 0 T26 NMOS LAMBDA=. 01750 UO=610 TPG=1 TOX=.0711U RSH=48.92 PB = CGSO=2 +CGDO=2.91E-10 CJ=1.77E-4 MJ=.5 CJSW=8. 85E-11 MJSW=. 3 .MODEL +XJ=.5U NSUB = 4.008E14 +LD=.2U .MODEL +XJ=.5U LEVEL=2 T280 NMOS GAMMA = LEVEL=2 .91E-10 NSS=4.758E11 .2232 LAMBDA=. 00155 UO=610 TPC=1 TOX=. 0711U CGSO=2 RSH=48.92 PB = NSUB = 4.008E14 +CCDO=2.91E-10 +LD=.2U VTO=.53 .871 .871 CJ=1.77E-4 VTO = .604 MJ=.5 GAMMA = .91E-10 CJSW=8. 85E-11 MJSW = NSS=4.983E11 . 3 .2509 + .MODEL T46 PMOS LAMBDA =. 02000 UO=187 TPG=-1 TOX=. 0711U CGSO = 4. 85E-10 +XJ=.8U NSUB 3.700E16 RSH=285.6 PB = CJSW=.958E-11 MJSW=.3 +CCDO=4.85E-10 CJ=.958E-5 MJ = = .719 .5 +LD = .6U LEVEL=2 VTO=-1.070 GAMMA = .6645 NSS=1.291E11 + MODEL T480 PMOS LAMBDA = 00155 UO=178 TPG=-1 TOX=. 0711U CGSO=4. 85E-10 +XJ=.8U NSUB = 3.700E16 RSH=285.6 PB = +CCDO=4.85E-10 CJ=.958E-5 MJ=.5 CJSW=.958E-11 MJSW=. 3 . .719 +LD=.6U LEVL=2 WIDTH OUT =8 VTO=-1.009 CAMMA = .7736 NSS=1.478E11 0 OP VDS 0 -7.5 -.183 plot dc i(vid5) i(vid4) DC + i(vid3) i(vid2) (o,-6 6e-o6) .print .END dc i(vid5) i(vid4) i(vid3) i(vid2) i(vid1) *******02/09/86 ******** IDS. VS. VDS **** SPICE FOR THE EK MOSFET MODEL 2G. 5 PMOS (10AUG81) T4 80 PARAMETERS - ********17: 16: 33***** TRANSISTORS TEMPERATURE = 27.000 DEC C *********************************************************************** TYPE T26 T280 T46 T480 NMOS NMOS PMOS PMOS LEVEL 2.000 2.000 2.000 2.000 VTO 0.530 0.604 -1.070 -1.009 2.96D-05 2.96D-05 9.08D-06 8.65D-06 GAMMA 0.223 0.251 0.665 0.774 PHI 0.529 0.529 0.763 0.763 1.75D-02 1.55D-03 2.00D-02 1.55D-03 0.871 0.871 0.719 0-719 CGSO 2.91D-10 2.91D-10 4.8 5D-10 4.8 5D-10 CGDO 2.91D-10 2.91D-10 4.85D-10 4.85D-10 48.920 48.920 285.600 285.600 CJ 1.77D-04 1.77D-04 9.58D-06 9.58D-06 MJ 0.500 0.500 0.500 0.500 CJSW 8.85D-11 8.85D-11 9.58D-12 9.58D-12 MJSW 0.300 0.300 0.300 0.300 TOX 7.11D-0 8 7.11D-0 8 7.11D-0 8 7.11D-0 8 NSUB 4.01D+14 4.01D+14 3.70D+16 3.70D+16 NSS 4.76D+11 4.98D+11 1.29D+11 1.48D+11 TPG 1.000 1.000 XJ 5.00D-07 LD UO KP iLAMBDA PB RSH -1.000 -1.000 5.00D-07 8.00D-07 8.00D-07 2.00D-07 2.00D-07 6.00D-07 6.00D-07 610.000 610.000 187.000 178.000 *******02/09/86******** IDS **** VS VDS -SPICE FOR THE EK 2G.5 (10AUG81) - ********17:16:33***** PMOS T4 80 TRANSISTORS DC TRANSFER CURVES TEMPERATURE 27.000 DEC C = ******************************* **************************************** VDS I (VID5) I (VID4) I (VID3) I (VID2) 0.000D+00 -6.517D-12 -6.517D-12 -6.517D-12 -6.517D-12 0D-01 -6.030D-06 -4.429D-06 -2.82 6D-06 -1.221D-06 -3.660D-01 -1.172D-05 -8.519D-0 6 -5.312D-06 -2.102D-06 -5.490D-01 -1.708D-05 -1.227D-05 -7.459D-06 -2.642D-06 -1.83 -7.320D-01 -2.210D-05 -1.569D-05 -9.268D-06 -2.843D-06 -9.150D-01 -2.679D-05 -1.877D-05 -1.074D-05 -2.845D-06 -1.098D+00 -3.113D-05 -2.151D-05 -1.187D-05 -2.84 -1.281D+00 -3.515D-05 -2.391D-05 -1.267D-05 -2.84 -1.464D+00 -3.883D-05 -2.598D-05 6P-0 6 7D-06 8D-0 6 7D+00 -4.217D-05 -2.772D-05 312D-05 -1.32 5D-05 -1.830D+00 -4.518D-05 -2.911D-05 -1.325D-05 -2.851D-06 -2.013D+00 -4.786D-05 -3.018D-05 -1.32 6D-05 -2.852D-06 -2.196D+00 -5.020D-05 -3.090D-05 -1.326D-05 -2.853D-06 -2.379D+00 -5.221D-05 -3.129D-05 -1.327D-05 -2.854D-06 -2.562D+00 -5.388D-05 -3.137D-05 -1.327D-05 -2. -2.745D+00 -5.522D-05 -3.138D-05 -1.328D-05 -2.856D-06 -1.64 -1. -2.84 -2.850D-06 855D-06 -2.928D+00 -5.623D-05 -3.139D-05 -1.328D-05 -2.857D-06 -3.111D+00 -5.691D-05 -3.140D-05 -1.32 8D-05 -2.859D-06 -3.294D+00 -5.72 5D-0 5 -3.141D-05 -1.329D-05 -2.860D-06 -3.477D+00 -5.730D-05 -3.142D-05 -1.329D-05 -2.861D-06 5 -3.660D+00 -5.732D-05 -3.143D-05 -1.330D-0 -3.843D+00 -5.734D-05 -3.144D-05 -1.330D-05 -4.02 6D+00 -5.735D-0 5 -4.209D+00 -5.737D-05 -4.392D+00 -5.739D-0 -3.145D-05 -3.14 6D-05 -1.331D-0 5 -1.331D-05 -2.862D-0 6 -2.863D-06 -2.864D-06 -2.865D-06 5 -3.147D-05 -1.332D-05 -2.866D-06 -4.575D+00 -5.741D-05 -3.148D-05 -1.332D-05 -2.867D-06 -4.758D+00 -5.742D-05 -3.149D-05 -3.15 0D-05 -1.3 3 2D- 05 -1.333D-05 -2.868D-0 6 -2.870D-06 -4.941D+00 -5.744D-05 -5.124D+00 -5.746D-05 -5.307D+00 -5.74 8D-05 -5.490D+00 -5.750D-05 -3.153D-05 -1.334D-05 -2.873D-06 -5.673D+00 -5.751D-05 -3.154D-05 -1.335D-05 -2.874D-06 -5.856D+00 -5.753D-05 -3.155D-05 -1.335D-05 -2.875D-06 -5.755D-05 -3.156D-05 -1.335D-05 -2.876D-06 -5.757D-05 -3.157D-05 -1.336D-05 -2.877D-06 -3.158D-05 -1.336D-05 -2.878D-06 -2.879D-06 -2.880D-06 -6.039D+00 -6.222D+00 -6.405D+00 -5.75 8D-05 -3.151D-0 5 -3.152D-05 -1.333D-05 -2.871D-06 4D-05 -2.872D-06 -1.33 -6.588D+00 -5.760D-05 -3.159D-05 -1.337D-05 -6.771D+00 -5.762D-05 -3.160D-05 -1.337D-05 -3.161D-05 -1.338D-05 -2.881D-06 -1.338D-05 -2.882D-06 -6.954D+00 -5.764D-05 -7.137D+00 -5.765D-05 -3.162D-05 320D+00 -5.767D-05 -3.163D-05 -1.339D-05 -2.883D-06 -3.164D-05 -1.339D-05 -2.885D-06 -7. -7.503D+00 -5.769D-05 J-JJii **** VS VDo run IHt, fcK FMUS~T48b TRANSISTORS DC TRANSFER CURVES TEMPERATURE DEC C 27.000 = ************************************** ********************************* LEGEND: *: I(VID5) + : : I(VID4) I(VID3) $: 0: I(VID1) = KVID2) VDS (*+=$0) KVID5) 6.600D-05 0.000D+00 -6.517D-12 . -1.830D-01 -6.030D-06 . -3.660D-01 -1.172D-05 . -4.950D-05 * r -5.490D-01 -1.708D-05 . -7.320D-01 -2.210D-05 . -9.150D-01 -2.679D-05 . -1.098D+00 -3.113D-05 . * * . -1.464D+00 -3.883D-05 . * -4.217D-05 . -1.830D+00 -4.518D-05 . -2.013D+00 -4.786D-05 . -2.196D+00 -5.020D-05 . -2.379D+00 -5.221D-05 . = + = , + + . * . -2.928D+00 -5.623D-05 . = .+ * . * -5.732D-05 = . -5.734D-05 + = .+ . -5.735D-05 + -5.737D-05 . -4.392D+00 -5.739D-05 . -4.575D+00 -5.741D-05 . + -4.758D+00 -5.742D-05 . .+ + * * . -4.941D+00 -5.744D-05 . -5.124D+00 -5.746D-05 . * * -5.307D+00 -5.748D-05 . -5.490D+00 -5.750D-05 . , m * -5.856D+00 -5.753D-05 . -6.039D+00 -5.755D-05 . -5.758D-05 . -6.588D+00 -5.760D-05 . . -6.771D+00 -5.762D-05 . -6.954D+00 -5.764D-05 . . -5.767D-05 -5.769D-05 = ' ' , + + . * , * , * , + , + . * + t * . + + + . + . * -7.503D+00 + * * -7.320D+00 . + * -5.765D-05 + . -6.405D+00 -7.137D+00 = . * -5.757D-05 + + , * -6.222D+00 ..... + * -5.751D-05 = . * -5.673D+00 = .+ * -4.209D+00 = . * -4.026D+00 = . * -3.843D+00 = + * -3.660D+00 = , .+ * -5.730D-05 + . * -3.477D+00 = + + * -5.522D-05 -5.725D-05 = = . * -2.745D+00 -3.294D+00 = + * -5.691D-05 = . + * = = . + * -1.647D+00 -3.111D+00 + . * -3.515D-05 -5.388D-05 + + + . * -1.281D+00 -2.562D+00 -1.650D-05 -3.300D-05 . . m + * *******02/09/86 IDS VS ******** VDS OPERATING **** SPICE FOR THE POINT EK 2G.5 (10AUG81) ********17:16:33***** T4 80 TRANSISTORS PMOS INFORMATION TEMPERATURE = 2 7.000 DEG C *********************************************************************** **** MOSFETS Ml MODEL ID M2 T480 T480 M3 M4 T480 T480 M5 T480 -1.82D-12 -1.82D-12 -1.82D-12 -1.82D-12 -1.82D-12 VGS -2.000 -3.000 -4.000 -5.000 -6.000 VDS 0.000 0.000 0.000 0.000 0.000 VBS 4.700 4.700 4.700 4.700 4.700 VTH -2.133 -2.133 -2.133 -2.133 -2.133 -3.377 0.00D+00 0.000 -0.748 -1.618 -2.494 GM O.OOD+00 0. 00D+00 0.00D+00 O.OOD+00 GDS O.OOD 00 7.61D-06 1.64D-05 2.52D-05 3.39D-05 VDSAT + GMB 0.00D+00 0. 00D+00 0 0 0. 00D+00 0.00D+0 0 CBD 5.47D-15 5.4 7D-15 5.47D-15 5.4 7D-15 5.4 7D-15 5.47D-15 5.47D-15 5.47D-15 3.8 8D-14 3.88D-14 3.88D-14 3.88D-14 3.88D-14 3.88D-14 O.OOD+00 0.00D + 00 CBS CGSOVL CCDOVL 5.47D-15 3.88D-14 3.88D-14 5.47D-15 3.8 8D-14 3.88D-14 . 0 0D +0 CGBOVL O.OOD+00 0.0 0D+00 O.OOD+00 CCS 1.33D-12 2.01D-12 1.96D-12 1.91D-12 1.86D-12 7.4 7D-13 9.16D-13 1.0 3D-12 O.OOD+0 0 O.OOD+00 0.00D+00 CGD CCB -3.94D-30 5.34D-13 4.63D-13 O.OOD+0 0 JOB CONCLUDED TOTAL JOB TIME 0.19 APPENDIX C PARAMETER EXTRACTION CALCULATIONS appendix This Vf, and in these T, the that IBM are PC . offers effect transferred supported generated Formula One iterative to or to a software is a general is Framingham, Computer MA For 24-28 the in curve Inc., Nss, Nsub, techniquess the Formula fitting, and 100 data applied These report. One, spreadsheet spreadsheets. Products, 01701. calculate purpose solving, 123 to package, list-oriented, from Lotus by Alloy pages by equation It used parameter. refer analysis. regression Avenue, body calculations, worksheets the the worksheets contains can Formula for program and be One Pennsylvania is Body Effect n-channel (oLVsub 80li vt rneas ured _:__! .524 . 530 .554 .536 cz- O . 53027 0 . 22324 0 0 **- r-t 0 .517 . . . 522 o 0 586 0 527 0 .531 0 .912 . 927 .943 -942 .911 . 893 .953 4 J. . . 010 995 .932 1 1 1 . . H 1 1 1 070 .110 . . . 140 120 -4 060 -4 140 -4 . 1 .210 i . 1 . -4 -4 080 1 4 -4 -4 190 -4 1 10 -4 tXi^ ;; 6u ===== :: r" = ~ Regression , Variable: Vmsn6 Coefficient List: gamma Correlation Coefficient: Dependent Analysis .530274607 Variable -.22324124 : == Equation Coefficient t Sheet Equation Gms=0m- * v)u Corresponding Vsubstrate St (Chi+Eg/2-Ph i ) * Eox-Erx*E0 * Cox=Eox/to:: * * Vt=0ms-q*Nss/Cox-2*Phi_f-2/Cox* (q*Esi *E0*Nsub*Phi NSUB=1/ (q*un*rho) * Phi_f * Vtp=(Vsub+2*Phi_f ) * Sn=5ign (Vtp) =kb*ln Cp=(2*Phi_f )-.5 * Vsubstrate=Sn# St Name 0 Phi_f (Sn*Vtp>--. Val . ue 4 I ni 1.45E10 0 rho 25.51897818 I kb I an Cal Un i t Comment s Fermi potential Electron charge comparison atom/cm3 atam/cm3 Calc l/cm3 l/cm3 intrinsic ChiTi/sq Ohm/sq Sheet Volt Volt kT/q 610 cm2/Vsec IM-ch 210 cm2/Vsec P-ch . . 01E14 025256 for czs.rrier mobility, Vds=10, mobility, Vds=10, n channel substrate Vmsn6 measurements IL Vmsp6 measurements measurements IL VmspSO OL Vsubstrate IL Vsubl 0 Oms I O.T, 4. 1 I Chi 4. 15 I Eg Co:-: 0 Eox I to:: Nsub to calculate prior p substrate channel -.3516484918 1. 12 . 0000000485 3. 45306E-13 . 000007 1 1 cm threshol d IL Vt OL Nss I bi measurements IL Vmsn80 0 conci resistance Vtemp Vtp IL Vsub IL Sheet 25835 1 503 1 q NSUB OL Dsp Unit 1.602E-19 I up L gamma -. 5-Cp Variable I > (Nsub/ni ) * I ============ .9759006991 Intercept: Independent Sheet surface 4. 017E14 vol tc?qes states atom/cm3 si gn OL Sri pre-calculatian 0 Cp I Erx 3.9 I EO 8. I Esi 11.7 .7188205731 854E-14 Oxide F/cni Si 1 i con reqt bi Body vt Effect n-channel Vsub Vt gamma measured 559 0 602 0 623 0 620 0 591 0 587 o 618 o 666 o 649 o . m , . . . . o . , ,988 1. 050 1. 070 , 1 060 ., 1 1 020 .. 010 ,, 1 070 . . 130 . 060 1. 1 10 1 1 1 . 220 . 270 i 1 J. . 300 i . .iCiO . 230 i i 1 1 1 r~. .". .210 -4 -4 -4 300 -4 . 360 -4 . 340 -4 . 270 -4 . . -. 6043 1 25090 SOu x80u : ========= Dependent Regression Vmsn80 === ;-; Variable: Coefficient List: Correlation Coefficient: Variable (Chi +Eg/2-Phi_f ) Eox=Erx *E0 * Cox=Eox /tox Vt=0ms- iub*Phi q*Nss/Co::-2*Phi_f-2/Ci * NSUB=1/ (q*un*rho) * Phi_f * Vtp=(Vs;ub+2 *Phi_f ) * Sn=sigri(Vtp ) =kb*ln Cp=(2*Fhi_f )--.5 * Vsubstrate= Sn*(Sn*Vtp) --.5-Cp Variable St Name Q Fhi_f T I un I up L Cal Unit Comments potential Electr on 1.602E-19 ni kb Unit ===================== Fermi 1.45E10 I Dsp Sheet .2583515081 4 rho I Value q NSUB 0 f) (Nsu.b/ni ) * I iT -.2509045842 * 1 Coefficient Equation 0ms=0m- * \)k Corresponding Vsubstrate # === -9720538131 .6043109149 Independent Sheet gamma Intercept: St Analysis 01E14 . 25.51897818 025256 . c fcr Calc h ar g e comparison atom/cm3 atom/c;T,3 l/cm3 l/cm3 intrinsic Ohm/sq Dhm/sq Sheet Volt Volt kT/q cm2/Vsec N-ch mobility, c m2 / Vsec P-c h mob 610 210 carrier cone resistance i 1 i ty Vds=10, Vd s= 1 0 , . gamma OL Vtp IL Vsub Vtemp n-channel substrate bi measurements IL Vmsn6 IL VmsnSO measurements measurements IL Vmsp6 IL VmspSO OL Vsubstt -ate measurements IL Vsub 1 0 Oms to calculate prior p-channel substrate -.3516484918 I Om 4. 1 I Chi 4. 15 1. 12 I Eg 0 Cox D Eox I tox IL Vt DL Nss I Nsub OL Sn 0 Cp I 7, I Erx EO I Esi 11.7 . 0000000485 3. . 45306E-13 OOOUO/l 1 cm threshold surface 4.017E14 voltages states atom/cm3 sj gn pre . cal cul at 71S8205731 Oxi de Q 8.854E-14 F/cm oil icon i on rer. bi Body Vt Effect Vsub -1.740 3 -1.800 3 -1.840 3 -1.820 3 -1.760 3 -1.740 3 -1830 3 S30 3 860 3 -IvSOO 3 i r -1 , 120 5 -2.150 5 -2. -2.130 5 060 5 2. -2.050 ^ -> =0 '-?U 70 - "? 4 ' channel Vt gamma measured - p 0 -2. 500 2. 47u 5 5 -1.07071 -.66448 80u x 6u Regression Analysis Sheet Variable: Vmsp6 Joefficient List: gamma Correlation Coefficient: dependent - Intercept: Independent 070705396 Corresponding Vsubstrate Coefficient -.6644818502 : St 9355776657 -1. Variable ==-- === Equation Sheet Equation * 0ms=0m-(Chi+Eg/2-Phi_f ) * Eox=Erx*E0 * Cox=Eo:</tox * Vt=0ms-q*Nss/Cox-2*Phi_f-2/Cox*(q*Esi*E0*Nsub*Phi_f * NSUB=1/ (q*up*rho) * Phi_f=kb*ln (Nsub/ni ) * Vtp=(Vsubl+2*Phi_f ) * Sn=sign(Vtp) * Cp=(2*Phi_f )'-.5 * Vsubstrate=Sn* (Sn#Vtp) '-. St Name d Phi 5-Cp Variable I Value Cal =========================== Unit Comments Fermi Electron charge comparison 7.96483087E12 I ni 1 I rho 3732 I kb I un up Sheet .3143885011 q NSUB L Dsp Unit 1.602E-19 f 0 I ) potential atom/cm3 atom/cm3 Cal l/cm3 l/cm3 intrinsic Ohm/sq Ohm/sq Sheet Volt Volt kT/q 760 cm2/Vsec N-ch 210 cm2/Vsec P-ch . . 45E 1 0 025256 c for carrier cor, resistance mobility, Vds=lC mobility, Vds=lC gamma OL Vtp IL Vsub Vtemp n-channel substrate IL Vmsn6 IL VmsnBO measurements IL Vmsp6 IL VmspBO measurements OL Vsubstrate IL Vsubl calcualte prior p-channel substrate threshold voltage? measurements measurements 0 Oms -. I Om 4. 1 I Chi 4. 15 I Eg 0 Cox 0 Eox I tox Nsub 1. 12 . 0000000485 3.45306E-13 . 000007 1 1 cm surface 3.694E15 Cp states atom/cmo si gn OL Sn 0 to 29561 i49ee TL Vt L Nss I b . pre-calculati on 7929546029 I Erx 3.9 I EO 8.854E-14 I Esi 11.7 Oxide F/cm 2: 1 l con re b Body vt Effect Vsub p-channel Vt gamma measured -1. 820 1.00912 -1. 880 -.77364 -1. 8S0 i 870 . 820 -1. 800 -1., A _ 830 -1 950 ,, Q'Tif-^ -1. 870 -1,. -n 160 , 230 ~~ *zi .. -i .270 ""? j-i i-^ . *** C: 160 150 J^ _'T . 240 '-i .340 *-> rf.f. -2. 450 ^1. JOv -2.470 _ *? 4.40 7 7 -2.550 -2.640 7 -2.610 7 -2.510 7 80u xBOu Dependent Regression Analysis Sheet Variable: Coefficient Correlation ==-- Vmsp80 List: gamma Coefficient: . Intercept: 9590938969 -1.009122797 Independent Variable Corresponding Vsubstrate -. -=== St Equation * 0ms=0m- * Eo:<=Erx*E0 (Chi +Eg/2-Phi Coefficient 7736411525 Equation Sheet === ) * Cox=Eox/to:< * * Vt=0ms-q*Nss/Cox-2*Phi_f-2/Cox* (q*Esi*EO*Nsub*Phi NSUB=1/ <q*up*rho) * Phi_f * Vtp=(Vsubl+2*Phi_f ) * Sn=sign(Vtp) =kb*ln ) (Nsub/ni ) * Cp=(2*Phi_f ) -.5 * Vsubstrate=Sn* St Name )i Phi_f (Sn*Vtp "-.5-Cp Variable Value Dsp Unit Sheet Cal =========================== Unit Comments Fermi .3143885011 1.602E-19 potential Electron charge comparison 0 q NSUB 7.96483087E1 atom/cm3 atom/cm3 Calc I ni 1.45E10 l/cm3 l/cm3 intrinsic I rho 3732 Ohm/sq Ohm/sq Sheet I kb Volt Volt kT/q I un 760 cm2/Vsec N-ch up 210 cm2/Vsec I L . 025256 P for carrier mobility, ch mobility, Vtemp Vtp IL Vsub n-channel IL Vmsn6 measurements IL Vmsn80 measurements Vsub 1 0 Oms r Om 4. 1 i Chi 4. 15 i Eg Cox 0 Eox I tox IL Vt -- Nsub Sn 0 Cp to calcualte prior pchannel substrate threshold vol 29561 14988 1. 12 . 0000000485 3.45306E-13 . 0000071 1 cm surface Nss OL : measurements Vmsp6 IL Vmsp80 OL Vsubstrate D substrate measurements IL } Vds=l' Vds=l' gamma OL IL cor resistance tags states 3.694E15 si gn pre . 7929546029 I Erx 3.9 I EO 8.854E-14 I Esi 11.7 cal culation Oxide F/cm Si 1 i con ri t Nsub gamma -.22324 calculation Nsub 3.542E 14") t/JH i4j^0xl -.25090 -.66448 - . 77364 4.474E 3.138E 157 4 15 . 253E j .1 . W5 ====== St tS id Equation * Eox=E0*Erx * Cox=Eox/tox # NSUB=gamma-"-2*Cox-'-2/ (2*q*ESi*E0) St Name Value I q NSUB 1.602E-19 OL )- Sheet Equation Dsp Unit gamma Cox 0 Eox I tox .00000711 I ESi 11.7 I EO 8.854E-14 I Erx 3.9 . 0000000485 Unit Comments Electron atom/cm3 d Cal F/cm"2 3. 45306E-13 cm F/cm atom/oTi3 Substrate charge doping con Calculation Vt Nss regressed calculated surface of .530 -4.758E 11 T-2 .604 -4.983E 11 TJ 0,w Calculation -1.070 -1.009 U>^ surface '.71 "JS Ns Vt regressed of states calculated -1.291E 11 "T^ <>/>- -1.478E 11 VI ^r states St Equation 0ms=0m-(Chi+Eg/2-Phi_f ) Eox=Erx*EO Cox=Eox/tax Vt=0ms-q*Nss/Cox-2*Phi_f-2/Cax* NSUB=1/ Cq*Esi*EO-*Nsub*Phi_f ) " 5 . (q*un*rha) Phi_f =kb*ln (Nsub/ni ) Vtp= ( Vsub+2*Phi ) Sn=sign (Vtp) Cp=(2*Phi_f )"-.5 Vsubstrats=Sr! St Name 0 Phi_f I (Sn*Vtp ) ". 5Cp Value Dsp Unit Cal Unit Comments Fermi .2583515081 potential Electron 1.602E-19 charge 0 q NSUB 8.21341743E14 atom/cm3 atom/cm.3 Calc I ni 1.45E10 l/cm-3 l/cm3 intrinsic Ohm/sq Ohm/sq Sheet Volt Volt kT/q 10 for comparison carrier t f-ha I kb t an 760 cm2/Vsec N-ch mobility, ;;-. 21*? cm2/Vsec P-ch mobility, .025256 <za: resistance Vds=l: Vds=l' T L gamma l ?L ij. _,- Vut.i! Vtp IL Vsub IL me as j.ême.n Vmsn-6 IL VmsnBO mea IL VmspSO OL Vsubstrate 0 0ms I 0m 4.1 I Chi 4.15 I Eg Q Cox Eox tax s ts = _- r5;^8n ts to caicuiite prior p substrate IL Vsubl I t measurements IL Vmspo 0 e men measu channel -.3516484918 1.12 - 0000000485 3.45306E-13 . 00O00711 cm threshold IL Vt surface OL Nss I Nsub OL Sn 0 Cp I Erx 3.9 I EO 8.854E-14 I Esi U-7 4.017E14 voltages states atom/urn- sign pre calc ulati on .7188205731 0:-: ide F/cm Si 1 i con r~ ':. APPENDIX D GATE CLOCK TIMING SPICE SIMULATIONS ,#####?06/2 1/86- ******** SPICE 26.5 (10AUB81) *****#**10: 29:21***** TRANSMISSION SATE WITH EK TRANSISTORS LISTING INPUT Figure TEMPERATURE = 27.000 DEG ###**************************##*****^ FEEDTHROUGH ANALYSIS t * C S BELL 5 1E-6 * 1 VNWELL VSRC 2 DC PULSE (-1 VGN 5 0 DC 6 Ml 3 5 2 O 1E-12 1E-12 2.9E-6 3.5E-6) 1 DC VGP 4 0 VID 3 O 0 2 0 DC O T280 L=80U W=80U NRS=. 1 NRD=. 1 AD=1280P AS=1280P PD=192U NRD=. 1 AD=1280P AS=1280P PD=192U PS=192U + M2 3 4 2 1 T480 L=80U W=80U NRS=. 1 PS=192U + CI 6 0 50P Rl 6 0 75K T26 .MODEL NMOS LAMBDA=.0175 NSUB=4.008E14 +XJ=.5U +CGDO=2.91E-10 CJ=1.77E-4 VT0=.53 LEVEL=2 +LD=.2U T280 NMOS .MODEL +CGDO=2.91E-10 +LD=.2U MJ=.5 RSH=48.92 MJ=.5 CJ=1.77E-4 LEVEL=2 VT0=.604 TPG=1 PB=.B71 T0X=.0711U CGS0=2. 91E-10 CJSW=8. 85E-1 1 GAMMA=.2232 LAMBDA=. 00155 NSUB=4.008E14 +XJ=.5U U0=610 RSH=48.92 MJSW=.3 NSS=4.758E11 T0X=.0711U TPG=1 U0=610 PB=.B71 CGS0=2. 91E-10 CJSW=8. 85E-1 1 MJSW=.3 NSS=4.983E11 GAMMA=.2509 + .MODEL +XJ=.8U T46 LAMBDA=.0275 PMOS NSUB=3.7E16 +CGDO=4.B5E-10 RSH=285.6 CJ=.958E-5 +LD=.6U LEVEL=2 VTO=- U0=178 MJ=.5 1.070 TPG=-1 PB=.719 T0X=.0711U CGS0=4.B5E-10 CJSW=. 958E-1 1 GAMMA=.6645 MJSW=.3 NSS=1.291E11 + MODEL +XJ=.8U T480 PMOS LAMBDA=. 00155 NSUB=3.7E16 RSH=285.6 +CGD0=4.85E-10 CJ=.958E-5 MJ=.5 +LD=.6U LEVEL=2 WIDTH VTO=- 0UT=80 OPTION LIMPTS=1E6 TRAN 1E-7 3.5E-6 .PLOT .END TRAN V(6> V(5) 1.009 U0=178 PB=.719 TPG=-1 CJSW=. 958E-1 1 GAMMA=.7736 T0X=.0711U CGS0=4. 85E-10 MJSW=.3 NSS=1.478E11 C 28 t##*##*06/21/B6 ******** GATE TRANSMISSION MOSFET SPICE 2G. 5 WITH EK (10AUG81) ******** 10: 29: 21***** TRANSISTORS MODEL PARAMETERS TEMPERATURE Figure = 27.000 DEG C ##********************************************************************* T26 T280 NMOS TYPE NMOS T480 T46 PMOS PMOS LEVEL 2.000 2.000 2.000 2.000 VTO 0.530 0.604 -1.070 -1.009 8.65D-06 2.96D-05 2. 96D-05 B.65D-06 GAMMA 0.223 0.251 0.665 0.774 PHI 0.529 0.529 0.763 0.763 75D-02 1. 55D-03 2.75D-02 0.871 0.871 0.719 0.719 4.85D-10 4.B5D-10 4.85D-10 KP LAMBDA 1 . PB , 1 . 55D-03 CGSD 2.91D-10 2. CGDO 2.91D-10 2. 91D-10 4.85D-10 48.920 48.920 285.600 285.600 77D-04 1. 77D-04 9.58D-06 9.58D-06 RSH CJ MJ CJSW mjsw tox 1 . .91D-10 , 0.500 0.500 0.500 8. 85D-11 9.58D-12 9.58D-12 0.500 8.85D-11 , 0.300 0.300 0.300 0.300 7- 11D-08 7. 11D-08 7- 11D-08 7- 11D-08 , NSUB 4.01D+14 4, 3.70D+16 3.70D+16 NSS 4.76D+11 4, 98D+11 1.29D+11 1.48D+11 TPG 1.000 l.OOO -1.000 -1.000 XJ 5.00D-07 5. 00D-07 8.00D-07 8.00D-07 LD 2.00D-07 00D-07 6.00D-07 6.00D-07 UD 610.000 610.000 178. OOO 178.000 .01D+14 . . . 28 *****06/2 1/86 ****??*? SPICE 26. 5 (10AUG81) ******** 10: 29: 21***** TRANSMISSION 6ATE WITH EK TRANSISTORS INITIAL TRANSIENT SOLUTION Figure TEMPERATURE = 27.000 DE6 28 C ###*##*#**********##**#****##^##^^#####^#########^#^#^#^### V0LTA6E NODE NODE VOLTAGE ( 1) 0.0000 ( 2) 0.0000 ( 5) -1.0000 ( 6) 0.0000 VOLTAGE SOURCE -2.230D-39 VSRC -1.306D-39 O.OOOD+OO VID 9.24OD-40 #****#*06/21/86 DISSIPATION ******** TRANSMISSION OPERATING ID 0.0000 ( 4) VOLTAGE l.OOOO O.OOOD+OO VGP TOTAL POWER VGS VDS VBS 3) NODE CURRENTS VNWELL VGN MODEL ( VOLTAGE CURRENT NAME **** NODE SPICE GATE POINT WITH Ml M2 T480 O.OOD+OO 2G.5 EK O.OOD+OO -1.000 l.OOO 0.000 0.000 0.000 0.000 WATTS (10AUG81) ******** 10: 29: 21***** Figure TRANSISTORS INFORMATION MOSFETS T2B0 O.OOD+00 TEMPERATURE = 27.000 DEG C 28 1/86. ******** SPICE 2G. 5 (10AUG81) ********10: 29: 21***** GATE WITH EK TRANSISTORS Figure 28 TRANSIENT ANALYSIS TEMPERATURE = 27.O00 DE6 C ###*##*06/2 TRANSMISSION w##***********************************#***#******#*#***#******* LEGEND: : V(6) +: V(5) (*) (+) -5.000D-02 O.OOOD+OO 5.000D-02 l.OOOD-Ol 1.500D-01 -2.0O0D+00 O.OOOD+OO 2.000D+00 4.000D+00 6.000D+00 V(6) TIME O.OOOD+OO 6.930D-35 1.000D-07 1.187D-1B 2.000D-O7 1.354D-18 3.00OD-O7 1.159D-18 4.000D-07 9.017D-19 5.00OD-O7 6.547D-19 6.000D-07 4.191D-19 * . . * . * . * . * . * . * 7.000D-07 1.935D-19 . * 8.000D-07 -2.222D-20 . * 9.00OD-O7 -2.281D-19 . * . * 1.000D-06 -4.440D-19 1.100D-06 7.084D-02 1.200D-06 5.309D-02 1.300D-06 4.096D-02 1.400D-06 3. 120D-02 . . . . 1.500D-06 2.295D-02 . 1.600D-06 1.754D-02 . 1.700D-06 1.393D-02 + . 1.800D-06 1.011D-02 1.900D-O6 7- 104D-03 2.000D-06 5.995D-03 2. 100D-06 4.710D-03 . 2.200D-06 2.300D-06 2.400D-06 2.500D-06 2.895D-03 . 2.600D-06 2.700D-06 2.BOOD-06 2. 900D-06 3.000D-06 3. 100D-06 3.200D-06 3.30OD-O6 3.400D-06 3.500D-06 2.340D-03 2.472D-03 1.417D-03 5.619D-04 1.043D-03 . . . . * . * . * . * . 9.052D-05 . 8.629D-04 * * . * . * 1.960D-04 . -3.571D-04 . 3.427D-04 7.476D-04 * . 9.799D-04 2.120D-04 * * * . * . JOB CONCLUDED TOTAL JOB TIME O. 17 ******** t##****06/21/86 SPICE 26.5 (10AU6B1) ********10:35:02***** TRANSMISSION 6 ATE WITH EK TRANSISTORS LI ST INS INPUT Figure TEMPERATURE = 27.000 DEG C ***** ?*##*******************************###****#***#^#####^< FEEDTHROUGH ANALYSIS * C S BELL -6.5 1E-6 # * VNWELL 1 2 VSRC 2 O DC O O PULSE (1 VGP 4 0 DC VGN 5 0 DC VID 3 6 Ml 3 5 DC 2 O 1E-12 1E-12 2.5E-6 3.5E-6) O 0 T280 L=80U W=80U + NRS=. 1 NRD=. 1 AD=1280P AS=1280P PD=192U NRD=. 1 AD=1280P AS=1280P PD=192U PS=192U M2 3 4 2 1 T4B0 L=80U W=80U NRS=. 1 PS=192U + CI 6 0 50P Rl 6 0 .MODEL +XJ=.5U 75K T26 NMOS MODEL +XJ=.5U LEVEL=2 VTO=.53 T280 NMOS MJ=.5 LAMBDA=. 00155 NSUB=4.008E14 RSH=48.92 MJ=.5 TPG=1 PB=.871 T0X=.0711U CGS0=2. 91E-10 CJSW=8. 85E-1 1 GAMMA=.2232 +CGD0=2.91E-10 CJ=1.77E-4 +LD=.2U U0=610 RSH=48.92 CJ=1.77E-4 +CGDO=2.91E-10 +LD=.2U LAMBDA=.0175 NSUB=4.008E14 MJSW=.3 NSS=4.758E11 T0X=.0711U UQ=610 TPG=1 PB=.B71 CGS0=2. 91E-10 CJSW=8.B5E-11 LEVEL=2 VT0=.604 GAMMA=.2509 MJSW=.3 NSS=4.983E11 + .MODEL +XJ=.8U T46 PMOS LAMBDA=-0275 NSUB=3.7E16 RSH=285.6 U0=178 TPG=-1 PB=.719 T0X=.0711U CGS0=4. B5E-10 +CGD0=4.85E-10 CJ=.958E-5 MJ=.5 CJSW=. 958E-1 1 +LD=.6U LEVEL=2 VTO=- 1.070 GAMMA=.6645 MJSW=.3 NSS=1.291E11 + MODEL T480 PMOS LAMBDA=.00155 U0=17B TPG=-1 +XJ=.8U NSUB=3.7E16 +CGDO=4.85E-10 +LD=.6U LEVEL=2 WIDTH RSH=285.6 CJ=.958E-5 VTO=- 0UT=80 OPTION LIMPTS=1E6 TRAN 1E-7 3.5E-6 PLOT TRAN V(6) V(4) END 1.009 PB=.719 MJ=.5 CJSW=. 958E-1 1 GAMMA=.7736 T0X=.0711U CGS0=4. 85E-10 MJSW=.3 NSS=1.478E11 29 ###*#**06/21/86 ******** TRANSMISSION MOSFET SPICE 2G.5 BATE WITH EK (10AU681) ********10: 35: 02***** TRANSISTORS MODEL PARAMETERS TEMPERATURE Figure = 27.000 DEB C #*#******************************************************************* T26 T280 NMOS TYPE NMOS T46 T480 PMOS PMOS LEVEL 2.000 2.000 2.000 2.000 VTO 0.530 0.604 -1.070 -1.009 8.65D-06 *- 1 96D-05 8.65D-06 GAMMA 0.223 0.251 0.665 0.774 PHI 0.529 0.529 0.763 0.763 75D-02 1. 55D-03 2.75D-02 0.B71 0.871 0.719 0.719 KP LAMBDA 2.96D-05 1 . PB . 1 . 55D-03 CGSO 2.91D-10 2, .91D-10 4.85D-10 4.85D-10 CGDO 2.91D-10 2. 91D-10 4.85D-10 4.85D-10 4B.920 48.920 285.600 285.600 77D-04 1. 77D-04 9.58D-06 9.58D-06 RSH CJ MJ CJSW 1 . , 0.500 0.500 0.500 0.500 B.85D-11 8. B5D-11 9.58D-12 9.58D-12 . 0.300 0.300 0.300 0.300 TOX 7. 11D-08 7. 11D-08 7. 11D-08 7. 11D-08 NSUB 4.01D+14 4 3.70D+16 3.70D+16 4.76D+11 4, 98D+11 1.29D+11 1.48D+11 MJSW NSS TPG . . 000 -1.000 -1.000 00D-07 B.00D-07 B.00D-07 00D-07 6.00D-07 6.00D-07 <blO.OOO 178. OOO 178.000 1 1.000 XJ 5-OOD-07 5 LD 2.00D-07 o UO .01D+14 610. OOO . . . 29 ******** <hhhhhhK>6/21/86 SPICE 26.5 (10AU681) ********! O: 35: 02***** TRANSMISSION 6ATE WITH EK TRANSISTORS INITIAL TRANSIENT SOLUTION Figure 29 TEMPERATURE = 27.000 DEB C ***************************************************##^##^###^^## VOLTAGE NODE NODE VOLTAGE ( 1) 0.0000 ( 2) 0.0000 ( 5) 0.0000 ( 6) 0.0000 VOLTAGE SOURCE NAME NODE < 3) -2.230D-39 VSRC -1.306D-39 O.OOOD+OO VID 9.240D-40 DISSIPATION ******** SPICE TRANSMISSION GATE WITH OPERATING POINT O.OOD+OO VDS VBS 1.0000 2G.5 EK WATTS (10AUG81) INFORMATION MOSFETS Ml M2 T280 T480 O.OOD+OO O.OOD+OO 0.000 1.000 0.000 0.000 0.000 0.000 ******+*10: 35: 02***** TRANSISTORS TEMPERATURE ?**#******#**-*.**.*.*.**.tt-tt.*-*-jMfr******************^ !D 4) O.OOOD+OO VGN ?******06/21/86 yGS ( VOLTAGE CURRENTS VNWELL TOTAL POWER MODEL 0.0000 NODE CURRENT VGP **** VOLTAGE Figure = 27.000 DEG C 29 SPICE 26>5 (10AIJG81) TRANSMISSION GATE WITH EK TRANSISTORS ###****06/21/86^******* TRANSIENT ANALYSIS *^^10:35:02***** TEMPERATURE Fiaure 27.000 = d!g -?9 C t##***********************^HHHt****^,^##^#^^########^######^##^### LEGEND: *: V(6) +: V(4) (*) -1.50OD-01 1.000D+01 (+) -1.000D-01 -5.000D-02 O OOOD+OO O.OOOD+OO 5 -5. . OOOD+OO 5 . OOOD+OO 1 V(6) TIME 0. OOOD+OO 6.930D-35 . 1.000D-07 -4.623D-29 . * OOOD-07 -5.265D-29 . * OOOD-07 -5.771D-29 . OOOD-07 -6.253D-29 . OOOD-07 -6.715D-29 OOOD-07 -7. 156D-29 * * * . * . * OOOD-07 -7.578D-29 . * B. OOOD-07 -7.982D-29 . * 9. OOOD-07 -8.367D-29 . l.OOOD-06 -8.736D-29 . 1.100D-06 -1.055D-01 1.200D-06 -9.206D-02 1.300D-06 ,4000-06 . -B.340D-02 . -7.562D-02 . . 500D-06 -6.526D-02 . 600D-06 -5.742D-02 . 700D-06 800D-06 1.900D-06 2. OOOD-06 2. 100D-06 2. 200D-06 , 2.300D-06 2. 400D-06 2.500D-06 2.600D-06 2.700D-06 2.800D-06 2.900D-06 -5.297D-02 . -4.652D-02 . -3.917D-02 . -3.623D-02 . -3.360D-02 . -2.785D-02 . -2.415D-02 . -2.335D-02 -2.020D-02 -1.584D-02 -1.545D-02 * * . * . . -1.512D-02 . -1.146D-02 . -9.559D-03 . 3. 100D-06 -1.O29D-02 . 3.200D-06 -8.556D-03 . 3.400D-06 3.500D-06 * . 3. OOOD-06 3. 300D-06 + . . . * * + * + * + * + * * * -5.514D-03 . * -6.350D-03 . -7.393D-03 . * JOB CONCLUDED TOTAL JOB TIME O. 19 . 000D-02 . OOOD+0 1 ******** #####**06/21/86 SPICE 26. 5 (10AU681) ******** 10: 39: 02***** TRANSMISSION BATE WITH EK TRANSISTORS INPUT LI ST INS Figure TEMPERATURE = 27.000 DEB C ###*#****************************?*#*?*?*?***????*???*##*******#**#**# FEEDTHROUBH ANALYSIS * C S BELL # 2 DC 1 VNWELL VSRC 2 0 DC PULSE (1 VGP 4 0 VGN 5 O O 0 DC VID 3 6 Ml 3 5 2 1E-6 1E-12 1E-12 2.5E-6 3.5E-6) 6E-6 1E-12 1E-12 2.9E-6 3.5E-6) -6.5 PULSE (-1 5 . O 0 T2B0 L=80U W=80U NRS=. 1 NRD=. 1 AD=1280P AS=1280P PD=192U NRD=. 1 AD=12B0P AS=1280P PD=192U PS=192U + M2 3 4 2 1 T480 L=BOU W=80U NRS=. 1 PS=192U + CI 6 0 50P Rl 6 0 75K .MODEL +XJ=.5U T26 +CGDO=2.91E-10 +LD=.2U .MODEL +XJ=.5U VT0=.53 LEVEL=2 T280 NMOS MJ=.5 RSH=48.92 MJ=. 5 CJ=1.77E-4 VT0=.604 TPG=1 PB=.B71 T0X=.0711U CGS0=2. 91E-10 CJSW=8. 85E-11 GAMMA=.2232 LAMBDA=. 00155 NSUB=4.008E14 LEVEL=2 U0=610 RSH=48.92 CJ=1.77E-4 +CGDO=2.91E-10 +LD=.2U LAMBDA=.0175 NMOS NSUB=4.008E14 MJSW=.3 NSS=4.758E11 T0X=.0711U TPB=1 U0=610 PB=.871 CGS0=2. 91E-10 CJSW=8.85E-1 1 MJSW=.3 NSS=4.9B3E11 GAMMA=.2509 + .MODEL T46 LAMBDA=.0275 PMOS +XJ=.BU NSUB=3.7E16 +CGDO=4.85E-10 RSH=285.6 CJ=.958E-5 TPB=-1 PB=.719 MJ=.5 T0X=.0711U CGS0=4.B5E-10 CJSW=. 958E-1 1 GAMMA=.6645 VT0=-1.070 +LD=.6U LEVEL=2 U0=178 MJSW=.3 NSS=1.291E11 + MODEL T480 PMOS LAMBDA=. 00155 +XJ=.BU NSUB=3.7E16 +CGD0=4.B5E-10 CJ=.958E-5 +LD=.6U LEVEL=2 WIDTH RSH=285.6 OPTION LIMPTS=1E6 TRAN 1E-7 3.5E-6 PLOT .END TRAN VC6) MJ=.5 VT0=-1.009 0UT=80 V(5) V(4) U0=178 PB=.719 TPB=-1 CJSW=. 958E-1 1 GAMMA=.7736 T0X=.0711U CBS0=4.85E-10 MJSW=.3 NSS=1.47BE11 30 #######06/2 1/86 ******** (10AU681) ********10:39: 02***** BATE WITH EK TRANSISTORS TRANSMISSION MOSFET SPICE 26.5 MODEL PARAMETERS TEMPERATURE Figure = 27.000 DEG C ?ft********************************************************************* T26 T280 NMOS TYPE NMOS T46 T480 PMOS PMOS LEVEL 2.000 2.000 2.000 2.000 VTD 0.530 0.604 -1.070 -1.009 8.65D-06 2.96D-05 2. 96D-05 8.65D-06 GAMMA 0.223 0.251 0.665 0.774 PHI 0.529 0.529 0.763 0.763 KP LAMBDA 1 . 75D-02 1. .55D-03 0.e71 0.B71 PB 2.75D-02 1 . 55D-03 0.719 0.719 CGSO 2.91D-10 2, .91D-10 4.85D-10 4.B5D-10 CGDO 2.91D-10 2. 91D-10 4.85D-10 4.85D-10 48.920 48.920 285.600 285.600 77D-04 1. 77D-04 9.58D-06 9.58D-06 RSH CJ MJ CJSW MJSW TOX 1 . , 0.500 0.500 0.500 0.500 B.B5D-11 8. 85D-11 9.58D-12 9.58D-12 , 300 0.300 0.300 7. 11D-08 7. 11D-08 7. 11D-08 0 0.300 7. 11D-08 . . NSUB 4.01D+14 4, 3.70D+16 3.70D+16 NSS 4.76D+11 4, 9BD+11 1.29D+11 1.4BD+11 TPG 1.000 XJ 5.00D-07 LD 2.0OD-O7 UO 610. OOO .01D+14 . 000 -1.000 -1.000 5, 00D-07 8.00D-07 8.00D-07 00D-07 6.00D-07 6.00D-07 610.000 178.000 178.000 1 . . . 30 ******** ft*****06/21/86 SPICE 2B>5 (10AUGai) #l0l39:02###w TRANSMISSION GATE WITH EK TRANSISTORS INITIAL TRANSIENT SOLUTION Figure TEMPERATURE = 30 27.000 DEG C ??**#*************************************^^#^#^####^#^^^####^^^ VOLTAGE MODE ( ( NODE 0.0000 1) 5) ( VOLTAGE SOURCE NAME 2) ( -1.0000 VOLTAGE NODE 0.0000 6) ( 3) VOLTAGE 0.0000 NODE ( 4) -2.230D-39 VSRC -1.306D-39 0.0000 O.OOOD+OO VID 9.240D-40 DISSIPATION ******** O.OOD+00 SPICE 2G.5 WATTS (10AUG81) ********10: 39: 02***** TRANSMISSION GATE WITH EK TRANSISTORS OPERATING POINT INFORMATION *****#iHHt********#*#-**##*******^ *D OOOO O.OOOD+OO VGN TOTAL POWER VGS VS VBS . CURRENTS VNWELL #****06/21/86 MODEL 1 CURRENT VGP **** VOLTAGE MOSFETS Ml M2 T2B0 T480 O.OOD+OO O.OOD+00 -l.OOO 1.000 0.000 0.000 0.000 0.000 TEMPERATURE Figure = 27.000 DEG C 30 t#*##**06/21/86 ******** TRANSIENT SPICE 26.5 6ATE TRANSMISSION (10AU681) WITH EK TRANSISTORS ANALYSIS ********10: 39: 02***** 30 Figure TEMPERATURE = DEG C 27. OOO ?ft********************************************************************* LEGEND: *: V(6> +: V(5) =: V(4) (#) D-01 -5.000D-02 O.OOOD+OO 5.000D-02 1.0O0D-O1 (+) D+00 O.OOOD+OO 2. OOOD+OO 4. OOOD+OO 6. OOOD+OO (=) D+01 OOOD+OO O.OOOD+OO 5. OOOD+OO l.OOOD+01 : TIME O.OOOD+OO 1. OOOD-07 V(6) 6.930D-35 1.187D-18 *r . . 2. OOOD-07 1.354D-18 . 3. OOOD-07 1.159D-1B . 4. OOOD-07 9.017D-19 . 5. OOOD-07 6.547D-19 . 6. OOOD-07 4.381D-19 . 7. OOOD-07 7.029D-02 . B. OOOD-07 9. OOOD-07 5.204D-02 4.096D-02 * = * = = . = * * * + -4.076D-02 1.300D-06 -2.923D-02 . 1.400D-06 -1.981D-02 . 1.500D-06 -1.276D-02 . 1.600D-06 -9.7B9D-03 * + + + . + * 1.200D-06 . * * + * + * . + * 156D-03 . -3.946D-03 . -7. * + * -2.B06D-03 . -2.963D-03 . * _ -1.439D-03 . -6.915D-05 . _ , -8.912D-04 . -9.889D-04 . _ _ 2.760D-04 . 9.717D-05 . * + * + * + * + * * -9.716D-04 . -1.030D-O4 . * * = . 3. OOOD-06 -3.128D-04 . 3. 100D-06 -5.958D-04 . 5.266D-04 . + + -t- = 7.889D-04 3.400D-06 3.500D-06 = = . . 3.200D-06 3.300D-06 * * = 3. 187D-02 2.B00D-06 2.900D-06 = . -5.B38D-02 2.200D-06 2.300D-06 2.400D-06 2.500D-06 2.600D-06 2. 700D-06 = * *+ 1.100D-06 1.B00D-06 1.900D-06 2. OOOD-06 2. 100D-06 = * = 1. OOOD-06 1.700D-06 -5. * * + + + = * 2.747D-04 . -8.231D-04 . + -9.61BD-04 . _ * CONCLUDED + -t- * = JOB + * ******** H*****06/21/86 SPICE 26.5 GATE TRANSMISSION (10AUB81) WITH EK TRANSISTORS LISTING INPUT ********10: 42:08***** Figure TEMPERATURE = 27.000 DEG C ??ft******************************************************************** FEEDTHROUGH # C # 2 DC VNWELL 1 VSRC 2 0 DC S O 0 VGP 4 0 PULSE (1 -6.5 VGN 5 0 PULSE (-1 5 VID 3 6 DC ANALYSIS BELL 1E-11 1E-12 1E-12 2.5E-6 3.5E-6) 1E-11 1E-12 1E-12 3.5E-6) 2.9E-6 O Ml 3 5 2 0 T280 L=80U W=BOU NRS=. 1 NRD=. 1 AD=1280P AS=1280P PD=192U NRD=. 1 AD=1280P AS=1280P PD=192U PS=192U + M2 3 4 2 1 L=80U T480 W=80U NRS=. 1 PS=192U + CI 6 0 50P Rl 6 0 75K .MODEL +XJ=.5U T26 +CGDO=2.91E-10 +LD=.2U .MODEL +XJ=.5U LAMBDA=.0175 NMOS NSUB=4.008E14 T280 VT0=.53 NMOS RSH=48.92 MJ=.5 CJ=1.77E-4 VT0=.604 +LD=.2U LEVEL=2 TPG=1 PB=.871 T0X=.0711U CGS0=2. 91E-10 CJSW=8. 85E-1 1 GAMMA=.2232 LAMBDA=. 00155 NSUB=4.008E14 +CGDCN2.91E-10 MJ=.5 CJ=1.77E-4 LEVEL=2 UQ=610 RSH=48.92 MJSW=.3 NSS=4.758E11 T0X=.0711U TPG=1 U0=610 PB=.B71 C6S0=2. 91E-10 CJSW=B.85E-1 1 MJSW=.3 NSS=4.9B3E11 GAMMA=.2509 + -MODEL LAMBDA=.0275 T46 PMOS +XJ=.8U NSUB=3.7E16 +CGD0=4.85E-lO RSH=285.6 CJ=.958E-5 +LD=.6U LEVEL=2 VTO=- 1.070 UQ=178 TPB=-1 PB=.719 MJ=.5 T0X=.0711U CGS0=4. B5E-10 CJSW=. 958E-1 1 GAMMA=.6645 MJSW-.3 NSS=1.291E11 + -MODEL T480 PMOS LAMBDA=. 00155 +XJ=.8U NSUB=3.7E16 +CGDO=4.85E-10 +LD=.6U LEVEL=2 .WIDTH RSH=285.6 CJ=.958E-5 VT0=-1.009 0UT=80 OPTION LIMPTS=1E6 TRAN 1E-11 4E-10 PLOT TRAN V(6) V(5) END V(4) U0=178 PB=.719 MJ=.5 TPG=-1 CJSW=. 958E-1 1 BAMMA=.7736 T0X=.0711U CBS0=4. 85E-10 MJSW-.3 NSS-1.47BE11 31 rt##***06/21/86 ******** BATE TRANSMISSION MOSFET SPICE 26.5 (10AU681) ******** 10: 42: 08***** WITH EK TRANSISTORS MODEL PARAMETERS TEMPERATURE Figure 31 = 27.000 DE6 C #ft******************************************************************** T26 T280 NMOS NMOS TYPE T46 T480 PMOS PMOS LEVEL 2.000 2.000 2.000 2.000 VTO 0.530 0.604 -1.070 -1.009 B.65D-06 96D-05 8.65D-06 0.223 0.251 0.665 0.774 PHI 0.529 0.529 0.763 0.763 1. 75D-02 1. 55D-03 2.75D-02 0.871 0.871 0.719 0.719 4.85D-10 4.85D-10 4.85D-10 LAMBDA 2. 96D-05 -> GAMMA KP , PB . *-\ 1 . 55D-03 CGSO 2. .91D-10 .91D-10 CGDO 2. 91D-10 2. 91D-10 4.85D-10 48.920 48.920 285.600 285.600 9.58D-06 9.58D-06 RSH CJ 1. 77D-04 , MJ CJSW 8. .77D-04 0.500 0.500 0.500 0.500 11. 8. 85D-11 9.58D-12 9.58D-12 , 0.300 0.300 0.300 0.300 7, 11D-08 7. 11D-OS 7. 11D-08 7. 11D-08 4, 3.70D+16 3.70D+16 1.29D+11 1.48D+11 MJSW TOX 1. . NSUB 4, NSS 4, .01D+14 .76D+11 TPG . .01D+14 4, 98D+11 . l.OOO l.OOO -1.000 -1.000 XJ 5, 00D-07 5, 00D-07 8.00D-07 8.00D-07 LD 2, 00D-07 -> 00D-07 6.00D-07 6.00D-07 610. OOO 178.000 178.000 UO . . 610.000 . . ******** *****06/21/86 SPICE 2B.5 TRANSMISSION BATE INITIAL U0AUB81) ******** 10: 42: 08***** WITH EK TRANSISTORS TRANSIENT SOLUTION Figure TEMPERATURE = 31 27.000 DEB C #**#**************************************#***#***^#*^^#^^##### VOLTABE NODE NODE VOLTASE ( 1) 0.0000 ( 2) 0.0000 ( 5) -1.0000 ( 6) 0.0000 VOLTAGE SOURCE NODE ( 3) VOLTAGE 0.0000 NODE ( 4) VOLTAGE 1.0000 CURRENTS CURRENT NAME VNWELL -2.230D-39 VSRC -1.306D-39 VGP O.OOOD+OO V6N O.OOOD+OO VID 9.240D-40 TOTAL POWER ##**##*06/21/86 DISSIPATION SPICE ******** TRANSMISSION OPERATING GATE POINT WITH O.OOD+00 2G.5 EK WATTS (10AUG81) ********10: 42: 08***** Figure TRANSISTORS INFORMATION TEMPERATURE = 27.000 DEG C *********************************************************************** **** MODEL ID VGS VDS VBS MOSFETS Ml M2 T280 T480 O.OOD+OO O.OOD+00 -1.000 1.000 0.000 O.OOO O.OOO 0.000 31 ####***06/21/86 ******** TRANSMISSION TRANSIENT BATE SPICE 26.5 (10AU681) WITH EK TRANSISTORS ANALYSIS ********10: 42: 08***** TEMPERATURE Figure = 27.000 DEB 31 C nil******************************************************************** LEGEND: ft: V(6) +: V(5) =: V(4) (*) -2.000D-02 O.OOOD+OO 2.000D-02 4.000D-02 6.000D-02 (+)- -2. OOOD+OO O.OOOD+OO 2. OOOD+OO 4. OOOD+OO 6. OOOD+OO (=) -l.OOOD+01 OOOD+OO O.OOOD+OO 5. OOOD+OO l.OOOD+01 -5. TIME | O.OOOD+OO 6.930D-35 l.OOOD-11 2.429D-19 2.000D-11 4.772D-02 3.000D-11 5. 159D-02 4.000D-11 4.432D-02 5.000D-11 3.521D-02 6.000D-11 2.717D-02 7.000D-11 2.049D-02 B.OOOD-11 1.489D-02 9.000D-11 1.056D-02 1.000D-10 7.078D-03 1.100D-10 4.25BD-03 1 200D-10 2.001D-03 1.300D-10 2.619D-04 128D-03 . * . * * . +* . . . . . . + . + . . . . . 1.500D-10 -2.240D-03 1.600D-10 -3. 129D-03 . 1.700D-10 -3.814D-03 . 1.800D-10 -4.363D-03 . -4.804D-03 . 157D-03 . 2.200D-10 2.300D-1O 2.400D-10 2.500D-10 2.600D-1O 2.700D-10 2.800D-10 2.900D-10 3.000D-10 3.100D-10 3.200D-10 3.300D-1O 3.400D-10 3.500D-10 3.600D-1O 3.7O0D-1O 3.B00D-1O -5. = * = * =* =* =* X -5.430D-03 . X -5.649D-03 . X -5.825D-03 . X -5.966D-03 . X -6.075D-03 . X 162D-03 . X -6. -6.233D-03 . X -6.289D-03 . X -6.333D-03 . -6.367D-03 . -6.395D-03 . -6.41BD-03 * = 1.400D-10 -1. 1.900D-10 2.000D-10 2.100D-10 + . . X X X X *= -6.435D-03 . *= -6.449D-03 . -6.460D-03 . -6.469D-03 . -6.476D-03 . + *= + *= *= *= -6.481D-03 . 3.900D-10 -6.485D-03 . *= ij,!oOOD-10 -6.489D-03 . *= JOB CONCLUDED TOTAL JOB TIME 0.53 ******** *****06/21/86 SPICE 26. 5 UOAUGBl) ********10: 46: 41***** TRANSMISSION BATE WITH EK TRANSISTORS INPUT LISTINB Figure TEMPERATURE = 27.000 DEG C f*** *******************************************^****^^^##^#1H FEEDTHROUGH ANALYSIS ? C ? S BELL * DC VNWELL 1 2 2 0 DC VSRC O O PULSE (O VGP 4 0 VGN 5 0 PULSE (-.4 VID 3 6 DC Ml 3 5 2 0 -6.0 5.6 . 5E-9 2. 10E-9 . 5E-9 2.25E-9 1E-10 2.5E-6 3.5E-6) 1E-10 2.5E-6 3.5E-6) 0 T280 L=80U W=80U NRS=. 1 NRD=. 1 AD=1280P AS=1280P PD=192U NRD=. 1 AD=12BOP PS=192U + M2 3 4 2 1 T4B0 L=80U W=BOU NRS=. 1 AS=1280P PS=192U + CI 6 0 50P Rl 6 0 75K .MODEL +XJ=.5U T26 NMOS -MODEL +XJ=.5U VT0=-53 LEVEL=2 T280 NMOS MJ=.5 RSH=48.92 CJ=1.77E-4 +LD=.2U LEVEL=2 VT0=.604 MJ=.5 TPG=1 PB=.871 T0X=.0711U CGS0=2. 91E-10 CJSW=8. 85E-1 1 GAMMA=.2232 LAMBDA=. 00155 NSUB=4.008E14 +CGDO=2.91E-10 U0=610 RSH=4B.92 CJ=1.77E-4 +CGDO=2.91E-10 +LD=.2U LAMBDA=.0175 NSUB=4.00BE14 MJSW=. 3 NSS=4.758E11 U0=610 TPG=1 PB=.B71 T0X=.0711U CGS0=2. 91E-10 CJSW=8. 85E-1 1 BAMMA=.2509 MJSW=.3 NSS=4.983E11 + MODEL T46 LAMBDA=.0275 PMOS +XJ=.8U NSUB=3.7E16 +CGDO=4.85E-10 +LD=.6U LEVEL=2 RSH=285.6 CJ=.958E-5 VTO=- 1.070 U0=17B TPG=-1 PB=.719 MJ=.5 T0X=.0711U CGS0=4.85E-10 CJSW=. 958E-1 1 BAMMA=.6645 MJSW=.3 NSS=1.291E11 + .MODEL T4S0 PMOS LAMBDA=. 00155 +XJ=.BU NSUB=3.7E16 RSH=285.6 U0=178 PB=.719 TPB=-1 T0X=.0711U CBS0=4. 85E-10 CJSW=. 958E-1 1 MJSW=.3 +CGDO=4.B5E-10 CJ=.958E-5 MJ VTO=NSS=1.478E11 GAMMA=.7736 +LD=.6U LEVEL=2 1.009 = WIDTH 0UT=80 OPTION LIMPTS=1E6 TRAN 5E-11 3E-9 PLOT TRAN V(6j V(5) END V(4) .5 PD=192U 32 ,###***06/21/86 ******** SPICE 26.5 (10AUBB1) ********10: 46: 41***** TRANSMISSION BATE WITH EK TRANSISTORS MOSFET MODEL PARAMETERS TEMPERATURE Figure = 27.000 DEG C #**#**************************??**?**???#**************************** T26 T280 NMOS TYPE NMOS T46 T480 PMOS PMOS LEVEL 2.000 2.000 2. OOO 2.000 VTO 0.530 0.604 -1.070 -1.009 8.65D-06 2. 96D-05 2. 96D-05 8.65D-06 GAMMA 0.223 0.251 0.665 0.774 PHI 0.529 0.529 0.763 0.763 1. 75D-02 1. 55D-03 2.75D-02 0.871 0.871 0.719 0.719 91D-10 4.B5D-10 4.85D-10 4.85D-10 KP LAMBDA . PB . 2. 1 . 55D-03 CGSO 2. CGDO 2. 91D-10 2. 91D-10 4.85D-10 48.920 48.920 285.600 285.600 1. 77D-04 1. 77D-04 9.58D-06 9.5BD-06 .91D-10 RSH CJ , 0.500 0.500 MJ CJSW , 8. 85D-11 , BSD- 8. , 11 0.500 0.500 9.58D-12 9.58D-12 0.300 0.300 0.300 0.300 TOX 7. 1 ID-OS 7. 11D-08 7. 11D-OB 7- 11D-0B NSUB 4, 4, 3.70D+16 3.70D+16 NSS 4. 4. 1.29D+11 1.4BD+11 MJSW , .01D+14 .76D+11 . .010+14 .98D+11 l.OOO 1.000 TPB -1.000 -1.000 XJ 5. 00D-07 5. 00D-07 8.00D-07 8.00D-07 LD 2. 0OD-O7 2. 00D-07 6.00D-07 6.00D-07 610.000 17B.000 178.000 UO , . 610. OOO , . ; ******** SPICE 26. 5 (10AU6B1) ********10: 46: 41***** TRANSMISSION BATE WITH EK TRANSISTORS Figure 32 INITIAL TRANSIENT SOLUTION TEMPERATURE = 27.000 DEG C #*****06/21/86 ##ft##*************************##***###**####^######^###^#^^^#######^^# NODE VOLTAGE NODE VOLTAGE ( 1) 0.0000 < 2) 0.0000 ( 5) -0.4000 ( 6) 0.0000 VOLTAGE SOURCE NODE ( 3) VOLTAGE NODE 0.0000 ( 4) VOLTAGE O.OOOO CURRENTS CURRENT NAME 230D-39 VNWELL -2. VSRC -1.306D-39 O.OOOD+OO VGP VGN O.OOOD+OO VID 9.240D-40 TOTAL POWER *******06/21/86 DISSIPATION ******** TRANSMISSION OPERATING SPICE GATE POINT WITH O.OOD+OO 2B.5 EK WATTS (10AUG81) ********10: 46: 41***** TRANSISTORS INFORMATION TEMPERATURE Figure = 27.000 DEG C *********************************************************************** **** MOSFETS MODEL ID Ml M2 T280 T480 O.OOD+OO O.OOD+00 VGS -0.400 0.000 VDS 0.000 0.000 VBS 0.000 0.000 32 ******** *#****06/21/86 TRANSIENT SPICE 26.5 (10AU681) 10: 46: 41***** ******** BATE WITH EK TRANSISTORS TRANSMISSION ANALYSIS Figure TEMPERATURE 27.000 = 32 C DEB LEGEND: *: V(6) +: V(5) =: V(4) 1 (#) . -5.000D-03 O.OOOD+OO 5.OO0D-03 1 O.OOOD+OO 2. OOOD+OO 4. OOOD+OO 6. OOOD+OO (+) -2. OOOD+OO (=) -6. OOOD+OO V(6) TIME - -4. OOOD+OO -2. 6.930D-35 . 5.000D-H -7.14BD-18 . * l.OOOD-10 -1.758D-17 . * * 1.500D-10 -3.029D-17 . 2.000D-1O -4.707D-17 . 2.500D-1O -7.059D-17 3.000D-10 3.500D-1O * + * . + * -1.003D-16 . + -1.356D-16 . * -1.766D-16 . 4.500D-10 -2.231D-16 . -2.934D-16 5.500D-10 -4.676D-05 6.000D-10 -9.522D-05 6.500D-10 -1.437D-04 * + 4.000D-10 5.000D-10 O OOOD+OO - O.OOOD+OO * * . * . * . * 7.000D-10 -1.922D-04 7.500D-1O -2.406D-04 . *. . *. . * B.OOOD-10 -2.891D-04 B.500D-10 -1.910D-04 . 9.000D-1O -7.619D-05 . . * = * * 9.500D-10 1.029D-03 . 1.000D-09 1.400D-03 . = X =* 1.050D-09 1.489D-03 . 1.100D-09 1.2B1D-03 . * = * ,= 1.150D-09 1.200D-09 1.250D-09 1.300D-09 1.350D-09 1.019D-03 . 7.213D-04 . = + + 4.302D-04 . 1.325D-04 . =.* X -1.450D-04 . -3.824D-04 . *+ 1.500D-09 1.550D-09 1.600D-09 1.650D-09 1.700D-09 1.750D-09 1.800D-09 1.850D-09 L900D-09 * = -6.116D-04 . -8.600D-04 . 103D-03 . -1.339D-03 . -1.574D-03 . -1.817D-03 . -2.044D-03 . -1. * * * * -2.321D-03 . -2.540D-03 . -2.796D-03 . * +* = = 1.400D-09 1.450D-09 O00D-O2 000D-02 .+ * . OOOD+OO 2 . . OOOD+OO L950D-O9 -3.056D-03 * 2.00OD-O9 -3.271D-03 * 2.050D-O9 -3.494D-03 * 2.10OD-O9 -3.708D-03 * 2.150D-09 -3.914D-03 2.200D-O9 -4. 2.250D-09 -4.325D-03 2.300D-O9 -4.53BD-03 * 2.350D-09 -4.752D-03 * 2.400D-O9 -4.967D-03 117D-03 * * 2.450D-09 -5.181D-03 2.500D-09 -5.397D-03 2.550D-09 -5.615D-03 * 2.600D-09 -5.836D-03 * 2.650D-09 -4.300D-03 2.700D-O9 -1.234D-03 2.750D-09 2.427D-03 2.800D-09 2.977D-03 *. *. 2.B50D-09 2.926D-03 * 2.900D-O9 2.911D-03 * 2.950D-O9 2.906D-03 * 3.000D-O9 2.904D-03 JOB CONCLUDED TOTAL JOB TIME 1.36 ******** ft*****06/21/86 SPICE 26. 5 (10AU6B1) ********10: 49: 58***** TRANSMISSION BATE WITH EK TRANSISTORS INPUT LISTINB TEMPERATURE fr-tl lLMHKUUGH ft C ft S Figure = 27.000 DEB analysis BELL ft VNWELL 1 2 VSRC 2 0 DC VGP 4 0 DC 0 0 PULSE (0 -6.0 VGN 5 0 PULSE (-. VID 3 6 DC Ml 3 5 2 .4 0 1 .5E-9 2E-9 .53E-9 2E-9 1E-10 2.5E-6 3.5E-6) 1E-10 2.5E-6 3.5E-6) 0 T280 L=80U W=80U NRS=. 1 T480 PS=192U L=B0U W=80U NRS=. 1 NRD= + M2 3 4 2 5.6 NRD= 1 AD=1280P AS=1280P PD=192U 1 AD=1280P AS=1280P PD=192U PS=192U + CI 6 0 50P Rl 6 0 75K MODEL +XJ=.5U T26 NMOS -MODEL +XJ=.5U T2B0 NMOS MJ=.5 RSH=48.92 CJ=1.77E-4 LEVEL=2 TPG=1 VT0=.604 MJ=.5 T0X=.0711U CGS0=2. 91E-10 CJSW=8. 85E-1 1 GAMMA=.2232 LAMBDA=. 00155 NSUB=4.008E14 +CGDO=2.91E-10 +LD=.2U VT0=.S3 LEVEL=2 U0=610 RSH=48.92 PB=.B71 CJ=1.77E-4 +CGDO=2.91E-10 +LD=.2U LAMBDA=.017S NSUB=4.008E14 MJSW=-3 NSS=4.758E11 U0=610 TPB=1 PB=.B71 T0X=.0711U CSSQ=2. 91E-10 CJSW=B. 85E-1 1 GAMMA=.2S09 MJSW=.3 NSS=4.983E11 + MODEL +XJ=.8U T46 LAMBDA=.0275 PMOS NSUB=3.7E16 +CGD0=4.85E-lO +LD=.6U LEVEL=2 RSH=2B5.6 CJ=.958E-5 VTO=- 1.070 U0=178 TPB=-1 FB=.719 MJ=.5 T0X=.0711U CBS0=4. B5E-10 CJSW=. 958E-1 1 GAMMA=.6645 MJSW=.3 NSS=1.291E11 + .MODEL T480 PMOS LAMBDA=. 00155 +XJ=.8U NSUB=3.7E16 RSH=285.6 U0=178 PB=.719 TPG=-1 +CGDO=4.B5E-10 CJ=.958E-5 MJ=.5 CJSW=. 95BE-1 1 +LD=.6U LEVEL=2 WIDTH VT0=-1.009 0UT=8O OPTION LIMPTS=1E6 TRAN 5E-11 3E-9 PLOT TRAN V(6) V(5) .END V(4) BAMMA=.7736 T0X=.0711U CGS0=4. 85E-10 MJ3W=.3 NSS=1.478E11 C 33 ####***06/21/86 ******** TRANSMISSION MOSFET SPICE 2G.5 (10AU6B1) ********10: 49: 58***** BATE WITH EK TRANSISTORS MODEL PARAMETERS TEMPERATURE Figure = 27.000 DEB C ##***************************************?*********?*?*******?*?*****#* T26 T2B0 NMOS TYPE NMOS T46 T480 PMOS PMOS LEVEL 2.000 2. OOO 2.000 2.000 VTO 0.530 0.604 -1.070 -1.009 B.65D-06 2. 96D-05 2. 96D-05 8.65D-06 GAMMA 0.223 0.251 0.665 0.774 PHI 0.529 0.529 0.763 0.763 1. 75D-02 1. 55D-03 2.75D-02 0.871 0.871 0.719 0.719 KP LAMBDA . PB , ~1 1 . 55D-03 CGSO 2. .91D-10 .91D-10 4.85D-10 4.85D-10 CGDO 2. 91D-10 2. 91D-10 4.B5D-10 4.B5D-10 48.920 48.920 2B5.600 285. 600 1. 77D-04 1. 77D-04 9.58D-06 9.58D-06 RSH CJ , 8. .85D-11 0.500 0.500 9.58D-12 9.58D-12 , 0.300 0.300 0.300 0.300 7. 11D-0B 7. 11D-0B 7. 11D-08 7. 11D-08 3.70D+16 3.70D+16 1.29D+11 1.48D+11 MJSW TOX 0.500 B. 85D-11 0.500 MJ CJSW , , . NSUB 4, 4, NSS 4. 4. 98D+11 .01D+14 .76D+11 .01D+14 , 1.000 l.OOO -1.000 -1.000 XJ 5. 00D-07 5, 00D-07 8.00D-O7 8.00D-07 LD o 00D-07 2, 00D-07 6.00D-07 6.00D-07 610. OOO 610.000 178.000 178.000 TPG UO . . , . 33 1******06/21/86 ******** SPICE 26. 5 (10AUB81) ********10: 49: 58***** TRANSMISSION BATE WITH EK TRANSISTORS INITIAL TRANSIENT SOLUTION Figure TEMPERATURE = 27.000 DEB 33 C *********************************************************************** NODE V0LTA6E NODE VOLTABE ( 1) O.OOOO < 2) 0.0000 ( 5) -0.4000 ( 6) 0.0000 VOLTAGE SOURCE ( O.OOOO 4) O. OOOO 230D-39 -2 VSRC -1.306D-39 . O.OOOD+OO VGP VGN O.OOOD+OO VID 9.240D-40 TOTAL POWER ******06/21/86 DISSIPATION ******** TRANSMISSION OPERATINB ID 3> VOLTABE CURRENTS VNWELL SPICE BATE POINT WITH Ml M2 T280 T480 O.OOD+OO O.OOD+OO 2G.5 EK O.OOD+OO VGS -0.400 0.000 VDS 0.000 O.OOO VBS 0.000 0.000 WATTS (10AUG81) ******** 10: 49:58***** Figure TRANSISTORS INFORMATION MOSFETS MDDEL ( NODE VOLTABE CURRENT NAME **** NODE TEMPERATURE = 27.000 DEG C 33 ,#**#**06/21/B6 ******** TRANSIENT SPICE 26.5 (10AU6B1) WITH EK TRANSISTORS ******** 1 O : 49 : 58***** GATE TRANSMISSION ANALYSIS Figure TEMPERATURE DEB 27.000 = 33 C LEGEND: : V(6) +: V(5) =: V(4) 000D-03 3-OOOD-03 2. OOOD+OO 4. OOOD+OO 6. OOOD+OO OOOD+OO O.OOOD+OO 2. OOOD+OO D3 O.OOOD+OO 1 DO O.OOOD+OO 00 -4. OOOD+OO . -2. 2 000D-03 . TIME = O.OOOD+OO 6.930D-35 + * -7.14BD-18 + * = 5.000D-H = t.OOOD-10 -1.75BD-17 . + * -3.029D-17 . + * = 1.500D-10 + * = + * = * = 2.000D-1O 2.500D-1O - -4.707D-17 -7.059D-17 . . 3.000D-1O -1.003D-16 + 3.500D-1O -1.356D-16 + * 4.000D-1O -1.766D-16 + * 4.500D-1O -2.231D-16 5.000D-10 -2.934D-16 - 5.500D-1O -B.617D-05 . 6.000D-1O -1.324D-04 6.50OD-1O -1.78BD-04 7.000D-10 -2.250D-04 7.500D-1O -2.713D-04 8.000D-1O -2.676D-04 B.500D-10 9.000D-10 -1.916D-04 2. 107D-04 + * + * . = _ +*. *+. * . * . + + . + * . + * + * . * = + . X + 9.50OD-1O 1.381D-03 . 1.000D-09 1 . 909D-03 . 1.050D-09 1 . 978D-03 . 1.100D-09 2.093D-03 . 1. 150D-09 2.057D-03 . + . + + _ + + 1.200D-09 1.250D-09 1.300D-09 1.350D-09 2. 07OD-O3 . 2.017D-03 . 2.013D-03 . 1.400D-09 1.450D-09 1.500D-09 1.919D-03 1.550D-09 1.600D-09 1.650D-09 1 . 970D-03 * . * *+ . . 878D-03 . 1 . B37D-03 . . 797D-03 . . 760D-03 . 725D-03 1.691D-03 L900D-09 1 1 . 659D-03 1 . 629D-03 * + * + . = 1.700D-O9 1.750D-09 1.800D-09 L850D-09 * + = . * + 1 1 * + * + . X . . *+ . * + = 1 * * * + _ 1 . . * X = 1 = * . 583D-03 . . 548D-03 . * = + 1.950D-09 1.518D-03 2.00OD-O9 1 2.550D-09 470D-03 448D-03 1-411D-03 1 3B3D-03 1 352D-03 1 328D-03 1.301D-03 1 275D-03 1 247D-03 1 225D-03 1 200D-03 1 876D-03 2.600D-O9 1 2.05OD-O9 2.100D-O9 2. 150D-09 2.200D-O9 2.250D-O9 2.300D-O9 2.350D-09 2.400D-Q9 2.450D-09 2.500D-09 1 * - * * - * . * . * . * . 2.80OD-O9 6. 151D-04 2.B50D-09 6. 128D-04 6. 121D-04 2.900D-09 . + * . 2.750D-O9 2.700D-O9 + * - 042D-03 7.326D-04 6.463D-04 6.220D-04 2.650D-09 * * . . 2.950D-09 6. 118D-04 3.000D-09 6. 117D-04 * + * + * * * * = JOB CONCLUDED JOB TIME TOTAL * 2.00 ******** ,******06/21/86 SPICE 26.5 TRANSMISSION BATE INPUT (10AUB81) ********! O: 52:25***** WITH EK TRANSISTORS LISTINB Figure TEMPERATURE = 27.000 DEB C ii****************************************,********^^*^*^*^^^^^^^^^^ FEEDTHROUBH ANALYSIS * C # S BELL ? VSRC 2 1 VNWELL -6.0 PULSE (-.4 0 VID 3 6 O O PULSE (O VGP 4 0 VGN 5 DC DC 2 0 DC Ml 3 5 2 0 5.6 . 5E-9 2E-9 . 54E-9 2E-9 O T280 L=80U W=80U NRS=. 1 W=80U PS=192U NRS=. 1 NRD=. 1 PS=192U + M2 3 4 2 1 T480 L=80U + CI 6 0 SOP Rl 6 0 75K MODEL +XJ=.5U T26 NMOS .MODEL +XJ=.5U T280 VT0=.53 NMOS MJ=.S RSH=48.92 CJ=1.77E-4 LEVEL=2 AD=1280P T0X=.0711U CGS0=2. 91E-10 CJSW=8. 85E-1 1 VT0=.604 MJ=.5 U0=610 TPG=1 PB=.871 MJSW=.3 T0X=.0711U CGS0=2. 9 IE- 10 CJSW=8. 85E-1 1 GAMMA=.2509 MJSW=.3 NSS=4.983E11 + .MODEL +XJ=.8U T46 PMOS LAMBDA=.0275 NSUB=3.7E16 +CGDO=4.85E-10 +LD=.6U LEVEL=2 RSH=285.6 CJ=.958E-5 VTO=- 1.070 U0=178 TPB=-1 PB=.719 MJ=.5 T0X=.0711U CGS0=4. 85E-10 CJSW=. 95BE-11 6AMMA=.6645 NSS= MJSW=.3 1.291 Ell + MODEL T480 PMOS LAMBDA=. 00155 U0=178 TPG=-1 T0X=.0711U +XJ=.BU NSUB=3.7E16 RSH=285.6 PB=.719 CBS0=4. 85E-10 +CGDO=4.85E-10 CJ=.958E-5 MJ=.5 CJSW=. 958E-1 1 +LD=.6U LEVEL=2 VT0=-1.009 WIDTH OUT=80 OPTION LIMPTS=1E6 TRAN 5E-11 3E-9 PLOT TRAN V<6> VMS) END V(4) BAMMA=.7736 PD=192U AD=1280P AS=1280P PD=192U TPB=1 PB=.B71 AS=1280P GAMMA=.2232 NSS=4.758E11 LAMBDA=. 00155 NSUB=4.00BE14 NRD=. 1 U0=610 RSH=48.92 CJ=1.77E-4 LEVEL=2 +CGDO=2.91E-10 +LD=.2U LAMBDA=.0175 NSUB=4.008E14 +CGDO=2.91E-10 +LD=.2U 1E-10 2.5E-6 3.5E-6) 1E-10 2.5E-6 3.5E-6) MJSW=.3 NSS=1.478E11 34 ft****06/21/86 ******** SPICE 26. 5 (10AU681) ********10:52:25**** TRANSMISSION BATE WITH EK TRANSISTORS MOSFET MODEL PARAMETERS TEMPERATURE Figure = 27.000 DEB C *******************************************#**-.--* T26 T280 NMOS TYPE NMOS T46 T480 PMOS PMOS LEVEL 2.000 2. OOO 2.000 2.000 VTO 0.530 0.604 -1.070 -1.009 2.96D-05 2.96D-05 8.65D-06 8.65D-06 GAMMA 0.223 0.251 0.665 0.774 PHI 0.529 0.529 0.763 0.763 KP 55D-03 2.75D-02 0.871 0.B71 0.719 0.719 CGSO 2.91D-10 2.91D-10 4.B5D-10 4.85D-10 CGDO 2.91D-10 2.91D-10 4.85D-10 4.85D-10 RSH 48.920 48.920 285.600 285.600 CJ 77D-04 77D-04 9.58D-06 9.58D-06 LAMBDA 1 . PB MJ Icjsw 1 . 75D-02 1 1 . . 1 . 55D-03 0.500 0.500 0.500 0.500 8.85D-11 8.85D-11 9.58D-12 9.58D-12 0.300 0.300 0.300 0.300 TOX 7.11D-08 7. 11D-08 7. 11D-08 7. 11D-08 NSUB 4.01D+14 4.01D+14 3.70D+16 3.70D+16 4.76D+11 4.98D+11 1.29D+11 1.48D+11 1.000 1.000 -1.000 -1.000 XJ 5.00D-07 5.00D-07 B.00D-07 8.00D-07 LD 2.00D-07 2.00D-07 6.00D-07 6.00D-07 610.000 610. OOO 178.000 178.000 MJSW NSS TPG uo 34 ******** *****06/21/B6 SPICE 26. 5 (10AU681) ********10: 52:25***** TRANSMISSION BATE WITH EK TRANSISTORS INITIAL TRANSIENT SOLUTION Figure TEMPERATURE = 27. OOO DEB 34 C ^****************************##**##**^^###^###^######^^###^##^##### NODE VOLTAGE NODE VOLTABE ( 1) 0.0000 ( 2) 0.0000 ( 5) -0.4000 ( 6) O.OOOO VOLTAGE SOURCE NODE ( 3) NODE VOLTABE O.OOOO ( 4) VOLTAGE O.OOOO CURRENTS CURRENT NAME VNWELL -2.230D-39 VSRC -1.306D-39 O.OOOD+OO VGP VGN O.OOOD+OO VID 9.240D-40 TOTAL POWER **#***06/21/86 DISSIPATION SPICE ******** TRANSMISSION OPERATING SATE WITH O.OOD+OO 2B.5 EK ******** 10: 52: 25***** Figure TRANSISTORS INFORMATION POINT WATTS (10AUG81) TEMPERATURE = 27.000 DEG C i********************************************************************** >*** MQSFETS MODEL ID Ml M2 T280 T4B0 O.OOD+OO O.OOD+OO VGS -0.400 0.000 VDS O.OOO O.OOO VBS 0.000 0.000 34 #*#****06/21/B6 ******** TRANSMISSION TRANSIENT SPICE 2G.5 BATE WITH EK (10AU681) ********10: 52: 25***** TRANSISTORS ANALYSIS Figure TEMPERATURE = 27.000 DEB 34 C *********************************************************************** LEGEND: *: V(6) +: V(5) =: V(4) (*) -l.OOOD-03 O.OOOD+OO 1 000D-03 2.000D-03 3-OOOD-03 (+) -2. OOOD+OO O.OOOD+OO 2. OOOD+OO 4. OOOD+OO 6. OOOD+OO (=) -6. OOOD+OO OOOD+OO O.OOOD+OO 2. OOOD+OO -4. OOOD+OO . -2. TIME O.OOOD+OO 6.930D-35 . + 5.000D-11 -7.14BD-18 . + * 1.000D-10 -1.758D-17 . + * * 1.500D-10 -3.029D-17 . + * 2.000D-10 -4.707D-17 . + * 2.500D-10 -7.059D-17 . + * 3.000D-10 -1.003D-16 . + * 3.50OD-1O -1.356D-16 . + * 4.000D-10 -1.766D-16 . + * 4.500D-10 -2.231D-16 . 5.000D-10 -2.934D-16 . 5.500D-10 -1.002D-04 . 6.000D-10 -1.464D-04 . 6.500D-10 -1.926D-04 . 7.000D-10 -2.389D-04 . * * -2.B51D-04 . -3.300D-04 . -2.648D-04 -6. * X 8.000D-10 9.000D-10 * * + 7.500D-10 B.500D-10 + + . 191D-04 . 9.500D-10 4.B06D-04 . 1.000D-09 1.024D-03 . 1.050D-09 1.165D-03 . +* X * = 1.100D-09 1.284D-03 . 1.150D-09 1.337D-03 . 1.200D-09 1.315D-03 . 1.250D-09 1.283D-03 . * * * 1 300D-09 1.240D-03 . 1.350D-09 1.400D-09 1.450D-09 1 500D-09 1.550D-09 1 600D-09 1 650D-09 1 700D-09 1.206D-03 . . . . . + . 1.188D-03 +* . 1. 186D-03 . 1. 139D-03 . 1.107D-03 . 1.091D-03 . 1.057D-03 . *+ . * . . 1.039D-03 * . 1.750D-09 . 1 800D-09 9.901D-04 . 1.850D-09 1.900D-09 9.626D-04 . 9.340D-04 . * . * . * . 1.008D-03 . * + * *. *. + * 1.950D-09 9. 167D-04 2.000D-09 8.901D-04 * 2.050D-09 8.735D-04 * 2. 100D-09 8.553D-04 * 2. 150D-09 8.295D-04 * 2.200D-09 B.060D-04 * 2.250D-09 7.908D-04 * 2.300D-09 7-728D-04 2.350D-09 7.496D-04 * * 2.400D-09 7.311D-04 * 2.450D-09 7.181D-04 * 2.500D-09 7.006D-04 * 2.550D-O9 2.073D-03 2.600D-09 1 2.650D-09 1. 128D-03 . 423D-03 2.700D-09 1.016D-03 * 2.750D-09 9.B51D-04 * 2.800D-09 9.768D-04 * 2.850D-09 9.747D-04 2. 900D-09 9.742D-04 * 2.950D-09 9.739D-04 * 3. 00OD-O9 9.737D-04 * JOB CONCLUDED TOTAL JOB TIME 1.76 ******** ******06/21/86. SPICE 2G. 5 (10AUG81) ********10: 54: 40***** TRANSMISSION BATE WITH EK TRANSISTORS INPUT LISTING Figure TEMPERATURE = 27.000 DEG C *****************************************#*#####^#^<####^#####^^^#^#> FEEDTHROUGH ANALYSIS * C * S BELL * WWELL 1 2 2 0 DC VSRC DC O 0 VGP 4 0 PULSE (0 VGN 5 0 PULSE (-.4 VID 3 6 DC Ml 3 2 5 0 -6.0 . 5.6 . 5E-9 2E-9 IE-ID 2. 5E-6 3 5E-6) 55E-9 2E-9 IE- 2.5E-6 3 5E-6) 10 0 T280 L=80U W=80U + NRS=. 1 NRD=. 1 AD=1280P AS=1280P PD=192U NRD=. 1 AD=1280P AS=1280P PD=192U PS=192U M2 3 2 4 1 T480 L=80U W=80U + NRS=. 1 PS=192U CI 6 0 SOP Rl 6 0 75K T26 .MODEL NMOS LAMBDA=.017S U0=610 TPG=1 T0X=.0711U RSH=4S.92 PB=.871 CGS0=2. 91E-10 CJ=1.77E-4 MJ=.5 CJSW=8. 85E-1 1 MJSW=.3 NSUB=4.008E14 +XJ=.5U +CGD0=2.91E-10 LEVEL=2 +LD=.2U T280 .MODEL VT0=.53 NMOS LAMBDA=. 00155 NSUB=4. 008E14 +XJ=.5U RSH=48.92 CJ=1.77E-4 +CGD0=2.91E-10 LEVEL=2 +LD=.2U BAMMA=.2232 VT0=.604 MJ=. 5 NSS=4.758E11 U0=610 TPG=1 PB=.871 T0X=.0711U CSS0=2. 91E-10 CJSW=8. 85E-1 1 GAMMA=. 2509 MJSW=.3 NSS=4.9S3E11 + T46 .MODEL PMOS LAMBDA=.027S NSUB=3.7E16 +XJ=.8U CJ=.958E-5 +CGDO=4.85E-10 +LD=.6U RSH=285.6 LEVEL=2 VTO=- 1.070 U0=178 TP6=-1 PB=.719 MJ=.5 T0X=.0711U CSS0=4. 85E-10 CJSW=. 958E-1 1 BAMMA=.6645 MJSW=.3 NSS=1.291E11 + T480 .MODEL +XJ=.8U PMOS +CGD0=4.85E-10 +LD=.6U VT0=-1.009 0UT=80 OPTION LIMPTS=1E6 .TRAN 5E-1 1 .PLOT TRAN END RSH=235.6 CJ=.95eE-5 LEVEL=2 .WIDTH . LAMBDA=. 00155 NSUB=3.7E16 3E-9 V(6) V(5) V(4) U0=178 PB=.719 MJ=.5 TPB=-1 CJSW=. 958E-1 1 BAMMA=.7736 TOX=.0711U CGS0=4. 85E-10 MJSW=.3 NSS=1.478E11 35 *****06/21/86. GATE TRANSMISSION MODEL MOSFET WITH 2 VTO 0. 530 0. 604 T46 !2 000 . 96D-05 . ********10: 2 T480 PMOS 000 . 1 - 2 070 . 8. 65D-06 - 000 . 1 0(59 . 8. 65D-06 GAMMA 0. 223 0 25 1 0.665 0.774 PHI 0.529 0. 529 0.763 0. 763 1. 75D-02 i. 55D-03 75D-02 1. 55D-03 LAMBDA 0 10 f-y CGDO 91D-10 *"? RSH 48 r\ CBSO 9 1 , D- o , , 0.871 PB . 91 , D- 10 , 0.719 0.719 87 1 . 4, S5D, 10 4, 85D-10 . 91D-10 4. 85D-10 4, 85D-10 920 48.920 285.600 285.600 CJ 1. 77D-04 1, 77D-04 p. 58D-06 9. 58D-06 MJ 0. 500 5(1)0 0. 500 r~\ CJSW 8. ,850-11 7 TOX NSS . 4 4 11D-08 .010+14 . . 0 XJ 5 LD 2 . . . . OOD-07 . S10. 000 , 9, ,580-12 0 0. 300 7 . 11D-08 r .010+14 . 98D+11 1 cr . i . \ . 1 OOD-07 6 610. 000 0. 500 9, ,580-12 0. 300 300 . 70D+16 3 29D+11 i . - 8 , 7 000 OOD-07 . , i i D-oe . T 4 000 00D-07 . 8, 85D-11 76D+11 1 TPG UO , 0. 300 MJSW NSUB . . . 54: 40***** Figure TRANSISTORS PMOS 2. 000 96D-05 (10AUG81) TEMPERATURE NMDS LEVEL KP EK T280 T26 *-J 2G.5 PARAMETERS NMOS TYPE SPICE ******** 1 . 11D-08 . . 70D+16 . 48D+11 . OOD-07 000 -1 OOD-07 8 OOD-07 6 178. 000 . . 000 OOD-07 178. 000 = 27.000 DEG C 35 ******06/21/86. ******** SPICE 2G.5 (10AUG81) ********10: 54: 40***** TRANSMISSION GATE WITH EK TRANSISTORS INITIAL TRANSIENT SOLUTION Figure TEMPERATURE = 27.000 DEG 35 C t****************************************#*******####^^^######## NODE VOLTAGE NODE VOLTAGE ( 1) 0.0000 ( 2) 0.0000 ( 5) -0.4000 ( 6) 0.0000 VOLTAGE SOURCE NODE ( 3) VOLTAGE 0.0000 NODE ( 4) VOLTAGE 0.0000 CURRENTS CURRENT NAME VNWELL -2. VSRC -1.306D-39 230D-39 0. OOOD+OO V6P VGN 0. OOOD+OO VID 9. 240D-40 TOTAL POWER DISSIPATION ******** *******06/21/B6 TRANSMISSION OPERATING SPICE GATE POINT WITH O.OOD+00 2G.5 EK WATTS (10AUG81) ********10: 54: 40***** TRANSISTORS INFORMATION TEMPERATURE Figure = 27.000 DEG C j-*********************************************************************-* **** MODEL ID VGS MOSFETS Ml M2 T280 T480 O.OOD+OO -O . 400 O.OOD+OO O . 000 VDS 0.000 0.000 VBS 0 0 . 000 . 000 35 ******** #******06/21/86. TRANSMISSION TRANSIENT SPICE GATE 2G.5 (10AUG81) EK TRANSISTORS WITH ********10: TEMPERATURE ANALYSIS 54: Figure 40***** 35 27.000 = DEG C LEGEND: *: V(6) + : V(5) = V(4) : oood-o; 0 OOOD+OO 1.000D-03 2.000D-03 . OOOD+OO 2. OOOD+OO 4.00 0 D + 0 0 6 OO0D+0O 2 -2. 000D-03 (+) -2. OOOD+OO 0 (=) -6 00 0D+ OO -4. . - 1 . (*) OOOD+OO 6.930D- 35 5.000D-1 1 148D- 18 + 17 + 1 . 10 1.500D-10 OOOD- 2. 10 2. 500D-10 OOOD- 3. 10 3.500D-10 OOOD- 4. -2. O OOOD+OO . V(6) TIME O.OOOD+OO OOOD- . 10 4.50OD-1O -7. -1.758D- -3.029D- -4.707D- -7.059D- -1 003D. + 17 + 17 + 17 + 16 + * * * * 16 * 16 * -1.356D- -1.766D- 16 -2.231D- - OOOD- 5. 10 5.500D-10 6. OOOD- 10 6.500D-1O 16 -2.934D- -1. - 1 122D- -04 603D- * 04 . 04 -2.064D- -s- 7. OOOD- 10 7.500D-10 OOOD- 8. 10 8.500D-10 9. OOOD- 10 9.50OD-1O 1 1 OOOD -09 . 050D-09 . 1. 100D-09 1. 150D-09 1 1 1 1 200D-09 . 250D-09 . 300D-09 . . 350D-09 1. 400D-09 1.450D-09 1 500D-09 . 1.550D-09 1 1 1 -2. -3. -03 156D- 1.431D- . 900D-09 -04 3.975D- -04 5. 101D- * + + + -04 5.868D- -04 6. 146D- -04 X 6.348D- -04 5.940D- = * + -04 5.630D- -04 * 5.320D- -04 5.093D- * -04 * 4.879D- -04 4.578D- 4. . -04 -4. 4. 850D-09 04 -1.484D- 650D-09 800 D -09 -04 455D- -04 600D-09 . 990D- -3.295D- . 1.750D-09 1 04 . 1. 700D-09 1 -2.529D- 3. 351D- +* -04 X 190D- -04 920D- * -04 * 3.531D- -04 3.353D- -04 126D- + -04 * 3.689D- 3. * + -04 -04 + . . OO0D+O0 00OD+00 1.950D-09 2.948D-04 * 2.000D-09 2.79BD-04 * 2.050D-09 651Q :>4 2. 100D-09 467D J4 306D- 04 * 209D- 04 * 059D- :>4 * 902D- J4 2. 150D-09 , 2. 200D-09 2.250D-09 , 2.300D-09 )4 * 04 * 2.350D-09 689D 2. 400D-09 2.450D-09 * .548D 04 * 430D 04 * 2. 500D-09 1 2.550D-09 1.919D- D3 2. 600D-09 1, 780D- )3 2.650D-09 1 481D- 2. 700D-09 1. 369D- * * + :.9D- * + . 2.750D-09 1. 2. 800D-09 1. 2.850D-09 1. 2. 900D-09 1. 2.950D-09 1. r.5D- 3.000D-09 1. i5D- JOB +* y * 6D- ,5D- CONCLUDED TOTAL JOB TIME -7C + + * + * +

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