Download MDT-ASD: LVDS properties

MDT-ASD: Additional PDR Issues
IC design review issues as stated in the document “Preliminary List of Criteria for IC Design Reviews” (ATLAS
Front-End Electronics Coordination).
1.
Specification of required performance and functionality
A brief set of specifications for the integrated circuit should be presented. If the initial specifications for the IC were not
fully met, but the performance of the circuit is considered acceptable, the specifications should be updated. Detailed
specifications of the digital performance including such items as command protocols, data output format, error flagging,
error recovery, power up initialization, resets, recovery from lack of synchronization, etc. should be specified.
Control data interface, programmability, Wilkinson ADC in “MDT-ASD: Serial data I/O and programmable
parameters”.
General functionality and specs, analog chain, biasing etc.: to be added (J. O.)
LVDS output drivers in “MDT-ASD: LVDS driver properties”
2.
Description of circuit, block schematic, simplified schematics of critical subcircuits
A reasonably complete and accurate block diagram is very important in enabling a reviewer to understand the design
methodology and verification strategy, and to spot potential problems. Simplified schematics of critical subcircuits, such
as preamplifiers, receivers & drivers, delay-locked loops, DAC’s, etc are likely to be useful.
Some in “MDT-ASD: Amplifier Simulations and Measurements”, additional documentation to be added (J. O.)
3.
Pin-out diagram and brief description of interfaces to other systems
Control data serial interface in “MDT-ASD: Serial data I/O and programmable parameters”,
LVDS driver output specifications in “MDT-ASD: LVDS driver properties”
MDT tube to pre-amplifier input specifications: to be added (J. O.)
Pin-out diagram to be added after packaging is sorted.
4.
Tools used for layout and simulation of each block
Layout:
 Analog blocks: MAGIC (Version?)
 Digital blocks, mixed signal blocks: Tanner L-Edit 8.03, CADENCE Virtuoso Layout Editor (icfb.exe
Version 4.4.2)
 Chip assembly: Tanner L-Edit 8.03
Simulation:
 MicroSim PSPICE 8.0, AVANT Star-HSPICE 98.2.1
5.
Basis of transistor models or standard cells
MOSIS Parametric tests from recent runs.
Model type: SPICE BSIM3 VERSION 3.1, SPICE 3f5 Level 8, Star-HSPICE Level 49
6.
Design Verification Procedure
Complete verification of a chip should typically consist of the following:

SPICE simulation

Protoyping (optional but recommended for high performance sections)

Transistor Model verification

Simulation with best/worst case parameters

Special attention to any required matching of Vbe, beta, Vt

Evaluation of PSRR and dependence on supply voltage

Have the correct I/O pads been used? Have bond wires been included in the simulation?

Has all functionality been simulated at the chip level rather than just at the channel level?
Layout versus Schematic (LVS) and Design Rule Checking (DRC)
2
DRC (Design Rule Check): Rule set SCMOS_SUBM (MOSIS) checked in MAGIC and/or Tanner L-Edit
LVS (Layout vs. Schematics): Tanner LVS 3.01, CADENCE LVS (icfb.exe Version 4.4.2)
Each sub-cell passes individual checking before assembly. Full final layout (incl. pads and ESD) passes checking
before and after stream-out (GDSII)
7.
Summary of tests performed on prototypes
Have critical sections of the circuit been protoyped?
Has it been shown via measurement that all performance specifications are met? If not, have exceptions to the original
specifications been circulated to the relevant people in the subsytem?
Have a large enough sample of chips been tested (many tens) to verify spread in the performance?
In “MDT-ASD: Serial data I/O and programmable parameters”, “MDT-ASD: LVDS driver properties”, “MDTASD: Amplifier Simulations and Measurements”.
Additional results on analog chain to be added (J. O.)
Results on ASD00A will be added as available.
8.
Design techniques utilized to ensure high reliability
Was any attention paid to minimizing impact of single point failures?
Were any techniques used to enhance reliability (multiple vias, wider than nominal widths, clearances, etc.)?
Is there data on chip lifetime from the manufacturer?
Has the process been used in a similar way for other circuits?
How has a package or other sealant been selected? Is it known what impact this may have on chip lifetime?
Is an adequate number of power supply and ground pins utilized?
To be added.
9.
System Test and Testability
If chips have been fabricated, have they been tested only on the bench or in a larger system?
Has testability been considered in the design?
What are the plans for production testing?
To be added:
On-chamber test results
Testability: Probe pads, analog outputs, DAC voltages on output pads, download – shift-out of shadow register
contents.
Production testing?
10. Radiation environment
Results from previous irradiation tests on process/ASD prototypes (Werner, UPENN?)
X-ray irradiation at CERN
Neutron irradiation (necessary?)
11. From TPC-ASD PRR document: Detector signal characteristics and modelling