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4. Logic Gates
p
n+
E1
B
n+
p
n+
n+
A
A
E3
E2
All gates with inverter at output are not fast. The reason is
large input capacitance of all loading gates (the sum of input
capacitances of each loading gate) that makes large time constant
with resistance RC. Totem-pole output stage with two transistors
in series solves the problem; these transistors are fed by inversed
signals.
n
Basic TTL gate
K
AA
E1
n
B
n+
p
p
n+
p
The basic gate is made up from multiemitter input transistor
VT1, transistor VT2, which provides complemented control
signals for totem-pole output stage transistors VT3 and VT4.
When VT2 is OFF, high level on its collector opens VT3 and low
+ EC
R4
R2
VT3
R1
VT1
A
B
C
d
i
h
VT2
VD
e
VT4
g
j
F= ABC
k
Rload
Cload
R3
level on VT2 emitter takes VT4 into OFF state, and it means high level in the output of the
gate. When VT2 is ON, VT4 is ON, and VT3 is OFF, the output level of the gate is low.
Normally only one totem-pole output stage transistor is ON at the same time, but we know, that
one transistor opens without delay while closing process of another transistor is longer. Resistor
R4 restricts the current when one transistor is already ON,
Point in
Voltage of
and another transistor is still ON. Diode VD guarantees the
the circuit
the point
closing of VT3 when it must to be closed, we will see it,
A
+ 0,2 V
when we will write the potentials of all points of the gate
d
+ 0,9 V
circuit.
e
+ 0,4 V
Now we will analyse an operation of the gate in
g
0
details. Let low level 0.2 V is in one input of the gate at
h
+EK
least, let it be the input A. The corresponding junction BE is
j
EK – 0,7 V
ON, and voltage drop on the saturated junction is 0.7 V. It
kF
EK – 1,4 V
means that potential of the point d is + 0.9 V. Voltage drop
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4. Logic Gates
on the saturated VT1 is 0.2 V, it means that potential of the point e is + 0.4 V. Voltage of 0.5 V
on VT1 BC junction testifies that VT1 is saturated. On the other hand, state of VT1 is specific –
its collector current IC  0, because VT2 is OFF: 0.4 V is too small voltage to open two BE
junctions of VT2 and VT4, connected in series. The resistance of the closed BE junction of
VT2 rBEOFF  R3, therefore Ug  0. VT2 is closed, and current trough R2 is only a small base
current of VT3. The potential of the point h approximately equals Ec. Such base potential
saturates VT3, therefore Uj  Uh – 0.7 V  Ec – 0.7 V. Diode VD is ON. It means that an output
voltage of TTL gate Uk  Uj – 0.7 V  Ec – 1.4 V. It is quite important conclusion: high level in
the output of the standard TTL gate is Ec – 1.4 V. When Ec  5 V, U1TTL  3.6 V.
Now let us say that high levels are in all inputs of the
Point in
Voltage of
gate: UA  UB  UC  U1TTL  3.6 V. All input junctions are
the circuit
the point
OFF, and it means that voltage of the point d is such, that it
A, B, C
+ 3.6 V
opens three PN junctions connected in series: BC junction of
d
+ 2.1 V
VT1, BE junction of VT2, and BE junction of VT4. The
e
+ 1.4 V
voltage drops on the saturated VT2 and saturated VT4 are 0.2
g
+ 0.7 V
V each, so Uk  0.2 V and Uh  Ug + 0.2 V  0.9 V. When
h
0.9 V
VT4 is ON, VT3 must to be OFF. Voltage Uh – Uk  0.9 –
j
0.2 V
0.2  0.7 V is too small to forward bias two PN junctions,
kF
0.2 V
connected in series: BE junction of VT3 and junction of VD.
Voltage drop on each reverse biased junction is only 0.35 V. Now we can see that without
diode VD transistor VT3 would be ON when it must be OFF.
We will calculate one important parameter of the gate – input current, when input level is
high. In this case BE junction of VT1 is OFF and it's BC junction is ON – it is a reversed state
of transistor. In reversed state of transistor iE  inviB like iK  iB in a linear transistor state,
when it's BE junction is forward biased and BC junction is reversed biased. The circuit of the
gate and the table of voltages gives UR1  Ec – Ud  5 – 2.1  2.9 V and iB  UR1 /R1. Let
R1  4 k. Then iB  2.9 /4  0.725 mA. Let inv  0.2. Then iIN  iE  0.2 0.725  0.15 mA.
This current is very large in comparison with an input current of DTL gate, when a high level in
input cuts off the gate's input diode.
Now we will calculate pyramiding factor of the TTL gate: the quantity of loading gates
that can be connected to the output of one TTL gate. This factor is ratio of the highest possible
output current of the gate, when there is a high level in the output, with input current of the
gate, when there is a high level in the input. According to the first table of voltages Uh  Ec . It
means that UR3  UBC. Voltage UBC of saturated transistor is 0.5 V. Let R3  0.15 k. Then the
highest possible output current iOUT max  UR3 /R3  0.5 /0.15  3.3 mA. The pyramiding factor
of the gate iOUT max /iIN  3.3 /0.15  20.
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4. Logic Gates
Schottky TTL
It is standard TTL in which all transistors are Schottky transistors. Schottky transistors can not
be saturated, therefore they have short closing time.
VT
E
B
C
VDS
n+
VTS
VT

Schottky TTL is faster than standard TTL.
A voltage drop on the open but not saturated transistor
is greater than a voltage drop on the saturated
transistor: U0TTLS  U0TTL . It means that interference
immunity of TTLS is less than interference immunity
of standard TTL.
n+
p
n
p
p
V TS
C
n+
n
E
n+
B
p
p
p
4.1.4. Modern DCTL Gates
ECL
Emitter-coupled logic is the family designed for extremely high-speed applications. It is well
suited for large mainframe computer systems that require a high number of operations per
second but that are not as concerned about an increase in power dissipation. The high speed of
ECL is achieved by never letting the transistors to saturate: this function performs common
resistor in emitter circuit.
The main part of the circuit is DCTL NOR gate: transistors VT1, VT2 and VT3 with
common collector load R1. The output signal of NOR gate is repeated by emitter-follower
(current amplifier) VT5 with load R4.
+ EC
+E – base voltage of transistor VT4 –
V T6
R3
R1
is such, that voltage drop on resistor
V T5
R2 closes VT4 if current of one
transistor VT1, VT2 or VT3 at least
V T1
V T2
V T3
V T4
F1= A + B+ C flows through resistor R2. VT4 is ON
if VT1, and VT2, and VT3 are OFF.
C
A
+E
B
Exceptional combination of 0s in all
R4
F2= A + B+ C
inputs corresponds with 0 in output of
R5
R2
emitter follower VT6 – it means that
logic operation 3OR is realized in this
output.
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