Download A Study of CMOS Current Comparators in 180 nm Technology

International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 5, May 2014
A Study of CMOS Current Comparators in
180 nm Technology
Adyasha Rath, Sweta Padma Dash, Subhrajyoti Das, Adyasa Samantaray, Geeta Pattnaik
Abstract— In this paper a comparative analysis of different
current comparator topologies is carried out in 180 nm CMOS
process technology at a supply voltage of 1.8V. Current
comparators are extensively used in ADC’s. The different
comparators are compared in terms of parameters like delay,
power dissipation and number of transistors used. Simulations
of the current comparators were done in Cadence using the
Spectre simulator.
Index Terms—ADC, current comparator, delay, power
dissipation.
I. INTRODUCTION
Comparators form the fundamental component of a myriad
type of analog systems including data convertors and other
front-end signal processing applications. With the ever
increasing need for shrinking the feature size of devices and
the quest for high speed, designers are considering currentmode implementations. The striking features of currentmode approaches such as high speed, large bandwidth and
reduced supply voltages etc. have made analog designers to
take more interest in designing current-mode circuits.
However, high performance current-mode comparators have
not been frequently published, and only a few structures
exist.
The demand for high speed and low power applications
makes the CMOS devices to be scaled down. Current-mode
operation is considered as an alternative in analog circuit
designs in order to get high speed and low power
consumption. In earlier days voltage comparators were very
common and most popular ones. However, the voltage
comparator suffered from certain drawbacks that include
reduced operational frequency, power consumption and
input offset voltage. Current comparison is done by
impressing the current pulse signal at the input of the
comparator and finding whether it is positive or negative.
The output voltage generated by the comparator is used
conveniently to indicate the result of operation.
The current mode approach enables low power and high
speed analog circuit designs effectively. Some
implementations of the current comparators can be seen in
[1] – [3]. Moreover, many signal sources in temperature
sensors, photo-sensors, etc., provide current signals and
current Schmitt Triggers have often been designed to detect
them. Other applications include current-mode circuits such
as A/D converters, oscillators, current to frequency
converters, neural networks, etc. the current comparator is a
fundamental building block.
II. CURRENT COMPARATOR
A current comparator determines if a current signal exceeds
a given threshold and produces an output voltage. A currentmode comparator receives an input signal in the form of a
current and compares it to a pre-defined threshold current.
The output is in the form of a voltage. Current sensing
comparison has many different applications including the
nonlinear current-mode signal processing and A/D
converters. Detection of low current at is an important
consideration for high speed applications. In applications
requiring high resolution such as in the current-mode image
compression chip the most important building block will be
the current comparator.
III. STUDY OF DIFFERENT CURRENT
COMPARATORS
In this section different current comparator topologies are
studied and simulated in Cadence using 180 nm CMOS
process technology.
A. TRAFF’s CURRENT COMPARATOR[4]
The current comparator reported in [4] proposed by H.Traff
in 1992 is perhaps the first current comparator which
possesses lower input impedance than previous circuits. In
the circuit shown in Fig. 1, M1 and M2 form a class B
voltage buffer; and M3- M6 form two inverting amplifiers.
Iin is the input current, which is the difference between the
signal and the reference currents.
Fig. 1 Traff‟s Current Comparator Schematic in 180 nm
ISSN: 2278 – 7798
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International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 5, May 2014
The circuit has three modes of operation. When Iin is
positive, V1 is pulled high. This is amplified by M3 and M4,
causing V2 to go low. VGS1 and VGS2 are negative, turning
M1 off and M2 on. In this state, V1 is a low impedance
node, because Iin is supplied by M2. When Iin changes its
sign, there is insufficient gate drive for the buffer to supply
Iin, thus V1 is temporarily a high impedance node. When Iin
is negative, V1 is pulled low and V2 is pulled high, turning
M1 off and M2 on; again V1 is a low impedance node.
complementary amplifier. The small input and output
resistances can reduce the voltage swings at node 1 and 2,
so the response time of the comparator will be greatly
decreased.
The transient response results of the Traff‟s current
comparator are as shown in Fig. 2.
Fig. 4 Chen‟s Comparator schematic in 180 nm
The transient response of the Chen‟s current comparator is
shown in Fig. 5. The delay and average power consumption
was found to be 10.1ns & 307 µW respectively. The layout
of the Chen‟s comparator is shown in Fig. 6.
Fig. 2 Transient Response of Traff‟s Current Comparator
The delay and average power consumption of the circuit was
found to be6.354ns & 178.2 µW respectively. The layout of
the Traff‟s comparator is shown in Fig. 3.
Fig. 5 Transient Response of Chen‟s Comparator
Fig. 3 Layout of Traff‟s comparator in 180nm technology
B. CHEN’s CURRENT COMPARATOR[5]
A continuous-time current comparator was proposed by
Chen as shown in Fig. 4 of [6] .It comprises of one CMOS
complementary amplifier (M1–M2), two resistive-load
amplifiers (M6–M9) and a CMOS inverters (M10–M11).
M1 and M2 both work in saturation region, M3 and M4 are
used to decrease the working current. The transistor M5 acts
as the negative feedback resistor of the CMOS
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Fig. 6 Layout of Chen‟s comparator in 180nm technology
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International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 5, May 2014
C.
CURRENT COMPARATOR IN [6]
The current comparators in [4] and [5] have neglected the
current subtraction stage and have taken input current
difference as the input to the comparator. The inclusion of
subtraction circuit accounts for additional power and
increases the time delay. Fig. 6 shows the current
comparator with the added current difference stage. The
input currents Iin and Iref are mirrored using identical
current mirrors into the transistor pair Mc3-Mc6. The
current difference ( Idiff) equal to the difference between Iin
and Iref. is hence generated from this stage which is given as
input to the next stage for further comparator operation. The
gain stage consists of cascade of two resistive amplifiers
(Mr1-Mr4) and the CMOS inverter (M1-M2) within the
feedback loop with output stage consisting of CMOS
inverter (M3-M4).
Fig. 9 Layout of conventional comparator [6] in 180nm
technology
In Table I a comparative analysis of the three current
comparators is done. It is found that the current comparator
in [6] exhibits the least delay at an average power
consumption of 676 µW. The delay of Traff‟s comparator
and Chen‟s comparator are found to be 6.354ns and 10.1ns
respectively.
Table I. Performance Comparison Summary of the Current
Comparators
Traff’s CC
Fig. 7 Current Comparator [6] schematic in 180 nm
When difference current Idiff is sensed at node „1‟, it is
converted into equivalent output voltage at node „2‟ by
the transimpedance gain stage which then converts the
corresponding voltage to a into full swing output voltage
using the output CMOS inverter (M3-M4).
The transient response of the current comparator in [6] is
shown in Fig. 8. The delay and average power consumption
was found to be 1.49ns & 67 µW respectively. The layout of
the comparator is shown in Fig. 9.
Power
Supply(V)
Technology
Minimum
Input Current
1.8
Chen’s
CC
1.8
CC in [6]
180nm
180nm
180nm
100nA
100nA
100nA
Delay
Power
Consumption
PDP
6.354ns
178.26 µW
10.1ns
307µW
1.49ns
676µW
1.13pJ
3.05pJ
1.007pJ
1.8
IV. CONCLUSION
In this work a comparative analysis of three types of current
comparator is done in 180 nm technology. The comparators
in [4] and [5] without inclusion of a current difference stage
exhibit a higher PDP (Power Delay Product) of 1.13pJ and
3.05pJ respectively. The current comparator in [6] exhibited
a least PDP of 1.007pJ at a current difference of 0.1µA than
the other two topologies with the inclusion of a current
difference stage.
REFERENCES
Fig. 8 Transient Response of Current Comparator in [6].
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[1] G.Palmisano and S.Pennisi, “Dynamic Biasing for True Low-Voltage
CMOS Class AB Current-Mode Circuits”, IEEE Transctions on
Circuits and Systems-II: Analog and Digital Signal Processing, Pages.15691575, Vol.47, Dec- 2000.
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International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 5, May 2014
[2] Chung-Yu Wu, Chih-cheng chen, Ming-Kai Tsai and Chih-Che Cho,
“A 0.5uA Offset-Free Current Comparator For High Precision CurrentMode Signal Processing”, IEEE Proceedings – Circuits and Systems,
Pages. 1829-1832, Vol.3, 1991.
[3] Byung-moo Min and Soo-won Kim, “High performance CMOS current
comparator using resistive feedback network ”, IEEE Proceedings Electronic Letters, Pages. 2074-2076, vol.34, Issue.22, 1998.
[4] H. Traff, "Novel Approach to High Speed CMOS Current
Comparators", IEEE Proceedings - Electronic Letters, vol.28, No.3, 1992.
[5] Lu Chen, Bingxue Shi, and Chun Lu, “ A High Speed/Power Ratio
Continuous-Time CMOS Current Comparator ”, IEEE Proceedings –
Electronics, Circuits and Systems, ICECS-2000, Pages. 883-886, Vol.2,
Dec- 2000.
[6] Sridhar, R. ; Pandey, N. ; Bhatia, V. ; Bhattacharyya, A.,
"On
Improving the performance of Traff‟s Comparator" , 2012 IEEE 5th India
International Conference on Power Electronics (IICPE),2012.
[7] D. A. Johns and K. Martin, Analog integrated circuit design. John
Wiley & Sons, 1997.
[8] R. J. Baker, CMOS: Circuit design, layout and simulation, 2nd ed. John
Wiley & Sons, 2007.
[9]B. Razavi, Design of analog CMOS integrated circuits. India: Tata
McGraw Hill, 2002.
Ms. Adyasha Rath. She is presently
pursuing
her
M.Tech
with
specialization in VLSI & Embedded
Systems under KIIT University. She
has received her B.Tech degree from
Biju
Pattnaik
University
of
Technology
in
Electronics
&
Communication Engineering in the
year 2012. Her areas of interest
include low power, high speed analog
and mixed mode circuit design.
Ms. Adyasa Samantaray She has
received her B.Tech degree from Biju
Pattnaik University of Technology in
the year 2009 in Applied Electronics
& Instrumentation Engineering. She is
presently pursuing her M.Tech at KIIT
University with specialization in VLSI
& Embedded System. Her areas of
interest include high speed, low power
digital and analog design.
Ms. Geeta Pattnaik She is currently
pursuing M-TECH in VLSI and
Embedded system at KIIT University ,
Odisha.. She had completed her
B.Tech from Seemanta Engineering
College affiliated to Biju Pattnaik
University and Technology in the year
2011 in the stream of Electronics &
Telecommunication. Her area of
interest is low power analog circuits
design.
Ms. Sweta Padma Dash. She is
currently pursuing Master in VLSI and
Embedded system at KIIT University ,
Odisha. She had completed B.Tech
from Modern Institute of Technology
and Management, affiliated to Biju
pattnaik University and Technology in
the year 2012. Her areas of interest
include analog and mixed signal ICs.
Ms. Subhrajyoti Das. She received
her B.Tech Degree in Electronics &
Telecommunication Engineering from
Mahavir Institute of Engineering &
Technology(M.I.E.T)
College,
Bhubaneswar under Biju Patnaik
University & Technology, Odisha in
the year 2011.She is presently
pursuing her M.Tech in VLSI design
& Embedded System at KIIT
University, Bhubaneswar, Odisha.
Her areas of research focus on design
of low power, high speed analog
circuits.
ISSN: 2278 – 7798
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