Download SRAM Cell and Column IO Design

EECE481
3/16/2005
Lecture 18
SRAM Cell and Column I/O Design
Res Saleh
Dept. of ECE
University of British Columbia
[email protected]
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EECE481 Lecture 18
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Architecture of 64Kb SRAM
2m =256
Row decoder
Column Pullups
word line
bitline
2n
=256
n=8
Address input
2m
Column Mux
m=8
Column decoder
Read/Write
Sense en
Write en
Sense amplifier
Read-write control
Write driver
Data In
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EECE481 Lecture 18
Data Out
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SRAM Storage Cell
Uses six transistors (called 6T memory cell):
wordline
inverter 1
a
2
Single Stage
Noise Margin
1
a
inverter 2
a
Bitline
VOL VS
Bitline
VOH
a
Read and write operations use the same port. There is one wordline
and two bit lines. The bit lines carry complementary data, a fact that
will be used to reduce access time. The cell layout is small since it has
a small number of wires (but large relative to DRAM).
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CMOS SRAM Cell Design
Vdd
b
b
wp
wp
wa
wa
a
a
wd
Problem: Find wa, wd, wp such that
1) minimize cell area
2) obtain good read and write cell margins
3) good soft error immunity
4) good cell read current
wd
wl
in that order
Vdd
Vdd
wp
a
Since the cell is symmetric
we need only design three
transistor sizes
wa
a
wd
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Cell Design
Vdd
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CMOS SRAM cell design - read
•
•
Make sure that internal node a does not go high enough to turn on M2
Use threshold voltage as a maximum allowable voltage at internal node
during read; Make current ratio between M1 and M3 about 3 to 4
Want to design device sizes such that read current is high enough to
create desired differential voltage on bit lines ~200mV within a specified
amount of time
•
Icell =
Vdd
b
Icell
Cbit ∆V
b
M5
τ
wl
M6
M3
trigger
b,b
M4
(=0)
a
(1=) a
a
Cbit
Cbit
M1
M2
τ
a
wl
Rule-of-Thumb: W1/W3 = 1-1.5
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CMOS SRAM cell design - write
•
Need to make sure M4 is strong enough to pull internal node a low
while M6 is trying to pull it high
Use switching threshold as trigger point for regenerative switch point;
usually want to make it less than the switching threshold
This will force inverter M5-M1 switch to new state
Make ratio of currents between M4 and M6 about 3 to 4
•
•
•
Vdd
Vdd
M5
b
M6
a
M1
Vdd
wl
b
M4
M3
( = 0)
b
(1=) a
a
M2
b
a
~Gnd
Rule-of-Thumb: W4/W6 = 1-1.5
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SRAM Cell Layout
Layout of SRAM cell
• word line running horizontally
•bit lines running vertically
•cross-coupled inverters on top
•access transistors on bottom
Portion of the core array using
SRAM cell
•scaled in dimensions compared
to single bit cell
•2 cells across, 3 cells high
replicated in this manner to build
the core array
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Wordline Capacitance
• Word line presents a large capacitance to the decoder
• Each cell loads the word line with two transistor capacitances
and one wire capacitance (plus wire resistance)
• Total capacitance is the capacitance per cell x number of cells
on word
line
clock
b
b b
b
b
b
w1
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decoder
Row
Address
Bits
w2
x
x
x
wordline
w3
2
1
EECE481 Lecture 18
w4
a
w5
Bitline
a
Bitline
8
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Column I/O Operation
Circuits that perform read and write on the array are column I/O
• Bitline load
– Can be static or precharged
– Proper configuration depends on amplifier design
• For read
– Bit lines must start at around Vdd
– Swings should be small for fast operation
– Involves Mux and sense amplifier design
• For write
– Need to drive one of the bitlines to Gnd
– Mux and write driver design
– Often use different I/O lines for read and write
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Bitline Capacitance
Load capacitance is mostly self-loading of the cells
• Drain cap and drain contacts (0.5-1 fF) of transistors are
shared
– Junctions are biased at Vdd (lower cap than normal)
• Wire capacitance ~ .2fF/micron of wire
clock
b
b b
b
b
wordline
b
2
w1
1
a
w2
decoder
Row
Address
Bits
a
wordline
Bitline
Bitline
2
w3
1
a
a
w4
Bitline
Bitline
w5
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Bitline Load Options
PC
PC
PC
Important to
equalize bitline
voltage before
reads
cell
cell
wl
wl
Latch-based
b
Latch-based
b
b
Sense amplifier
b,b
VDD
b
Sense amplifier
b,b
PC
VDD
∆ v
PC
wl
wl
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b
Analog differential
b
Sense amplifier
VDD
VDD-VTN
PC
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Write Circuitry
M7
M8
pre
• Precharge bitlines high
clk
• Pull one column line low
cell
• Turn on word line
pre
• Wait until internal values
addr
Cbit
Cbit
of cell are established
b
• Turn off word line
• Design precharge
transistors
cell
data
b
a
wl
a
WL
col
b, b
to pull bit lines high
• Design write drivers to pull
one
side low depending on data
value
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W
M13
D
W
M14
D
col.sel.
a
Write
Driver
a
M15
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Read Circuitry
• Precharge bitlines high
M8
M7
pre
clk
• Turn on word line
cell
pre
•One line will slowly
discharge
addr
• Wait until bit line reaches
required low voltage level
Cbit
Cbit
data
cell
b
• Turn on column select
a
• Amplify difference with
sense amplifier
b
wl
a
trigger
WL
b,b
a
• Design sense amplifier
M9
based on desired response
time and power
col.enable
requirements
Sense
M10
col/sense
enable
Sense
Amplifier
• Use precharge based on enable
type of sense amp used.
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a
out
Output
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Column Decoder/Mux
•
•
•
•
•
Need decoder for column
address followed by a mux
to select column for input
or output operations
Require two outputs to
drive complementary pass
gates
Since the requirements for
read and write are different
can use separate read and
write IO lines
Have PMOS access for
the read IO lines, since the
read happens near Vdd
Have NMOS devices for
the write IO lines, since
you need to drive bitlines
to Gnd (see next slide)
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cell
cell
cell
cell
cell
cell
cell
cell
1
col
addr
C
O
L
U
M
N
D
E
C
O
D
E
R
2
3
2M
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Column Muxing – Separate I/O
Write
Driver
Sense
Amp
Write
Driver
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Sense
Amp
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Multi-Level Column Decoding
•Alternatives for column
selection are tree decoder,
regular decoder + pass
transistor, or some
combination of the two
•Shown on the right is a tree
decoder
– switches driven
directly by address bits
and their complements
COLUMNS
Bi
Bi + 2
B i+ 3
A1
A1
A2
–total of 2M+1 devices
–large devices to
reduce resistance
–long paths -> large C
-> SLOW
• To speed up, add buffers or
use adjust sizing of devices
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Bi + 1
A
2
•
•
•
TREE DECODER
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SENSE
CIRCUIT
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Other Options for Column Decoder/Mux
COLUMNS
Decoders
2
to
4
•
•
•
•
•
•
•
•
•
2
to
4
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Building Amplifiers
• We need an amplifier to handle small voltage swings on the bit
lines for fast operation
• Normally you need to choose between
– Drawing DC power (diff. sense amplifier)
– Using a clock edge (latch-based amplifier)
(to turn DC power on only when the signal is present)
• For CMOS logic gates
– When input is at VDD or Gnd, one of the transistors is off
– Nothing can happen until this transistor turns on
• And even then you need to wait some more for gate to switch
• Sitting in low gain region of transfer curve
• For an amplifier
– Want to be in high-gain region (saturation)
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Latch-based Sense Amplifier
• It must sense a very small signal
• It must consume a small area
– Need one for each bitline
– Or sets of bitline (4 or 8)
• Simplest design:
– Two back-to-back inverters
– Add a clocked pulldown
• Once Bit and Bit_b are established,
turn on pulldown device to activate
inverters
• Side with lower voltage will drop to
0V while the other side stays high
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Bit
Bit_b
VDD
SenseEnable
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Using Clocks and Regeneration
M2
SenseEnable
EECE481 Lecture 18
M3
Sense
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Sense_b
• Three stages of operation
– Precharge
– Sample
– Regenerate
• At the end of sample
– Small bitline voltage on
sense and sense_b
• Regenerate
– M2 and M3 turn on
– Voltage difference
causes current difference
– Which causes larger
voltage difference
M1
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