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Lecture 25 MOSFET Basics (Understanding with Math) Reading: Pierret 17.1-17.2 and Jaeger 4.1-4.10 and Notes Georgia Tech ECE 3040 - Dr. Alan Doolittle MOS Transistor I-V Derivation With our expression relating the Gate voltage to the surface potential and the fact that S=2F we can determine the value of the threshold voltage VT 2 F VT 2 F S 2qN A C ox S 2 F S 2qN D 2 F C ox S (for n - channel devices) (for p - channel devices) where, C ox ox xox is the oxide capacitance per unit area Where we have made use of the use of the expression, S KS o Georgia Tech ECE 3040 - Dr. Alan Doolittle MOS Transistor I-V Derivation Coordinate Definitions for our “NMOS” Transistor x=depth into the semiconductor from the oxide interface. y=length along the channel from the source contact z=width of the channel xc(y) = channel depth (varies along the length of the channel). n(x,y)= electron concentration at point (x,y) n(x,y)=the mobility of the carriers at point (x,y) Georgia Tech Device width is Z Channel Length is L Assume a “Long Channel” device (for now do not worry about the channel length modulation effect) ECE 3040 - Dr. Alan Doolittle MOS Transistor I-V Derivation Concept of Effective mobility The mobility of carriers near the interface is significantly lower than carriers in the semiconductor bulk due to interface scattering. Since the electron concentration also varies with position, the average mobility of electrons in the channel, known as the effective mobility, can be calculated by a weighted average, n x xc ( y ) x 0 n ( x, y )n( x, y )dx x xc ( y ) x 0 Empirically n n( x, y )dx or defining , QN ( y ) q x xc ( y ) x 0 n( x, y )dx ch arg e / cm q x xc ( y ) n n ( x, y )n( x, y )dx x 0 QN ( y ) Georgia Tech o 1 VGS VT where, o and are constants 2 ECE 3040 - Dr. Alan Doolittle MOS Transistor I-V Derivation Drain Current-Voltage Relationship In the Linear Region, VGS>VT and 0<VDS<Vdsat J N q n nE qDN n Neglecting the diffusion current, and recognizing the current is only in the y-direction, J N J Ny Georgia Tech d q n nE y q n n dy ECE 3040 - Dr. Alan Doolittle MOS Transistor I-V Derivation Drain Current-Voltage Relationship In the Linear Region, VGS>VT and 0<VDS<Vdsat I D J Ny dxdz Z x xc ( y ) x 0 J Ny dx x xc ( y ) d q n ( x, y )n( x, y )dx Z x 0 dy d Z n QN dy yL y 0 VDS I D dy Z n 0 VDS I D L Z n 0 Z n ID L Georgia Tech VDS 0 Q N d QN d Q N d To find ID, we need an expression relating the electrostatic potential, and QN ECE 3040 - Dr. Alan Doolittle MOS Transistor I-V Derivation “Capacitor-Like” Model for QN Assumptions: •Neglect all but the mobile inversion charge (valid for deep inversion) •For the MOSFET, the charge in the semiconductor is a linear function of position along the semiconductor side of the plate. Thus, varies from 0 to VDS Since Cox dQ , dV Source MOS Capacitor Only voltages above threshold create inversion charge QN Cox VGS VT for VGS VT Neglect the depletion region charge Georgia Tech Drain MOS Transistor QN Cox VGS VT for VGS VT Note: Assuming a linear variation of potential along the channel leads to an underestimation of current but is a good estimate for hand calculations. ECE 3040 - Dr. Alan Doolittle MOS Transistor I-V Derivation Using “Capacitor-Like” Model for QN we can estimate ID as: Z n V ID 0 QN d DS L Z n ID L VDS Z n C ox ID L 0 C ox VG VT d 2 VDS VGS VT V DS 2 0 V DS V Dsat and VGS VT This is known as the “square law” describing the Current-Voltage characteristics in the “Linear” or “Triode” region. Note the linear behavior for small VDS (can neglect VDS2 term). Note the negative parabolic dependence for larger VDS but still VDS<VDsat (can NOT neglect VDS2 term). Georgia Tech ECE 3040 - Dr. Alan Doolittle MOS Transistor I-V Derivation “Capacitor-Like” Model for QN But what about the saturation region? For VDS>Vdsat the voltage drop across our channel is VDsat with the remaining voltage (VDS-VDsat) dropped across the pinch-off region I D I Dsat Z n C ox L 2 V Dsat V V V GS T Dsat 2 V Dsat V DS But the charge at the end of the channel is zero due to the pinched off channel, Q N ( y L) C ox VGS VT V Dsat 0 VGS or VT V Dsat Thus, I D I Dsat Georgia Tech Z n C ox VGS VT 2 2L V Dsat V DS ECE 3040 - Dr. Alan Doolittle MOS Transistor I-V Derivation Summary of MOSFET IV Relationship Z n C ox ID L 0 VDS 2 VDS V V V GS T DS 2 V Dsat and VGS VT I D I Dsat Z n C ox VGS VT 2 2L V Dsat V DS VDsat VGS VT Georgia Tech ECE 3040 - Dr. Alan Doolittle MOS Transistor Applications Voltage variable Resistor An n-channel MOSFET has a gate width to length ratio of Z/L=100, un=200 cm2/Vsec, Cox=0.166 uF/cm2 and VT=1V. We want to develop a resistor that has a resistance that is controlled by an external voltage. Such a device would be used in “variable gain amplifiers”, “automatic gain control devices”, “compressors” and many other electronic devices. Define what range of VDS must be maintained to achieve proper “voltage variable resistance” operation. Find the “On-resistance” (VDS/ID) of the transistor from 1.5V<VGS<4Vfor small VDS . First, to achieve voltage variable resistance operation, we must operate in the linear region. Otherwise, the current is either a constant regardless of drain voltage (saturation region) or is approximately zero (cutoff due to the capacitor being in either accumulation and depletion). Thus, VGS -VT>VDS. Given the values above, 0<VDS<0.5V Continued... Georgia Tech ECE 3040 - Dr. Alan Doolittle MOS Transistor Applications Voltage variable Resistor Using the linear region ID equation: Z n C ox ID L RDS RDS 2 Z n C ox VDS VGS VT VDS for small VDS V V V GS T DS 2 L L V DS V DS Z ID Z n C ox n C ox VGS VT VGS VT VDS L 0.01 200 0.166e 6 F / cm 2 VGS 1 Thus, 100 RDS 600 Georgia Tech ECE 3040 - Dr. Alan Doolittle MOS Transistor Applications Current Source The same transistor is to be used for a “Current Source”. Define the range of drain-source voltage that can be used to achieve a fixed current of 50 uA. For a constant current regardless of Drain-Source voltage, we must use the saturation region: Z n C ox VGS VT 2 VDsat VDS 2L 100 200cm 2 / VSec 0.166uF / cm 2 VGS 12 50uA 2 VGS 1.173V I D I Dsat This source will operate over a VDS>VGS-VT or VDS>0.173 V Georgia Tech ECE 3040 - Dr. Alan Doolittle MOS Transistor: Deviations From Ideal Channel Length Modulation Effect Above “pinch-off” (when VDS>VDsat=VGS-VT) the channel length reduces by a value L. Thus, the expression for drain current, I D I Dsat Z n C ox VGS VT 2 2L Becomes, I D I Dsat Z nCox VGS VT 2 2L L or since * L L, I D I Dsat V Dsat VDS VDsat VDS 1 1 L 1 L L L L L Z nCox 2 VGS VT 1 2L L VDsat VDS *In many modern devices, this assumption does not hold. Thus, the channel length modulation parameter we are deriving does not describe the IV expressions well. Georgia Tech ECE 3040 - Dr. Alan Doolittle MOS Transistor: Deviations From Ideal Channel Length Modulation Effect But the fraction of the channel that is pinched off depends linearly on VDS because the voltage across the pinch-off region is (VDS-VDsat) so, L V DS L Channel Length Modulation causes the dependence of drain current on the drain voltage in saturation. where is known as the Channel-Length Modulation parameter and is typically: 0.001 V-1 < V I D I Dsat Georgia Tech Z n C ox VGS VT 2 1 VDS 2L V Dsat VDS ECE 3040 - Dr. Alan Doolittle MOS Transistor: Deviations From Ideal Body Effect (Substrate Biasing) Until now, we have only considered the case where the substrate (Body) has been grounded…. …but the substrate (Body) is often intentionally biased such that the Source-Body and Drain-Body junctions are reversed biased. The body bias, VBS, is known as the backgate bias and can be used to modify the threshold voltage. Note that now our channel potential has an offset equal to VBS, …. Georgia Tech ECE 3040 - Dr. Alan Doolittle MOS Transistor: Deviations From Ideal Body Effect (Substrate Biasing) Thus, our threshold potential with the body grounded, VT 2 F VT 2 F S 2qN A C ox S 2 F S 2qN D 2 F C ox S (for n - channel devices) (for p - channel devices) Surface Potential S The Gate- Body Threshold becomes, 2qN D 2 F VBS (for p - channel devices) VGB 2 F VBS S Cox S Threshold VGB Threshold 2 F VBS S Cox 2qN A S 2 F VBS (for n - channel devices) But we would like to have this in terms of VGS instead of VGB. Since, VGS =VGB+VBS VGS Threshold 2 F VT= Georgia Tech VGS Threshold 2 F S 2qN A C ox S 2 F VBS S 2qN D 2 F VBS C ox S (for n - channel devices) (for p - channel devices) ECE 3040 - Dr. Alan Doolittle MOS Transistor: Deviations From Ideal Body Effect (Substrate Biasing) This can be rewritten in the following form (more convenient to reference the threshold voltage to the VBS=0 case). 2 2 VT Pierret VTN Jaeger VTO F VBS 2 F VT Pierret VTP Jaeger VTO F VBS 2 F (for n - channel devices) (for p - channel devices) where, Georgia Tech 2qN A S C ox is known as the body effect parameter ECE 3040 - Dr. Alan Doolittle MOS Transistor: Enhancement Mode verses Depletion Mode MOSFET We have been studying the “enhancement mode” MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). It is called “enhancement” because conduction occurs only after the channel conductance is “improved” or “enhanced”. In this case, VTN>0 and VTP<0 Transistors can be fabricated such that: VTN 0 and VTP 0 These transistors have conduction for VGS=0 due to a channel already existing without the need to “invert the near surface region”. To modulate currents, a field must applied to the gate that depletes the channel. Thus, transistors of this nature are called “Depletion mode MOSFETs”. Georgia Tech ECE 3040 - Dr. Alan Doolittle MOS Transistor: Enhancement Mode verses Depletion Mode MOSFET Georgia Tech ECE 3040 - Dr. Alan Doolittle MOS Transistor: Summary 4-Terminal Enhancement Depletion 3-Terminal Enhancement Depletion NMOS (n-channel) PMOS (p-channel) Jaeger uses the notation: NMOS K n K n' W W n Cox where W is the Gate Width (Z in Pierret) L L PMOS K p K p' Georgia Tech W W p Cox where W is the Gate Width (Z in Pierret) L L ECE 3040 - Dr. Alan Doolittle MOS Transistor: Summary NMOS PMOS Regardless of Mode K n K n' Cutoff W W W W p Cox (Note : W Z in Pierret) n C ox (Note : W Z in Pierret) K p K 'p L L L L I DS 0 Linear I DS Z n C ox L VGS VTN Saturation for VGS VTN 2 VDS V V V GS TN DS 2 and VGS VTN VDS 0 VGS Threshold Voltage VTN VTO VT for Enhancement Mode VT for Depletion Mode Georgia Tech Z n C ox VGS VTN 2 1 VDS 2L VTN and V DS VGS VTN 0 I DS 2 F VSB 2 F I DS 0 for VGS VTP 2 Z n C ox VDS ID VGS VTP V DS L 2 VGS VTP and VGS VTP VDS 0 VGS Z n C ox VGS VTP 2 1 VDS 2L VTP and VDS VGS VTP 0 I DS VTP VTO 2 F VBS 2 F VTN 0 VTP 0 VTN 0 VTP 0 ECE 3040 - Dr. Alan Doolittle MOS Transistor: Bias Circuitry-Enhancement Mode NMOS Due to zero DC current flow in the gate, the bias analysis of a MOSFET is significantly easier than a BJT. A B C Georgia Tech •Form Thevenin circuits looking out the gate, drain, and source ECE 3040 - Dr. Alan Doolittle MOS Transistor: Bias Circuitry-Enhancement Mode NMOS 3V I G Rth VGS 10V I DS R3 VDS IG •But IG=0 so VGS=3V •Assume Saturation operation (selected for easy math because IDS does not depend on VDS since no was given – =0): IDS Kn vGS VTN 2 for v DS vGS VTN 0 2 25 x10 6 3 12 50 A i DS 2 Check V DS i DS 10V 50uA(100k ) VDS VDS 5V VGS VTN 2V •Assumption of Saturation operation was correct! If it were not correct simply make another assumption (I.e. linear region) and resolve. Georgia Tech ECE 3040 - Dr. Alan Doolittle MOS Transistor: Bias Circuitry-Depletion Mode NMOS •Bias circuit of a depletion mode device is much simpler due to the fact that the device conducts drain current for VGS=0V VTO 3V 0 V K n 200 uA •What value of R1 results in 100 uA drain current? •Again Assuming saturation: V2 Kn vGS VTN 2 for v DS vGS VTN 0 2 2 I DS 2 100uA VTN 3V 2V Kn 200uA / V 2 i DS VGS IDS R1 VGS 2 20 K I DS 100uA Check V DS 10V I DS R1 V DS 100uA20k V DS V DS 8V VGS VTN 2V (3V ) 1V •Assumption of Saturation operation was correct! If it were not correct simply make another assumption (I.e. linear region) and resolve. Georgia Tech ECE 3040 - Dr. Alan Doolittle PMOS Transistor: Bias Circuitry-Enhancement Mode PMOS VTO 1V 0 V K p 25 uA ID IS VGS VTP V2 K Z n C ox VGS VTP 2 1 VDS p VGS VTP 2 2L 2 and V DS VGS VTP 0 1. 5 M 6V R EQ 1M || 1.5M 600 K 1.5M 1M I S RS VGS I G RG V EQ V EQ 10V V DD V DD V EQ RS Kp 2 V GS 2 25 E 6 2.66 12 34.4A 2 I D RS V DS I D R D V DS 6.08V ID V DD 25 E 6 VGS 12 VGS 2 7.21 0 VGS 2.71 or 2.66V 10 6 4 39,000 VGS2 0.051VGS VTP VGS Check V DS V DS VGS VTP 0 6.08 2.66 ( 1) 0 Georgia Tech ECE 3040 - Dr. Alan Doolittle MOS Transistor: Bias Circuitry-Possible Combinations 1) Vth _ Base VGS I DS Rth _ Source Vth _ Source 2) I DS and K 2 n VGS VTN 1 VDS 2 optionally , Assume or I DS 2 VDS K n VGS VTN VDS 2 either saturated or linear/triode. 3) Vth _ Drain VDS I DS Rth _ Source Rth _ Drain Vth _ Source •Always: Solve 1) for VGS and plug into 2). •In certain cases, VDS will need to be eliminated by using 3) solved for VDS and plugged into 2). •Case A: Saturated, and =0 and no source resistor – only 1 and 2 required. Results in 1st order polynomial. •Case B: Saturated, and >0 and no source resistor – all 3 equations needed. Results in 1st order polynomial. •Case C: Saturated, and =0 and a source resistor – all 3 equations needed. Results in 2nd order polynomial. •Case D: Saturated, and >0 and a source resistor – all 3 equations needed. Results in 3rd order polynomial. •Case E: Linear/Triode, with or without a source resistor – all 3 equations needed. Results in 2nd order polynomial. Georgia Tech ECE 3040 - Dr. Alan Doolittle Useful Formulas for DC Bias Solutions If a 3rd order polynomial results, try factoring it into a linear and quadratic term 1st. If this is not easy for your case, a longer but sure fire way is listed below. Georgia Tech ECE 3040 - Dr. Alan Doolittle