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CS 61C: Great Ideas in Computer
Architecture
Lecture 5: Intro to Assembly
Language, MIPS Intro
Instructor: Sagar Karandikar
[email protected]
http://inst.eecs.berkeley.edu/~cs61c
1
Levels of
Representation/Interpretation
High Level Language
Program (e.g., C)
Compiler
Assembly Language
Program (e.g., MIPS)
Assembler
Machine Language
Program (MIPS)
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
lw
lw
sw
sw
0000
1010
1100
0101
$t0, 0($2)
$t1, 4($2)
$t1, 0($2)
$t0, 4($2)
1001
1111
0110
1000
1100
0101
1010
0000
Anything can be represented
as a number,
i.e., data or instructions
0110
1000
1111
1001
1010
0000
0101
1100
1111
1001
1000
0110
0101
1100
0000
1010
1000
0110
1001
1111
Machine
Interpretation
Hardware Architecture Description
(e.g., block diagrams)
Architecture
Implementation
Logic Circuit Description
(Circuit Schematic Diagrams)
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Assembly Language
• Basic job of a CPU: execute lots of instructions.
• Instructions are the primitive operations that the
CPU may execute.
• Different CPUs implement different sets of
instructions. The set of instructions a particular
CPU implements is an
Instruction Set Architecture (ISA).
– Examples: ARM, Intel x86, MIPS, RISC-V,
IBM/Motorola PowerPC (old Mac), Intel IA64, ...
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Instruction Set Architectures
• Early trend was to add more and more instructions
to new CPUs to do elaborate operations
– VAX architecture had an instruction to multiply
polynomials!
• RISC philosophy (Cocke IBM, Patterson, Hennessy,
1980s) –
Reduced Instruction Set Computing
– Keep the instruction set small and simple, makes it
easier to build fast hardware.
– Let software do complicated operations by composing
simpler ones.
4
MIPS Architecture
• MIPS – semiconductor company that built one of
the first commercial RISC architectures
• We will study the MIPS architecture in some detail
in this class (upper-div arch classes like 150, 152
use a similar ISA, RISC-V)
• Why MIPS instead of Intel x86?
– MIPS is simple, elegant. Don’t want to get bogged
down in gritty details.
– MIPS widely used in embedded apps, x86 little used in
embedded, and more embedded computers than PCs
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Assembly Variables: Registers
• Unlike HLL like C or Java, assembly cannot use
variables
– Why not? Keep Hardware Simple
• Assembly Operands are registers
– Limited number of special locations built directly
into the hardware
– Operations can only be performed on these!
• Benefit: Since registers are directly in
hardware, they are very fast
(faster than 1 ns - light travels 30cm in 1 ns!!! )
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Number of MIPS Registers
• Drawback: Since registers are in hardware,
there are a predetermined number of them
– Solution: MIPS code must be very carefully put
together to efficiently use registers
• 32 registers in MIPS
– Why 32? Smaller is faster, but too small is bad.
Goldilocks problem.
• Each MIPS register is 32 bits wide
– Groups of 32 bits called a word in MIPS
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Names of MIPS Registers
• Registers are numbered from 0 to 31
• Each register can be referred to by number or name
• Number references:
–$0, $1, $2, … $30, $31
• For now:
– $16 - $23 $s0 - $s7
(correspond to C variables)
– $8 - $15  $t0 - $t7 (correspond to temporary variables)
– Later will explain other 16 register names
• In general, use names to make your code more
readable
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C, Java variables vs. registers
• In C (and most High Level Languages) variables
declared first and given a type
• Example: int fahr, celsius;
char a, b, c, d, e;
• Each variable can ONLY represent a value of
the type it was declared as
(cannot mix and match int and char variables).
• In Assembly Language, registers have no type;
operation determines how register contents are
treated
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Addition and Subtraction of Integers
• Addition in Assembly
– Example:
add $s0,$s1,$s2 (in MIPS)
– Equivalent to:
a=b+c
(in C)
where C variables ⇔ MIPS registers are:
a ⇔ $s0, b ⇔ $s1, c ⇔ $s2
• Subtraction in Assembly
– Example:
sub $s3,$s4,$s5 (in MIPS)
– Equivalent to:
d=e-f
(in C)
where C variables ⇔ MIPS registers are:
d ⇔ $s3, e ⇔ $s4, f ⇔ $s5
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Addition and Subtraction of Integers
Example 1
• How to do the following C statement?
a = b + c + d - e;
• Break into multiple instructions
add $t0, $s1, $s2 # temp = b + c
add $t0, $t0, $s3 # temp = temp + d
sub $s0, $t0, $s4 # a = temp - e
• A single line of C may break up into several lines of
MIPS.
• Notice the use of temporary registers – don’t want to
modify the variable registers $s
• Everything after the hash mark on each line is ignored
(comments)
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Immediates
• Immediates are numerical constants.
• They appear often in code, so there are special
instructions for them.
• Add Immediate:
addi $s0,$s1,-10 (in MIPS)
f = g - 10
(in C)
where MIPS registers $s0,$s1 are associated with
C variables f, g
• Syntax similar to add instruction, except that
last argument is a number instead of a register.
add $s0,$s1,$zero (in MIPS)
f=g
(in C)
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Overflow in Arithmetic
• Reminder: Overflow occurs when there is a
“mistake” in arithmetic due to the limited
precision in computers.
• Example (4-bit unsigned numbers):
15
+ 3
18
1111
+ 0011
10010
• But we don’t have room for 5-bit solution, so
the solution would be 0010, which is +2, and
“wrong”.
13
Overflow handling in MIPS
• Some languages detect overflow (Ada),
some don’t (most C implementations)
• MIPS solution is 2 kinds of arithmetic instructions:
– These cause overflow to be detected
• add (add)
• add immediate (addi)
• subtract (sub)
– These do not cause overflow detection
• add unsigned (addu)
• add immediate unsigned (addiu)
• subtract unsigned (subu)
• Compiler selects appropriate arithmetic
– MIPS C compilers produce addu, addiu, subu
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Data Transfer:
Load from and Store to memory
Memory
Processor
Enable?
Read/Write
Control
Input
Program
Datapath
Address
PC
Write Data =
Store to
memory
Registers
Arithmetic & Logic Unit
(ALU)
Bytes
Read Data =
Load from
memory
Processor-Memory Interface
Data
Output
I/O-Memory Interfaces
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Memory Addresses are in Bytes
• Lots of data is smaller than 32 bits, but rarely
smaller than 8 bits – works fine if everything is a
Addr of lowest byte in
multiple of 8 bits
word is addr of word
• 8 bit chunk is called a byte
(1 word = 4 bytes)
… …… … …
• Memory addresses are really
12 13 3 14 15
in bytes, not words
8 9 2 10 11
4 516 7
• Word addresses are 4 bytes
0 102 3
apart
– Word address is same as address of leftmost byte
(i.e. Big-endian)
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Transfer from Memory to Register
• C code
int A[100];
g = h + A[3];
• Using Load Word (lw) in MIPS:
lw $t0,12($s3) # Temp reg $t0 gets A[3]
add $s1,$s2,$t0 # g = h + A[3]
$s3 – base register (pointer)
12 – offset in bytes
Offset must be a constant known at assembly time
Note:
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Transfer from Register to Memory
• C code
int A[100];
A[10] = h + A[3];
• Using Store Word (sw) in MIPS:
lw $t0,12($s3) # Temp reg $t0 gets A[3]
add $t0,$s2,$t0 # Temp reg $t0 gets h + A[3]
sw $t0, 40($s3) # A[10] = h + A[3]
Note:
$s3 – base register (pointer)
12,40 – offsets in bytes
$s3+12 and $s3+40 must be multiples of 4
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Loading and Storing bytes
• In addition to word data transfers
(lw, sw), MIPS has byte data transfers:
– load byte: lb
– store byte: sb
• Same format as lw, sw
• E.g., lb $s0, 3($s1)
– contents of memory location with address = sum
of “3” + contents of register $s1 is copied to the low
byte position of register $s0.
$s0: xxxx xxxx xxxx xxxx xxxx xxxx xzzz zzzz
…is copied to “sign-extend”
byte
loaded
This bit
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Speed of Registers vs. Memory
• Given that
– Registers: 32 words (128 Bytes)
– Memory: Billions of bytes (2 GB to 8 GB on laptop)
• and the RISC principle is…
– Smaller is faster
• How much faster are registers than memory??
• About 100-500 times faster!
– in terms of latency of one access
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How many hours h on Homework 0?
A: 0 ≤ h < 5
B: 5 ≤ h < 10
C: 10 ≤ h < 15
D: 15 ≤ h < 20
E: 20 ≤ h
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Clickers/Peer Instruction
We want to translate *x = *y +1 into MIPS
(x, y pointers to ints, stored in: $s0 $s1)
A:
addi $s0,$s1,1
B:
lw
$s0,1($s1)
sw
$s1,0($s0)
C:
lw
$t0,0($s1)
addi $t0,$t0,1
sw
$t0,0($s0)
D:
E:
sw
$t0,0($s1)
addi $t0,$t0, 1
lw
$t0,0($s0)
lw
sw
$s0,1($t0)
$s1,0($t0)
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Break
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MIPS Logical Instructions
• Useful to operate on fields of bits within a word
− e.g., characters within a word (8 bits)
• Operations to pack /unpack bits into words
• Called logical operations
Logical
C
Java
MIPS
operations operators operators instructions
and
&
&
Bit-by-bit AND
or
|
|
Bit-by-bit OR
not
~
~
Bit-by-bit NOT
sll
<<
<<
Shift left
srl
>>
>>>
Shift right
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Logic Shifting
• Shift Left: sll $s1,$s2,2 #s1=s2<<2
– Store in $s1 the value from $s2 shifted 2 bits to the
left (they fall off end), inserting 0’s on right; << in C.
Before: 0000 0002hex
0000 0000 0000 0000 0000 0000 0000 0010two
After: 0000 0008hex
0000 0000 0000 0000 0000 0000 0000 1000two
What arithmetic effect does shift left have?
• Shift Right: srl is opposite shift; >>
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Arithmetic Shifting
• Shift right arithmetic moves n bits to the right
(insert high order sign bit into empty bits)
• For example, if register $s0 contained
1111 1111 1111 1111 1111 1111 1110 0111two= -25ten
• If executed sra $s0, $s0, 4, result is:
1111 1111 1111 1111 1111 1111 1111 1110two= -2ten
• Unfortunately, this is NOT same as dividing by 2n
− Fails for odd negative numbers
− C arithmetic semantics is that division should round towards 0
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Computer Decision Making
• Based on computation, do something different
• In programming languages: if-statement
• MIPS: if-statement instruction is
beq register1,register2,L1
means: go to statement labeled L1
if (value in register1) == (value in register2)
….otherwise, go to next statement
• beq stands for branch if equal
• Other instruction: bne for branch if not equal
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Types of Branches
• Branch – change of control flow
• Conditional Branch – change control flow
depending on outcome of comparison
– branch if equal (beq) or branch if not equal (bne)
• Unconditional Branch – always branch
– a MIPS instruction for this: jump (j)
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Example if Statement
• Assuming translations below, compile if block
f → $s0 g → $s1 h → $s2
i → $s3 j → $s4
if (i == j)
bne $s3,$s4,Exit
f = g + h;
add $s0,$s1,$s2
Exit:
• May need to negate branch condition
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Example if-else Statement
• Assuming translations below, compile
f → $s0 g → $s1 h → $s2
i → $s3 j → $s4
if (i == j)
bne $s3,$s4,Else
f = g + h;
add $s0,$s1,$s2
else
j Exit
f = g – h; Else: sub $s0,$s1,$s2
Exit:
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Administrivia
• Hopefully everyone completed HW0
• HW1 out
• Proj 1 out
– Make sure you test your code on hive machines, that’s
where we’ll grade them
• First Guerrilla Session this Thursday (07/02) from 57pm in the Woz
– Optional (not part of EPA)
– Covers Number Rep and MIPS
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Administrivia
• Midterm one week from Thursday
–
–
–
–
–
–
In this room, at this time
One 8.5”x11” handwritten cheatsheet
We’ll provide a MIPS green sheet
No electronics
Covers up to and including this Thursday’s lecture (07/02)
TA-led review session on Monday 07/06 from 5-8pm in HP
Auditorium
• Feedback form at the end of lab 2 – tell us
how lecture, disc, and lab are going
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CS61C in the News
RISC-V Workshop
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CS61C in the News
RISC-V Workshop
• Workshop happening right now at
International House
• A modest goal: To become the industry
standard ISA (replacing x86, ARM, MIPS, etc.)
• CS150, CS152, CS250, CS252 use RISC-V
35
CS61C in the News pt. 2
36
Inequalities in MIPS
• Until now, we’ve only tested equalities
(== and != in C). General programs need to test < and >
as well.
• Introduce MIPS Inequality Instruction:
“Set on Less Than”
Syntax:
slt reg1,reg2,reg3
Meaning: if (reg2 < reg3)
reg1 = 1;
else reg1 = 0;
“set” means “change to 1”,
“reset” means “change to 0”.
37
Inequalities in MIPS Cont.
• How do we use this? Compile by hand:
if (g < h) goto Less; #g:$s0, h:$s1
• Answer: compiled MIPS code…
slt $t0,$s0,$s1 # $t0 = 1 if g<h
bne $t0,$zero,Less # if $t0!=0 goto Less
• Register $zero always contains the value 0, so bne and beq
often use it for comparison after an slt instruction
• sltu treats registers as unsigned
38
Immediates in Inequalities
• slti an immediate version of slt to test
against constants
Loop:
. . .
slti $t0,$s0,1
beq
$t0,$zero,Loop
# $t0 = 1 if
# $s0<1
# goto Loop
# if $t0==0
# (if ($s0>=1))
39
Loops in C/Assembly
• Simple loop in C;
A[] is an array of ints
do { g = g + A[i];
i = i + j;
} while (i != h);
• Use this mapping: g, h, i, j, &A[0]
$s1, $s2, $s3, $s4, $s5
Loop: sll $t1,$s3,2
addu $t1,$t1,$s5
lw
$t1,0($t1)
add $s1,$s1,$t1
addu $s3,$s3,$s4
bne $s3,$s2,Loop
# $t1= 4*i
# $t1=addr A+4i
# $t1=A[i]
# g=g+A[i]
# i=i+j
# goto Loop
# if i!=h
40
Which of the following are true for
the addiu instruction?
1: The instruction performs a
different operation at the hardware
level than add (excluding overflow
reporting)
2: The instruction tells the
hardware not to report an overflow
A:
B:
C:
D:
E:
F,
T,
F,
F,
T,
F,
T,
T,
T,
F,
F
T
F
T
F
3: The instruction sign extends the
immediate
41
And In Conclusion …
• Computer words and vocabulary are called instructions
and instruction set respectively
• MIPS is example RISC instruction set in this class
• Rigid format: 1 operation, 2 source operands, 1
destination
– add,sub,mul,div,and,or,sll,srl,sra
– lw,sw,lb,sb to move data to/from registers from/to
memory
– beq, bne, j, slt, slti for decision/flow control
• Simple mappings from arithmetic expressions, array
access, if-then-else in C to MIPS instructions
42