Download programable devices

PROGRAMABLE DEVICES
This is the broadest category of products we cover in one section as can readily be seen
when considering that the parts reported on range in die size from 7 mm2 to 115 mm2.
Technologies covered range from standard to antifuse, and some unusual combinations of
process features occur. For example, the AT&T use of a salicide process which we
regard as being quite advanced, on a die that looks quite primitive otherwise.
None of these devices used any of the process features generally regarded as indicating
advanced capability like more than two or three metal or poly layers, plugs for vertical
interconnect, or chemical-mechanical planarization (CMP).
4-1
HORIZONTAL DIMENSIONS (DESIGN RULES)
PROGRAMABLE
DEVICES
Actel
AT&T
Altera
Altera
Lattice
AMD
A1280A
FPGA
9423
ATT3020
FPGA
9323
EMP5128LC
EPLD
9349
EMP7032
EPLD
9401
GAL22V10
EPLA
9351
PAL22V10
EPLA
9402
Die size
10.5 x 10.9 mm
(115 mm2)
4.2 x 5.3 mm
(22 mm2 )
6.9 x 8.1 mm
(56 mm2 )
2.7 x 4.0 mm
(11mm 2)
2.4 x 2.9 mm
(7mm 2 )
2.6 x 4.4 mm
(11mm 2)
Min M2 width
1.5µm
1.3µm
2.2µm
1.0µm
1.5µm
2.0µm
Min M1 width
1.8µm
0.7µm
1.5µm
0.6µm
1.0µm
1.8µm
Min M2 space
1.9µm
1.6µm
1.7µm
1.0µm
1.4µm
2.0µm
Min M1 space
1.1µm
1.1µm
1.5µm
0.6µm
1.1µm
1.4µm
Min via
1.5µm
1.2µm
1.8µm
1.6µm
1.1µm
1.8µm
1.2µm
1.0µm
1.3µm
1.0µm
1.0µm
1.9µm
Min Poly 2
1.7µm
NA
0.7µm
NA
NA
NA
Min Poly 1
0.7µm
0.8µm*
1.4µm
0.45µm*
0.5µm
0.7µm
Min gate - (N)†
0.7µm
0.8µm
0.75µm
0.45µm
0.5µm
0.7µm
Min gate - (P)†
0.9µm
0.9µm
0.95µm
0.7µm
0.65µm
0.7µm
Cell pitch
5 x 4.25µm
NA
5 x 11µm
6.5 x 17µm
Cell area
21µm2
NA
55µm2
110µm2
(Met. to
Met.)
Min cntct (Met.
to
Si)
*Polycide
†Physical gate length
TABLE 4 - 1
12.4 x 15.9µm
197µm2
10.7 x 20.2µm
216µm2
VERTICAL DIMENSIONS
PROGRAMABLE
DEVICES
Actel
AT&T
Altera
Altera
Lattice
AMD
A1280A
FPGA
9423
ATT3020
FPGA
9323
EMP5128LC
EPLD
9349
EPM7032
EPLD
9401
GAL22V10
EPLA
9351
PAL22V10
EPLA
9402
Final passivation
1.15µm
0.75µm
1.7µm
0.7µm
0.9µm
1.1µm
Metal 2
1.1µm
1.1µm
1.25µm
1.15µm
0.85µm
1.5µm
Metal 1
0.75µm
0.6µm
0.95µm
0.8µm
0.65µm
0.75µm
Intermetal
dielectric
0.7µm
0.6µm
0.75µm
0.6µm
0.4µm
0.75µm
Poly 2
0.25µm
NA
0.25µm
NA
NA
NA
Poly 1
0.25µm
0.4µm*
0.15µm
0.35µm*
0.3µm
0.3µm
Recessed oxide
0.9µm
0.5µm
0.65µm
0.5µm
0.5µm
0.75µm
N-well
3µm
1.5µm
?1
4µm
6.5µm
5µm
P-well
?1
?1
?1
3µm
6.5µm
4.5µm
Epi
7.5µm (P)
6.5µm (P)
None
None
None
None
*Polycide
TABLE 4 - 2
1Could not delineate
DIE MATERIALS
PROGRAMABLE
DEVICES
Actel
AT&T
Altera
Altera
Lattice
AMD
A1280A
FPGA
9423
ATT3020
FPGA
9323
EMP5128LC
EPLD
9349
EPM7032
EPLD
9401
GAL22V10
EPLA
9351
PAL22V10
EPLA
9402
Final passivation
Nitride on glass
Nitride on glass
Nitride on glass
Nitride
Nitride on glass
Glass
Metal 2
Aluminum
Titanium
Aluminum
Aluminum
Titanium
Aluminum
Titanium-tungsten
Titanium-nitride
Aluminum
Aluminum
Metal 1
Aluminum
Titanium-nitride
Aluminum
Titanium-nitride
Titanium
Titanium
Aluminum
Titanium-tungsten
Titanium
Aluminum
Titanium-tungsten
Titanium-nitride
Aluminum
Titanium-nitride
Titanium
Aluminum
Titanium-nitride
Titanium
Intermetal dielectric
Glass
Glass
Glass
Glass
Glass
Glass
Reflow glass
BPSG
BPSG
BPSG
BPSG
BPSG
BPSG
Polycide metal
NA
Titanium
NA
Tungsten
NA
NA
TABLE 4 - 3
TECHNOLOGY DESCRIPTION
ACTEL A1280A
FPGA (Antifuse)
Introduction
Ref. report SCA 9409-348
These parts were packaged in 172-pin, Ceramic Quad Flat Packs (CQFPs), date coded
week 23 of 1994. All parts were fully functional production samples. This architecture
provides 8,000 equivalent gate array gates or 20,000 PLD equivalent gates. The devices
operate from a standard 5V power source.
See tables for specific dimensions and materials identification and see figures for
examples of physical structures.
Unusual/Unique Features
- Antifuse structure.
- Relatively complex process including various length shallow source/drain extensions.
Quality
Quality of process implementation was normal. Metal thinning was significant but not of
serious concern.
In the area of layer patterning, both etch definition and control (depth) were good.
Alignment/registration was also good.
Packaging/assembly quality and workmanship was good as well.
Technology
These devices were made by a twin (multiple)-well CMOS process in a P-epi on a P
substrate. Two levels of metal and two levels of polysilicon were used. A normal
recessed-oxide isolation was employed. No attempt to shorten the birdsbeak area was
made. The cell array used poly 2 over diffusion with ultra thin oxide windows for
programming.
Both metal levels consisted of aluminum and were defined by standard dry etch
techniques. Metal 2 used no cap but did have a relatively thick layer of titanium
4-2
underneath as an adhesion/barrier layer. Metal 1 used a titanium-nitride barrier on a very
thin titanium adhesion layer, but also had no cap layer on top.
No plugs were present at vias or contacts and no polycide or salicide source/drain
treatment was used.
No buried contacts were used. Metal 2 contacted metal 1, and metal 1 contacted
diffusions and poly.
Planarization of the intermetal dielectric was by deposited glass layers and planarizing
etch. A spin-on-glass (SOG) was included. The dielectric under metal 1 was planarized
by a reflow process.
Poly 1 (no polycide) provided all gates on the die while poly 2 was used exclusively for
program elements. All gates used oxide sidewall spacers that were left in place. In
addition, various length, lightly doped, shallow N+ extensions were present at some Nchannel gates. In some cases, these were present on both sides of the gate, in others, only
on one side. Also, of course, another totally separate diffusion is used in the memory
array (see below).
Both gate oxide and antifuse dielectric appeared to be normal grown oxides, but a thin
layer of what appeared to be silicon nitride was present directly below the BPSG reflow
glass (above poly 2). Since we found no cutouts that would indicate its use as a mask
definition layer, we assume it is intended to mask the lightly doped very shallow
diffusion extensions from possible doping effects of the reflow glass.
Overall minimum feature measured anywhere on these dice was the 0.7 micron poly 1 width.
Minimum physical gate lengths measured were 0.7 micron for N- channel and 0.9 micron
for P-channel.
Array Cell Structures
These parts used round windows of ultra thin ruptureable oxide for programming. These
windows were located between poly 2 and special N+ diffusion "program" lines in 8-bit
groups between piggyback metal contacts. The array was in the form of an X-Y matrix.
Cells are programmed by "zapping" the thin dielectric to establish a connection between
the poly 2 line and the N+ diffusion line. Series resistance is kept low by connecting the
N+ with piggyback metal 2 lines.
Individual cell size including the overhead area caused by the piggyback connections, was 5
x 4.25 microns (21.25 microns2) although individual cells measure only 3.5 x 4.25 microns
(<15 microns2). Diameter of the antifuse window was measured to be 1.25 micron.
4-3
Packaging/Assembly
As mentioned, devices were packaged in standard 172-pin, CQFPs. All pins were
connected. Die attach was by a silver glass or epoxy and standard ultrasonic wirebonds
using aluminum wire were used. Two tiers of bond pads were used in the package.
No special heatsink or other elements were used.
No evidence of a die coat was found.
4-4
®
PIN 1
The Actel A1280 FPGA circuit die. Mag. 16x.
®
EMBEDDING MEDIA
section,
Mag. 8000x
POLY 1 GATE
Mag. 3700x, 60°
N+
Mag. 30,000x, 50°
Actel A1280. SEM views illustrating device structures.
TECHNOLOGY DESCRIPTION
AT&T ATT3020-70
FPGA
Introduction
Ref. report SCA 9410-375
These parts were packaged in 84-pin, ceramic Pin-Grid Array (PGA) packages, date
coded week 23 of 1993. Parts were fully functional production samples. These devices
provide an architecture composed of configuration program store plus three types of
configurable elements: perimeter I/O, core logic, and interconnect. The 3020 offers 8 x 8
configurable logic blocks and 2000 equivalent gates. They operate from a standard 5V
power source.
See tables for specific dimensions and materials identification and see figures for
examples of physical structures.
Unusual/Unique Features
- Unusual combination of process features.
Quality
Quality of process implementation was less than desirable in the area of metal 1 step
coverage at contacts where we found very severe metal thinning.
Layer patterning and etch definition were good, but control (depth) was very poor at
sidewall definition resulting in severe overetching of the recessed oxide.
Alignment/registration was good.
Packaging/assembly was normal to poor due to silicon chipouts at the edges of the die.
Technology
These devices were made by a twin (multiple)-well CMOS process, employing a P-epi on
a P substrate. Two levels of metal and one level of polycide (titanium on polysilicon)
were used. A severely etched-back, recessed-oxide isolation was employed, but
birdsbeak areas were not particularly short. No evidence of any unusual gate oxide or
dielectric layers was found.
4-5
Both metal levels consisted of aluminum defined by standard dry etch techniques. Cap
layers were not used on either metal 2 or metal 1, but metal 1 did make use of a barrier.
It consisted of titanium-nitride on titanium.
Standard vias and contacts were used (no plugs) and no buried contacts (poly to silicon)
were present. Metal 2 contacted metal 1, and metal 1 contacted diffusions, and polycide.
Planarization of the intermetal dielectric was by at least two layers of deposited glass and
some minimal planarizing etch. The dielectric under metal 1 was planarized by a reflow
process. Overall, planarization was minimal and poor. No spin-on-glass (SOG) was used
and the severe overetching of the recessed oxide created very high steps at every polycide
line where it crossed this oxide. These steps were accentuated rather than decreased by
the subsequent attempt at planarization.
All gates were formed by the layer of polycide and all used sidewall spacers that were left
in place.
A somewhat unusual feature present was the use of salicide on the sources/drains, which
although certainly not unheard of, was unexpected on a die with the rudimentary process
features present everywhere else.
Overall minimum feature measured anywhere on these dice was the 0.7 micron metal 1
width.
Minimum physical gate lengths measured were 0.8 micron for N-channel and 0.9 micron
P-channel.
Array Cell Structures
These parts used large complex "cell" blocks consisting of many transistors, so transistor
count and area measurement are meaningless for comparison purposes. Technology in
this area was identical to rest of the die and no items of special interest were found.
Packaging/Assembly
Devices were packaged in standard 84-pin ceramic PGAs with metal lids. All but two
pads on the die were connected. A single tier package land arrangement was employed
and connected by gold wire and thermosonic wirebonds. Die attach was by gold-silicon
eutectic.
No die coat was used and no heatsink was present.
4-6
®®
The AT&T 3020-70 FPGA circuit die. Mag. 40x.
®
METAL 2
section,
Mag. 12,000x
METAL 1
Ti SILICIDE
POLYCIDE GATE
INTERMEDIATE GLASS
POLY
Mag. 4000x, 60°
DIFFUSION
METAL 1
section,
Mag. 30,000x
POLYCIDE GATE
AT&T 3020-70. SEM views illustrating device structures.
TECHNOLOGY DESCRIPTION
ALTERA EPM5128LC
(MAX 5000) EPLD
Introduction
Ref. report SCA 9411-376
These parts were packaged in 68-pin, plastic leaded chip carrier (PLCC) packages, date
coded week 49 of 1993. Parts were fully functional production samples. These devices
are UV erasable when in window packages (one time programable in plastic). This
specific device offers 128 macrocells and is capable of >60 MHz for pipelined data rates.
These parts were apparently an Altera design, fabbed by Cypress according to package
and die marking. They operate from a standard 5V power source.
See tables for specific dimensions and materials identification and see figures for
examples of physical structures.
Unusual/Unique Features
- Unique dielectric feature at vias.
Quality
Quality of process implementation was good, but parts failed latch-up tests.
In the area of layer patterning, both etch definition and control (depth) were good.
Alignment/registration was also good.
Packaging/assembly was good as well.
Technology
These devices were made by a twin (multiple)-well CMOS process, employing an N
substrate. No evidence of an epi layer was found. Two levels of metal and two levels of
poly (no polycide) were used. A normal recessed-oxide isolation was employed.
Both metal levels consisted of aluminum defined by standard dry etch techniques. Metal 2
employed a titanium barrier/adhesion layer and no cap layer. Metal 1 used a titanium cap
and a titanium-tungsten barrier on a titanium adhesion layer.
4-7
No plugs were present at vias or contacts and no salicide source/drain treatment was used. No
buried contacts were used. Metal 2 contacted metal 1, and metal 1 contacted diffusions, and
poly 2.
Planarization of the intermetal dielectric was by three layers of deposited glass including a spinon-glass. A unique and unexplained feature was present in the SOG at all via connections. The
SOG material had different etch characteristics immediately around the via cuts (i.e., it appeared
to be less dense). The only explanation for this seems to be that it is an effect of the etch used for
the via cuts. We've never seen it before, but it appeared to have no affect on anything including
quality. The dielectric under metal 1 was planarized by a reflow process.
All gates were formed by a layer of standard polysilicon (poly 2) and all used oxide sidewall
spacers that were subsequently removed.
Redundancy fuses were present (but not activated) and were also made with the poly 2.
No evidence of any unusual gate oxide materials was found.
Overall minimum feature measured anywhere on these dice was the 0.7 micron poly width.
Minimum physical gate lengths measured were 0.75 micron for N-channel and 0.95 micron
P-channel.
Array Cell Structures
These parts used a two- transistor one-capacitor cell, all of which use the floating poly 1 so that
both gate and capacitor oxide is the same. Dielectric between the poly 2 word line and poly 1
elements was an ONO (oxide-nitride-oxide), however.
Bit lines were formed by metal 1.
Poly 1 was defined after sidewall formation on poly 2, so it protrudes beyond the poly 2 word
lines. Poly 1 did not use sidewall spacers. Gate length of these poly 1 floating gates was 1.3
micron.
The cell size was measured to be 55 microns 2.
Packaging/Assembly
Devices were packaged in standard 68-pin J-lead PLCCs. All pins were connected. Die attach
was by a silver-epoxy.
No die coat was used and no heatsink was present.
4-8
®
The Altera EPM5128LC EPLD circuit die. Mag. 20x.
®
section,
Mag. 10,000x
POLY 2
N+
OXIDE
POLY 1
Mag. 9100x, 60°
Q2
Q1
BIT 1
BIT 2
WORD
VSS
BIT 1
Q1
C
BIT 2
Mag. 4000x, 0°
POLY 2
ON
POLY 1
Q2
Altera EPM5128LC. SEM views illustrating device structures.
TECHNOLOGY DESCRIPTION
ALTERA EPM7032
(MAX 7000) EPLD
Introduction
Ref. report SCA 9406-336
These parts were packaged in 44-pin, plastic leaded chip carrier (PLCC) packages, date
coded week 1 of 1994. Parts were fully functional production samples. These devices
reflect Altera's second generation MAX architecture with 125 MHz system speed and 7.5
nsec propagation delays. This specific device offers 600 usable gates and 32 advanced
macrocells. They operate from a standard 5V power source.
See tables for specific dimensions and materials identification and see figures for
examples of physical structures.
Unusual/Unique Features
- Modern but relatively simple process.
Quality
Quality of process implementation was less than desirable in the area of metal 1 step
coverage at contacts where we found significant aluminum thinning and a hint of possible
cracking in the barrier metal. Subsequent analysis of this product type done at a later date
and not related to this project indicated that these problems had been solved.
Parts also failed latch-up tests.
In the area of layer patterning, both etch definition and control (depth) were good.
Alignment/registration was also good.
Packaging quality was normal.
Technology
These devices were made by a twin (multiple)-well CMOS process, employing a P
substrate. No evidence of an epi layer was found. Two levels of metal and one level of
polycide (tungsten on polysilicon) were used. A fairly deep recessed-oxide isolation was
employed, with birdsbeak areas kept short.
4-9
Both metal levels consisted of aluminum defined by standard dry etch techniques, and
both had thick titanium-tungsten barriers. Cap layers were not used on either metal 2 or
metal 1.
No plugs were present at vias or contacts and no salicide source/drain treatment was
present. No buried contacts were used. Metal 2 contacted metal 1, and metal 1 contacted
diffusions, and polycide.
Planarization of the intermetal dielectric was by at least four layers of deposited glass
(including two spin-on-glass layers) and planarizing etch. The dielectric under metal 1
was planarized by a reflow process.
All gates were formed by the polycide (tungsten on polysilicon) and all used oxide
sidewall spacers that were left in place.
Redundancy fuses were not present.
No evidence of any unusual gate oxide or dielectric materials was found.
Overall minimum feature measured anywhere on these dice was the 0.45 micron polycide width.
Minimum physical gate lengths measured were 0.45 micron for N-channel and 0.7 micron
P-channel.
Array Cell Structures
These parts used a 3 transistor NMOS cell incorporating one capacitor. Programming
uses a window of thin tunnel oxide.
Metal 2 provided piggyback word lines, metal 1 was used for all the power connections,
control and program lines. Polycide was used for all gates, capacitors and word lines.
The cell size was measured to be 110 microns 2.
Packaging/Assembly
Devices were packaged in standard 44-pin PLCC packages with J leads. All pins were
connected. Die attach was by a silver epoxy, and wirebonding used the thermosonic
method with gold wire.
No die coat was used and no heatsink was present.
4 - 10
®
PIN 1
The Altera EPM7032 EPLD circuit die. Mag. 55x.
®
section,
Mag. 11,000x
OXIDE
section,
Mag. 5700x
POLYCIDE
SELECT GATE (1N)
Mag. 2400x, 0°
SECTION
PGM
TUNNEL AREA
POLYCIDE
Altera EPM7032. SEM views of device structures.
TECHNOLOGY DESCRIPTION
LATTICE GAL22V10C EPLA
Introduction
Ref. report SCA 9406-337
These parts were packaged in 28-pin, J-lead, Plastic Leaded Chip Carriers (PLCCs), date
coded week 51 of 1993. All parts were fully functional production samples. This
architecture provides ten output logic macrocells guaranteed to be 100 percent field
programable and reportedly provide the highest performance available anywhere. Device
operate from a standard 5V power source.
See tables for specific dimensions and materials identification and see figures for
examples of physical structures.
Unusual/Unique Features
- Short gates (0.5 micron).
- Numerous mask modifications.
- Unique metal 2 perforation design.
Quality
Quality of process implementation was normal except for significant metal thinning in a
very few isolated areas.
In the area of layer patterning, both etch definition and control (depth) were good.
Alignment/registration was also good.
Packaging/assembly quality and workmanship was good as well.
Technology
These devices were made by a twin (multiple)-well CMOS process on a P substrate. No
evidence of an epi layer was found. Two levels of metal and one level of polysilicon
were used. A normal recessed-oxide isolation was employed. The cell array used a
single poly design with thin tunnel-oxide windows for programming.
4 - 11
Both metal levels consisted of aluminum and were defined by standard dry etch
techniques. Both used titanium-nitride cap layers. Only metal 1 used a titanium-nitride
barrier under the aluminum.
As mentioned, metal 2 structures were somewhat unique. Besides the fact that there was
evidence of many mask changes (such as isolated via contacts), the metal 2 power lines
contained a complex array of slots and cutouts. This is normally done for stress relief but
usually less elaborately.
No plugs were present at vias or contacts and no salicide source/drain treatment was
present. No buried contacts were used. Metal 2 contacted metal 1, and metal 1 contacted
diffusions and poly.
Planarization of the intermetal dielectric was by deposited glass layers and planarizing
etch. A spin-on-glass (SOG) was included. The dielectric under metal 1 was planarized
by a reflow process.
The single layer of polysilicon (no polycide) provided all gates and program elements. All
gates used oxide sidewall spacers that were left in place.
No evidence of unusual gate oxide or dielectric materials was found.
Overall minimum feature measured anywhere on these dice was the 0.5 micron poly
width.
Minimum physical gate lengths measured were 0.5 micron for N- channel and 0.65 micron
for P-channel.
Array Cell Structures
These parts used a 3 transistor, 2 capacitor cell and a thin tunnel oxide window design for
programming the macrocells.
Metal 1 was used for the word lines and Program 2 lines. Metal 2 provided Bit, Enable
and Program 1 lines. Poly was used for all gates and the capacitor areas on the floating
gates. Round, very thin tunnel oxide windows were used for programming. It is possible
that the capacitor and gate oxides are different thicknesses (would require TEM cross
sections to verify). Size of these programable cells was 197 microns2.
4 - 12
Packaging/Assembly
As mentioned, devices were packaged in standard 28-pin, J-lead PLCCs. All except
center pins on each side were connected. Die attach was by a silver epoxy and standard
thermosonic wirebonds using gold wire were used.
No evidence of a die coat was found.
4 - 13
®
PIN 1
The Lattice GAL22V10C EPLA circuit die. Mag. 73x.
®
METAL2
CUTOUTS
optical,
Mag. 500x, 0°
METAL 2
PASSIVATION
METAL 2
METAL 1
POLY
section,
Mag. 11,000x
OXIDE
TUNNEL OXIDE
N+
POLY
PGM 2
N+
Mag. 2600x, 0°
3
Lattice GAL22V10C. Optical and SEM views of device structures.
TECHNOLOGY DESCRIPTION
AMD PAL CE22V10H-5JC/5 EPLA
Introduction
Ref. report SCA 9403-333
These parts were packaged in 28-pin, J-lead, Plastic Leaded Chip Carriers (PLCCs), date
coded week 2 of 1994. All parts were fully functional production samples. This
architecture provides 10 programable macrocells with 10 nsec propagation delays
possible. Devices operate from a standard 5V power source.
See tables for specific dimensions and materials identification and see figures for
examples of physical structures.
Unusual/Unique Features
- None.
Quality
Quality of process implementation was normal. No significant areas of concern were
found.
In the area of layer patterning, etch definition was good and control (depth) was normal.
Alignment/registration was good except for the thin tunnel-oxide windows which
overlapped recessed oxide areas probably more than intended.
Packaging/assembly quality was also good.
Technology
These devices were made by a twin (multiple)-well CMOS process on a P substrate. No
evidence of an epi layer was found. Two levels of metal and one level of polysilicon
were used. A normal recessed-oxide isolation was employed. The cell array used a
single poly design with thin tunneling oxide windows for programming.
Both metal levels consisted of aluminum defined by standard dry etch techniques. Metal
2 used no cap or barrier layers, but metal 1 used a titanium-nitride barrier on a titanium
adhesion layer.
4 - 14
No plugs were present at vias or contacts and no salicide source/drain treatment was
present. No buried contacts were used. Metal 2 contacted metal 1, and metal 1 contacted
diffusions and poly.
Planarization of the intermetal dielectric was by deposited glass layers and planarizing
etch. A spin-on-glass (SOG) was included. The dielectric under metal 1 was planarized
by a reflow process.
The single layer of polysilicon (no polycide) provided all gates and program elements.
All gates used sidewall spacers that were removed after use.
No evidence of unusual gate oxide or dielectric materials was found, but some lifting was
noted at the edges of the gates. Also, as mentioned, tunnel oxide windows appeared
misaligned.
Overall minimum feature measured anywhere on these dice was the 0.7 micron poly
width.
Minimum physical gate lengths measured were 0.6 micron for both N- and P-channel.
Array Cell Structures
These parts used a 3 transistor, 1 capacitor cell design with a thin tunnel oxide window
for programming the macrocells.
As shown in the figures, alignment of the thin oxide windows left something to be
desired. The word lines were made with metal 2. Program 1, Enable and the bit lines
used metal 1. Poly provided the Program 2 lines and all gates.
Cell layout was not particularly efficient resulting in a cell size of 216 microns 2.
Packaging/Assembly
As mentioned, devices were packaged in standard 28-pin, J-lead PLCCs. All except the
center pins on each side were connected. Die attach was by a silver epoxy and standard
thermosonic wirebonds using gold wire were used.
No evidence of a die coat was found.
4 - 15
®
The AMD PALCE 22V10H-5JC/5 circuit die. Mag. 55x.
®
section, Mag. 10,000x
N+
ENABLE
POLY
Mag. 3000x, 0°
AMD PALCE 22V10H-5JC/5. SEM views of device structures.