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Thermal and Electrical Simulation of Smart
Power Circuits by Network Analysis
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The 17th International Symposium on Power Semiconductor Devices &ICs, ISPSD'05
Santa Barbara, California, USA
May 2005
Introduction
J. Teichmann, W. Kraus, F. Liebermann, G. Täschner, C. Wallner
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Atmel Germany, Theresienstraße 2, D 74072 Heilbronn, Germany, Phone: 0049 7131 67-0
e-mail: [email protected]
Simulation principle
Cross section of lateral power transistor on SOI
electrical inputs and outputs
electrical
network
o Spectre-based method is described for complex electrical-thermal transient simulations
o Packaged circuit is divided into numerous small columns
o A large electrical representation of the thermal network is formed (FEM method)
o The electrical circuit sends the dissipated power to the thermal network and receives the
temperature
o All grid points have individual temperatures
o All grid point devices of the system have the same temperature
o An EKV transistor model with temperature input and power output is used
o Transient simulations and measurements are compared
o Application in smart power circuits
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other
circuitry
power
dissipation
temperature
spatial
(thermal)
RC network
y
(top view)
PCB
Cross-section of a SOI lateral
power transistor
t
Thermal domain
Temperature
Heat flow
T / °C
P/W
E. Roger et al.: A 2GHz., 60 V –Class SOI-Power....,ISPSD‘03 (PS4P1.pdf):
Electrical domain
Voltage
M2
M1
V /V
Current
location of
transistor
or device
Thermal
resistance
heat
spreader
Thermal
Capacitance
Rth/ K/W
Cth / J/K
Resistance
Capacitance
R/W
n1
C/F
SB
D
SB
D
SB
D
Buried
oxide
Column Si
adhesive
Cu 70 ｵm
Heat generated by individual transistors has uniform power
dissipation
Lines of power dissipation
Package + PCB cross section
EKV transistor models
•
Only material data
and their dimensions
are implemented
temperature input
•
and
power output
D
v to v
A
symbol
14 slices Si
G
threshold
mobility
Tjunction
E5
E7
S7
• Non-linear bias-dependence of driftresistance on drain and gate voltage
• The model uses the formulation of this
bias dependence as given in [3].
• Combined non-linear drift-resistance with
a low-voltage MOS model for HVMOS
modelling.
• Core MOS model EKV-model [4] due to
its proven suitability for analogue design
• Reduced complexity compared to other
recent MOS models, whereas the driftresistance takes care of the HVMOSspecific effect of quasi-saturation.
Pdiss
Pulse measurement: 100 ns, 5 µs, 50 µs
Power
transistor

PCB
250 µm
250 µm
Used grid sizes:
Tambient
Transistor area: 0.12 mm², SOI, QFN48
BSIM versus EKV
S
lateral:13 µm, 50 µm, 250 µm
vertical: 8 layers, 18 layers (Si vertical: 83 µm, 18 µm)
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Example measurement vs. electro-thermal simulation
1.6
1.5
1.4
1.3
1.2
1.1
1.0
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0.7
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0.5
0.4
0.3
0.2
0.1
0.0
P
EKV: ~ 25 parameters
measured
201°C
100 ns
52 W, 423W/mm²
145 °C
5 µs
50 µs
201 °C
measurement
(temp. diode in
transistor middle)
11 mm²
20 W, 163W/mm²
100n
5u
Imax=8 A, P=24 W, VDS=3 V
50u
5
10
15
20
25
30
35
40
45
211°C simulation
 Check for short and medium term behaviour of
the electro-thermal model and thermal network
400 µs
simulated
simulated
junction
temperature,
centre of heating
transistor
90
temperature /°C
PCB
40
die
Heat spreader
Exposure time:
200-250
313 µs
150-200
100-150
0 ms
50 µm grid
180
180
160
160
160
140
140
140
140
73
200
67
150
61
200
55
100
49 s
s 150
50
43
12
9
1
3
37
100
31
50
120
120
120
100
100
100
100
80
80
80
60
60
60
40
40
40
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20
20
0
0
0
150
150
8
100
temperature /
50
°C
0
6
200
180
180
160
160
140
140
120
120
100
200
42 ms
200
180
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160
160
140
140
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120
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100
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60
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60
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40
40
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20
20
20
0
0
0
0
R9
R5
R1
Measured
temperature
profile,
PCB
50 K/50 µm
6.5 mm
2 x 21 W
6.5 mm
Impact on simulation accuracy:
Is the lateral and vertical grid sufficient?
Validity and availability of all used material constants
Thickness (tolerances!) of all layers
Accuracy of transistor models up to 300…400°C
Physical and electrical data of the actual measured sample
Time delay of temperature diodes (incl. cross talk) in µs range
Matching features of temperature diodes
Are leakage currents accurately included in models?
Impact of non ideal heat drill holes in the printed board
Accuracy of thermal mapping (snap shot or “sequential read”)
Accuracy of current probes
Note, the current of a device is a correct representation of the integral temperature of a device
Cu
Applications
12 V
o
o
o
o
0 ms
10 µm grid
5V
Lamp 1
40 ms
Lamp 2
0
15
9
n x 50 µm
9
Max temperature
gradient:
2
13
1
n x 50 µm
Accuracy (measurement versus simulation)
Si
die
Heat spreader
4
5
n x 250 µm
125 K/50 µm
12
10
200
11
3
14
250
7
5
52 ms
1
300
300-350
250-300
200-250
21
150-200
17
100-150
13
50-100
0-50
3
7
R13
R21
R17
R29
R25
R37
R33
350
n x 250 µm
0
temperature diode
Max temperature
gradient:
1
200 ms --> 344 s CPU
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7
250 µm grid
9
40
13
R45
simulation
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60
0
s
Linux, Dell precision 360, red head 7.3:
80
41 ms
200
25
19
0
15
11
13
9
n x 50 µm
R41
7
5
6
300
15
160
120
20 ms
79
250
19
180
97
250
20 HV transistors
200
180
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o
o
o
o
o
o
o
o
o
o
o
7 ms
3 ms
200
91
300
85
8866 phy_res 12283 resistors
1 ms
200
0-50
300
23 0
5.3W /mm
1000
200
50-100
8619 capacitors
660 W/mm²
switching on two 12 V 21 W lamps, 40 ms distant
250-300
PCB
65795 equations
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 simple optimisation of third order Cauer network by several simulation runs
Simulated temperature evolution on die and package
heat spreader
50 µm grid
18255 nodes
10
time / s
Power, max. 273 W
7
200ºC
50
1
 measured and modelled in realistic application (e.g. cooling)
6
250 µm grid
100
TempPT100/°C
simulation
s
200
IC
50
30
blackening
250
 The data were derived from the measured temperature evaluation caused by a
constant power source of the same size as the package (use the package itself)
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20
0.1
179 °C
 Long time temperature response dominated by the PCB
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PT100
Lateral temperature resolution 10 µm
temperature / °C
Heat spreader network
PCB network
die network
ms response
measured
Implementation of the thermal performance of a PCB
Thermal mapping versus simulation
350
 Easy creation of huge networks
B
Electro-thermal FEM simulation
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BSIM: ~ 100 parameters
Multiple grid simulation
n x 50 µm
Spectre
symbol
500 ms
or spatial thermal
network
5
3
B
µs response
Non linear Si heat conduction in Spectre: device “phy_res”. Polynomial, third degree
0
B
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[3] N. Hefyene “Bias-dependent drift resistance modelling for accurate DC and AC simulation of asymmetric HV-MOSFET”, SISPAD
2002, pp. 203-206
[4] M. Bucher, C. Lallement, C. Enz, F. Krummenacher “Accurate MOS modelling for Analog Circuit Simulation Using the EKV
Model”, ISCAS, 1996, pp. 703-706
see also: D.M. Binkley, C.E. Hopper, S.D. Tucker, B.C. Moss, J.M. Rochelle, and D.P. Foty: "A CAD Methodology for Optimizing
Transistor Current and Sizing in Analog CMOS Design",IEEE Trans. Computer-Aided Design, vol. 22, No. 2, Feb. 2003
whole package simulation
N7
W7
80
transistor
N6
E6
drain source voltage / V
T
350
S[0:7]
Cu
s5
u
Example output characteristics
Added terminals:
N5
S5
Si
E[0:7]
E4
W5
Si
W[0:7]
N4
S6
s4
2
Idrain/ A
Column presentation
E3
n4
PCB
Filled drill
holes
1
E2
W6
n5
IC and PCB
N3
Adhesive,
solder
2 *pitch
1500 ｵm
Cu 70 ｵm
S2
N[0:7]
s3
chip
SiO2
Si 250 ｵm
N2
S4
n3
Si
mould compound 450 ｵm
S1
S3
Si
s2
Au wire
E1
W2
s1
SB
x
Column Cu
N1
W1
W4
n2
Column pad
E0
W3
Pitch 5...8 µm
T
N0
S0
SiO2
Power in
T
W0
Si
Temp out
Power in
metallization
s0
BOX
chip
Temp out
mold
compound
t
n0
Si
I/A
Cu 200 ｵm
3 slices Si
n0
M3
s0
grid
°C  V
Column concept
15 mm SOI transistor 200 ms, 25 V, Pav=17 W
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Preliminary device size estimation in feasibility phase
Calculation of critical temperature rises
Package selection
Complex circuit simulations
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