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ECE 305 1) Spring 2015 ECE 305 Homework SOLUTIONS: Week 13 Mark Lundstrom Purdue University Measured IV data for an n-‐channel MOSFET are shown below. Relevant parameters for this MOSFET are: T = 300 K Oxide thickness: x0 = 2.2 nm Relative dielectric constant: K O = 4 Power supply voltage: VDD = 1.2 V Series resistances: RS = RD = 100 Ω − µm Actual channel length = 85 nm Assume that the MOSFET is 1 micrometer wide, W = 10−4 cm . ECE-‐305 1 Spring 2015 ECE 305 Spring 2015 HW Week 13 Solutions (continued) Answer the following questions: 1a) From the so-‐called “on-‐current”, I D (VGS = VDD ,VDS = VDD ) = 1.2 V , estimate the average velocity of electrons in the channel at the source end of the channel. (Note: You will need to correct for the effect of the series resistance as discussed in HW12.) Solution: υ (0) =
I ON
WQn (0) Qn (0) = Cox (VGS − I D RS − VT )
KOε o
Cox =
= 1.6 × 10−6 F cm 2 xo
(
)(
)
Qn (0) = 1.6 × 10−6 1.2 − 1120 × 10−6 × 100 − 0.26 = 1.32 × 10−6
12
-2
Qn (0) q 8.3× 10 cm I ON
1120 × 10−6
υ (0) =
= −4
= 8.5 × 106 cm/s WQn (0) 10 × 1.32 × 10−6
υ (0) = 8.5 × 106 cm/s 1b) From the linear region of operation, estimate the effective mobility of this MOSFET. Solution: At the highest gate voltage: RTOT = RCH + RS + RD = 340 Ω − µm
RCH = RTOT − RS + RD = ( 340 − 200 ) Ω − µm
RCH = 140 Ω − µm
Because the width is given as 1 micrometer, RCH = 140 Ω − µm . ID =
W µ nCox
(VGS′ − VT )VDS′
L
Assume very small VDS with a small I D , so the intrinsic gate voltage is about the applied gate voltage. ECE-‐305 2 Spring 2015 ECE 305 Spring 2015 HW Week 13 Solutions (continued) 1
RCH =
W µ nCox
(VGS − VT )
L
L
L
µn =
=
RCHWCox (VGS − VT ) RCHW Qn
Qn = −Cox (VGS − VT ) = −1.6 × 10−6 (1.2 − 0.28) = 1.47 × 10−6
µn =
L
8.5 × 10−7
=
= 412 cm2/V-‐s RCHW Qn 140 × 10−4 × 1.47 × 10−6
µ n = 412 cm 2 /V-s
2) Assume the square law theory of the MOSFET: W µ nCox ⎡
VD2 ⎤
V
−
V
V
−
0 ≤ VD < VDsat VG ≥ VT (
)
⎢
⎥ L ⎣ G T D 2 ⎦
2
W µ nCox
ID =
VG − VT ) VD ≥ VDsat VG ≥ VT (
2L
ID =
2a) Derive an expression for the electric field vs. position along the channel in the linear region of operation. Solution: The drain current is a drift current: I D ( y ) = W µ nQn ( y )E y ( y ) , where in the square law theory: Qn ( y ) = −Cox ⎡⎣VG − VT − V ( y ) ⎤⎦ . ECE-‐305 Equate this to the expression for the “linear region” current: W µ nCox ⎡
VD2 ⎤
I D ( y ) = W µ nQn ( y )E y ( y ) = I D =
⎢(V − V )V − ⎥
L ⎣ G T D 2 ⎦
2
⎡
VD ⎤
⎢(VG − VT )VD −
⎥
2 ⎦
1⎣
E y ( y) = −
L ⎡VG − VT − V ( y ) ⎤
⎣
⎦ 3 Spring 2015 ECE 305 Spring 2015 HW Week 13 Solutions (continued) For very small drain voltages, we can ignore VD2 2 , and Qn ( y ) ≈ −Cox (VG − VT ) , so E
y
( y) ≈ −
VD
L
VD << VG − VT which is just what we would expect for a resistor. 2b) Derive an expression for the electric field vs. position along the channel at VD = VDsat . Solution: Begin as in 2a). The drain current is a drift current: I D ( y ) = W µ nQn ( y )E y ( y ) , where in the square law theory: Qn ( y ) = −Cox ⎡⎣VG − VT − V ( y ) ⎤⎦
Equate this to the expression for the saturation region current: W µ nCox
2
I D ( y ) = W µ nQn ( y )E y ( y ) = I D =
VG − VT )
(
2L
2
1
⎡VG − VT − V ( y ) ⎤E y ( y ) = − (VG − VT ) electric field is gradient of voltage, so: ⎣
⎦
2L
2
dV
dV
1
− (VG − VT )
+V
= − (VG − VT )
dy
dy
2L
−
V ( y)
∫ (V
G
0
− VT ) dV +
V ( y)
∫
0
y
2
1
V dV = − (VG − VT ) ∫ dy
2L
0
which can be integrated to find: V 2 ( y)
2⎛ y⎞
1
− (VG − VT )V ( y ) +
= − (VG − VT ) ⎜ ⎟
2
2
⎝ L ⎠ or 2⎛ y⎞
V 2 ( y ) − 2 (VG − VT )V ( y ) + (VG − VT ) ⎜ ⎟ = 0
⎝ L⎠
Solve the quadratic equation for V(y): V ( y ) = (VG − VT ) ± (VG − VT ) 1− y / L
Choose the minus sign because V ( 0 ) = 0 and V ( L ) = VG − VT (drain end at pinch-‐
off). V ( y ) = (VG − VT ) ⎡1− 1− y / L ⎤
⎣
⎦ ECE-‐305 4 Spring 2015 ECE 305 Spring 2015 HW Week 13 Solutions (continued) Now we can find the electric field in the channel: (V − VT ) (1− y / L)−1/2
dV
E ( y) = −
=− G
dy
2L
−1/2
(V − V )
E ( y ) = − G T (1− y / L )
2L
Examine answer: At y = 0, we get (V − V )
E (0) = − G T
2L As y → L , E ( y → L ) → −∞ At the pinch-‐off point, the electric field approaches infinity and the inversion layer charge approaches zero. The product of the two is finite. This is a limitation of the simple theory that the velocity saturation model tries to fix. 3)
There is often a sheet of “fixed charge” at the oxide-‐semiconductor interface. (By fixed charge, we mean a charge that does not vary with surface potential, φS .) Assume a 1.5 nm thick oxide with a relative dielectric constant of 4.0. Answer the questions below. 3a) Assume that a fixed charge of QF q = 1011 cm -2 is present. Explain how the fixed charge shifts the threshold voltage. What is the direction of this shift (e.g. is it a positive or negative voltage shift?). Solution: The voltage drop across the oxide is changed by an amount: Q
ΔV = − F Cox
Cox =
K Oε 0 4.0 × 8.854 × 10−14
=
= 2.36 × 10−6 xo
1.5 × 10−7
ΔV = −
QF
1.6 × 10−19 × 1011
=−
= −6.8 × 10−3 V
−6
Cox
2.36 × 10
ΔV = −6.8 × 10−3 V This change in voltage drop acriss the oxide shifts VT . The shift is negative. If we are dealing with an N-‐MOSFET, then the threshold voltage will be a little smaller (less positive). If we are dealing with a P-‐MOSFET, the threshold voltage is also a little smaller, which means that the threshold voltage will be a little more negative. Charge at the oxide-‐Si interface reduces the magnitude of VT for N_MOSFETs and increases the magnitude of VT for P-‐MOSFETs. ECE-‐305 5 Spring 2015 ECE 305 Spring 2015 HW Week 13 Solutions (continued) Note that this is a fairly large charge by today’s standards. High quality gate oxides can have 10 times less fixed charge. In the late 1970’s, however, oxides were 100 nm thick and the corresponding shifts in voltage were much larger (~0.45 V) for this QF . (Do you see why?) 3b) In HW 1, we saw that the number of atoms per cm2 on a (100) Si surface is N S = 6.81× 1014 cm -2 . Assume each atom has one charged dangling bond, so a fixed charge of QF q = 6.81× 1014 cm -2 is present. How much is the voltage shift now? Solution: The voltage drop across the oxide is changed by an amount: Q
1.6 × 10−19 × 6.81× 1014
ΔV = − F =
= −46 V Cox
2.36 × 10−6
ΔV = −46 V This is an enormous shift in voltage. MOSFET technology would not be possible without the remarkable ability of SiO2 to passivate (e.g. neutralize) more than 99.9% of the dangling bonds. 4)
The gate electrode of an MOS capacitor is often a heavily doped layer of polycrystalline silicon with the Fermi level located at E F ≈ EC for an n+ polysilicon gate and E F ≈ EV for a p+ polysilicon gate. These heavily doped semiconductors act almost like metals. Sketch the following four equilibrium energy band diagrams: 4a) An n-‐type Si substrate ( N D = 1017 cm -3 ) with an n+ polysilicon gate. Solution: (first separated, then together) ECE-‐305 6 Spring 2015 ECE 305 Spring 2015 HW Week 13 Solutions (continued) A small electron transfer will occur from the gate to the semiconductor. The result is: Note: The semiconductor is accumulated. There is a little depletion of electrons in the polysilicon gate. This does not happen for a metal because there are so many 4b) An n-‐type Si substrate ( N D = 1017 cm -3 ) with a p+ polysilicon gate. Solution: (first separated, then together) Electrons will transfer from the semiconductor to the gate. ECE-‐305 7 Spring 2015 ECE 305 Spring 2015 HW Week 13 Solutions (continued) Note: The semiconductor is depleted. We again see some depletion in the polysilicon gate. 4c) A p-‐type Si substrate ( N A = 1017 cm -3 ) with an n+ polysilicon gate. Solution: (first separated, then together) Electrons will transfer from the gate to the semiconductor. ECE-‐305 8 Spring 2015 ECE 305 Spring 2015 HW Week 13 Solutions (continued) Note: The semiconductor is depleted. The polysilicon gate shows some depletion here too. 4d) A p-‐type Si substrate ( N A = 1017 cm -3 ) with a p+ polysilicon gate. Solution: (first separated, then together) A small electron transfer will occur from the semiconductor to the gate. Note: The semiconductor is accumulated. The polysilicon gate also depleted a little. 5) Compute the “metal”-‐semiconductor workfunction difference for each of the cases above. 5a) An n-‐type Si substrate with an n+ polysilicon gate. Solution: We must find the location of the Fermi level in the semiconductor. Begin with n0 = N D = N C e(
ECE-‐305 E FS − EC ) k BT
, which can be solved for 9 Spring 2015 ECE 305 Spring 2015 HW Week 13 Solutions (continued) ( EC − EFS ) = k BT ln ⎛ N C ⎞ N = 3.23× 1019 cm-3 ⎜⎝ N ⎟⎠ C
q
q
D
(E
C
− E FS
q
) = k T ln ⎛ N
B
q
⎞
⎜ N ⎟ = 0.026 ln 323 = 0.150 eV ⎝ D⎠
Φ MS = χ − χ + EC − E FS
{ (
( )
C
)} = − ( E
C
)
− E FS = − 0.150 eV Φ MS = −0.150 eV The work function difference is small, as can be seen in the energy band diagram of 4a). 5b) An n-‐type Si substrate with a p+ polysilicon gate. Solution E − E FS
= 0.150 eV We have the same Si substrate, so C
q
(
{ (
Φ MS = χ + EG − χ + EC − E FS
)
)} = 1.12 − 0.15 eV =0.97 eV Φ MS = 0.97 eV The work function difference is close to the bandgap of Si, as can be seen in the energy band diagram of 4b). Note: Since the left contact is a p-‐type semiconductor and the right contact is an n-‐type semiconductor, we can show that the magnitude of the built-‐in potential is given by the PN junction equation: k T ⎛N N ⎞
Φ MS q = B ln ⎜ A 2 D ⎟ q
⎝ ni ⎠
ECE-‐305 10 Spring 2015 ECE 305 Spring 2015 HW Week 13 Solutions (continued) 5c) A p-‐type Si substrate with an n+ polysilicon gate. Solution: p0 = N A = NV e(
(E
FS
− EV )
q
(E
FS
− EV
q
=
EV − E FS ) k BT
, which can be solved for k BT ⎛ NV ⎞
NV = 1.83× 1019 cm -3 ln ⎜
q
⎝ N A ⎟⎠
) = k T ln ⎛ N
B
q
{
⎞
V
⎜ N ⎟ = 0.026 ln 183 = 0.135 eV ⎝ A⎠
( )
(
Φ MS = χ − χ + EG − E FS − EV
)} = − E + ( E
G
FS
)
− EV = −0.985 eV Φ MS = −0.985 eV The work function difference is very large in magnitude, as can be seen I the energy band diagram of 4c). 5d) A p-‐type Si substrate with a p+ polysilicon gate. Solution: The same p-‐type substrate, so: E FS − EV
= 0.135 eV q
(
)
{
(
Φ MS = χ + EG − χ + EG − E FS − EV
)} = ( E
FS
)
− EV = 0.135 eV Φ MS = 0.135 eV ECE-‐305 The work function difference is very small in magnitude, as can be seen in the energy band diagram of 4d). 11 Spring 2015