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Functional and Timing Abstraction Patricia Renault Pirouz Bazargan Sabet Pirouz Bazargan Sabet ValMem - March 2007 Outline Functional Abstraction Timing Model Delay Evaluation Pirouz Bazargan Sabet ValMem - March 2007 Introduction Layout Layout Extraction Extraction Netlist Tr, C, R Netlist Tr Netlist C, R Abstraction Abstraction Abstraction Netlist of Gates, C, R Netlist of Gates Netlist C, R Pirouz Bazargan Sabet ValMem - March 2007 Functional Abstraction Aim : Recongnize gates from transistors network Pirouz Bazargan Sabet ValMem - March 2007 Functional Abstraction Classic Method : Pattern Matching pattern circuit Pirouz Bazargan Sabet ValMem - March 2007 Functional Abstraction Classic Method : Pattern Matching Classic algorithm Speed up using signature comparison Require to know the circuit Not adapted to custom designs Does not respect the electrical point of view Pirouz Bazargan Sabet ValMem - March 2007 Functional Abstraction Formal Method Recognize the function of a transistor structure Electrical point of view - Current trace Pirouz Bazargan Sabet ValMem - March 2007 Functional Abstraction follow the current paths a b a b Transistor structure is not enough Functional analysis is required Pirouz Bazargan Sabet ValMem - March 2007 Functional Abstraction a b a b Fup =b+a Fdown = a . b Fup = Fdown Pirouz Bazargan Sabet ValMem - March 2007 Functional Abstraction c a d b Fup = a.c + b.d Fdown = a.c + b.d Pirouz Bazargan Sabet Fup . Fdown = c.d.(a⊕b) co Fup + Fdown = c.d tr t c i nf l te a t i-s ValMem - March 2007 Functional Abstraction c a d b c=d Fup . Fdown = c.d.(a⊕b) co Fup + Fdown = c.d Pirouz Bazargan Sabet tr t c i nf l te a t i-s ValMem - March 2007 Functional Abstraction c a d b Pirouz Bazargan Sabet ValMem - March 2007 Functional Abstraction Formal Method : problems How far I have to explore ? Apparition of loops Pirouz Bazargan Sabet ValMem - March 2007 Functional Abstraction Formal Method : Loops A loop is the signature of a memory point Break point in the backward exploration Pirouz Bazargan Sabet ValMem - March 2007 Functional Abstraction Formal Method : Identifying a memory point xi = f (x1,..., xi ,..., xn) = xi . fi1 + xi . fi0 ∂f = fi0 xor fi1 = fi1 .fi0 + fi1 .fi0 ∂x i fi1 .fi0 and fi1 .fi0 cannot be 1 for a given input configuration Pirouz Bazargan Sabet ValMem - March 2007 Functional Abstraction Formal Method : Identifying a memory point f = xi . fi1 + xi . fi0 if fi1 .fi0 (v) = 1, f varies in direct way with xi f is a positive function of xi if fi1 .fi0 (v) = 1, f varies in opposite way with xi f is a negative function of xi ∂f + = fi1 .fi0 ∂x i Pirouz Bazargan Sabet ∂f − = fi1 .fi0 ∂x i ValMem - March 2007 Functional Abstraction Formal Method : Identifying a memory point f = xi . fi1 + xi . fi0 for a memory point ∂f − ∂f + = fi1 .fi0 ≠ 0 ∂x i Pirouz Bazargan Sabet ∂x i = fi1 .fi0 ≡ 0 ValMem - March 2007 Functional Abstraction Formal Method : Identifying a memory point Formal analysis cannot identify memory points usig electrical conflicts Pirouz Bazargan Sabet ValMem - March 2007 Outline Functional Abstraction Timing Model Delay Evaluation Pirouz Bazargan Sabet ValMem - March 2007 Timing Model xi y How to abstract each gate from the timing point of view STG (State Transition Graph) Pirouz Bazargan Sabet ValMem - March 2007 Timing Model Unique delay model consider the transitions of y xi y 1 0 the worst case delay is attributed to each transition Pirouz Bazargan Sabet ValMem - March 2007 Timing Model Unique delay model worst case delays cannot be summed xi Pirouz Bazargan Sabet y z ValMem - March 2007 Timing Model Input-output delay model consider the transitions of y with respect to xi N 4-state graphs for an N-input gate Pirouz Bazargan Sabet ValMem - March 2007 Timing Model Input-output delay model consider the transitions of y with respect to xi xi 00 01 10 11 y the worst case delay is attributed to each transition Pirouz Bazargan Sabet ValMem - March 2007 Timing Model Input-output delay model worst case delays cannot be summed in case of correlations xi Pirouz Bazargan Sabet y z ValMem - March 2007 Timing Model Complete STG delay model consider the transitions of y with respect to the transition of the configuration xi 1 2N-state graph for an N-input gate Pirouz Bazargan Sabet ValMem - March 2007 Outline Functional Abstraction Timing Model Delay Evaluation Pirouz Bazargan Sabet ValMem - March 2007 Delay Evaluation How to characterize the delay of a transition Pirouz Bazargan Sabet ValMem - March 2007 Delay Evaluation Accurate delay using electrical simulation xi y Electrical simulation (Spice) of each configuration Pirouz Bazargan Sabet ValMem - March 2007 Delay Evaluation Analytic delay using a transistor model ids = −C dv dt choose a transistor model (ids ) and resolve the differential equation Pirouz Bazargan Sabet ValMem - March 2007
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