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Prof.R.S.Kakade (Sub- Electronics) Chapter no. 6 Field Effect Transistor (10 Marks) (Unipolar Transistor) Introduction: The field effect transistor is a three terminal semiconductor device. In which current conduction is by one type of carrier only, i.e. holes or electrons. This conduction of current is controlled by means of electric field between the gate electrode and the conducting channel of the device. Hence it is called field effect transistor. It has high i/p impedance and low noise level. It was invented in 1960. Types of FET: The field effect transistor are classified as follows.. MOSFET stands for Metal Oxide Semiconductor Field Effect Transistor. FET: symbol: n channel FET p channel FET The above fig. shows the symbol for n channel FET and P channel FET. The FET has three terminal named as, drain (D) source (S) and gate G out of which gate is acting as a controlling terminal. Working Principle of n channel FET: The structure of n channel FET is as shown in above fig. 2nd Sem/CM/IF Field Effect Transistor 1 Prof.R.S.Kakade (Sub- Electronics) A semiconductor bas of n type material is taken and contacts are made of the two ends of tje bar called as Drain and source. On both sides of n type bas a heavily doped (P) regions have been formed by diffusion to create p-n junction both these P+ region are connected together and contact is made is called gate terminal of FET. Operation: . As shown in above fig. the supply voltage is connected between source and drain terminal of JFET called as VDS and reverse voltage is applied between G and S terminal of JFET called as VGS. When VDS is applied between drain and source terminal the electrons will flow from source to drain through a n type channel. This flow of electrons makes the drain current ID as VGS = 0 there is no depletion region, there is flow of current easily through n channel bar. When a reverse voltage applied between gate and source is increased the width of depletion region, increases as shown in fig. This reduces the width of conducting channel, there by increasing the resistance of n type bar. Thus the current from source to drain is decreased. Thus we can conclude as the reverse voltage VGS increases the drain current ID decreases and when VGS decreased the drain current increases. So it is clear that drain current i.e. current from source to drain can be controlled by the application of potential ( i.e. electric field) on the gate, for this region the device is called as FET. 2nd Sem/CM/IF Field Effect Transistor 2 Prof.R.S.Kakade (Sub- Electronics) Characteristics of FET: The V-I characteristics of JFET transistor is graph of drain current ID versus Drain to source voltage VDS at different value of gate to source voltage VGS value is taken on X axis and ID is taken on y-axis. The chara. of JFET has been divided into three region i.e. cutoff, sat and ohmic region. When VGS = 0 and VDS also zero, the channel is entirely open, drain current is zero as there is no source of electron. As we increase the VDS current ID increases linearly with voltage VDS as shown in chara. This region to the left or point A of the curve is called ohmic region. In this region bar acts as simple resistor, Because of simple resistor there is voltage drop in the bar due to drain channel iD. The voltage drop along the length of channel reverse biases the gate junction. Because of reverse bias of gate junction depletion width increases and this width is not uniform it increases more at the drain ends as we starts increasing VDS the depletion region width meets to each other. Therefore, the current iD no more longer increases. It approaches constant value shown in fig. above by AB called as sat region or pinch off region. The voltage VDS at which the free charges from the channel are removed is called as pinch off voltage. Further increases in voltage VDS the reverse bias across the gate junction increases and at high VDS break down gate unction across the drain current id shorts to high value as shown by dotted area. If we increase gate reverse voltage from 0v to – 1v the curve shifts downwards. The pinch off occurs for small value of VDS. Circuit dia. for drain chara. 2nd Sem/CM/IF Field Effect Transistor 3 Prof.R.S.Kakade (Sub- Electronics) Drain resistance: Dynamic drain resistance at operating point is defined as the ratio of small change in drain to source voltage to the corresponding change in drain current at constant, at a constant value of gate to source voltage. Rd = VDS iD at constant VGS. Transconductance (gm): The ratio of change in drain current to the corresponding change in gate to source voltage, at a constant value of drain to source voltage. (Or) Mutual conductance: The mutual conductance at an operating point is defined as the ratio of small change in drain current to the small change in gate voltage, keeping the drain voltage constant. That is gm = iD VGS at VDS = constant Amplification factor : It is defined, as ratio of small change in drain voltage to the small change in gate voltage, current ID, is kept constant. That is gm = = VDS VGS at ID = constant The relation between above parameter is = rd x gm Comparison of BJT and FET Sr. BJT no. 1 BJT is a current controlling device 2 BJT is a bipolar device current flows due to both minority and majority carriers. 3 Low input impedance 4 Noise generated by BJT is high. 5 Thermal runaway can damaged the BJT 6 BJT is bigger in size. 7 Transfer chara. is linear 2nd Sem/CM/IF Field Effect Transistor FET FET is a voltage controlled device FET is unipolar device, current flows due to the majority carriers. High input impedance Noise generated by BJT is low. Thermal runaway does not occurs. FET is smaller in size. Transfer chara. in non-linear. 4 Prof.R.S.Kakade (Sub- Electronics) MOSFET: MOSFET is the short form of Metal Oxide Semiconductor Field Effect Transistor. There are three types of MOSFET, 1) Depletion type MOSFET 2) Enhancement type MOSFET 3) Power MOSFET Symbol of n channel depletion type of MSOFET Symbol of p channel depletion type of MOSFET Simplified symbol N channel P channel As shown in fig. type of P semiconductor material is used as substrate. The substrate is intentionally connected to source terminal termed as ‘SS’. The drain and source terminals are connected to the n type of regions through the metallic regions. The n type regions are linked with each other by a n channel as shown in fig. The gate terminal is insulated from the n channel by a thin silicon dioxide layer (Sio2) Due to presence of the sio2 layer between gate terminal and n type channel the i/p impedance of MOSFET is very high. 2nd Sem/CM/IF Field Effect Transistor 5 Prof.R.S.Kakade (Sub- Electronics) When VGS = 0 v as gate source and substrate are connected together and to the ground. Thus VGS = 0 A positive voltage VDD id applied between drain and source. Due to the positive voltage applied to drain terminal free electrons from the channel are attracted to the drain and the drain current starts flowing labeled as IDSS When VGS is negative:Due to negative voltage applied between gate and source. The gate will tend to repel the free electrons towards the p type substrate and attract the holes from substrate. Therefore there is recombination of electron and holes in side channel. This will reduce the no free electrons from n channel available for conduction. Therefore the drain current will decrease with increases in negative value of VGS. Enhancement type MOSFET: Fig. Symbol of n and p channel enhancement MOSFET The fig shows the construction of n channel enhancement MOSFET. In this type MOSFET a slab of p type semiconductor is used as substrate. The drain and source terminal are connected to n type doped regions through a metallic contacts. But most important point is that the channel is absent here sio2 layer is still present for insulating Gate terminal from the substrate. Operation: 2nd Sem/CM/IF Field Effect Transistor 6 Prof.R.S.Kakade (Sub- Electronics) When VGS = 0 and positive voltage is applied between its drain and source due to absence of n type channel a zero drain current will result. When VGS is positive and VDS positive the positive potential at Gate terminal will repel the holes present in the p type substrate. This resulting in creation of depletion region near Sio2 insulating layer, but minority carriers i.e electrons in p type substrate will be attracted towards gate terminal and gather near the surface of Sio2 as shown in fig. As we increases the VGS the no. of electrons gathering near the Sio2 layer will increases. The electrons concentration near Sio2 layer increases to such extent that it creates the n type doped regions. The drain current then starts flowing through this induced channel. The value of VGS at which this conduction begins is called as threshold voltage indicated by VT. Application of FET: 1) IT can be used as an amplifier. 2) It can be used as a switch. 3) IT can be used as analog switch in circuits, like sample and hold, Amplitude Modulation, ADC/DAC (Analog to digital or Digital to analog) converters. 4) As a voltage variable resistor (VVR). 5) In Digital circuits. Applications of MOSFET: 1) 2) 3) 4) 5) 6) It can be linear amplifier As an inverter As an active load CMOS inverter In the digital circuits AS a switch. 2nd Sem/CM/IF Field Effect Transistor 7