Download EE247 Lecture 16 Current Source DAC Unit Element

EE247
Lecture 16
D/A converters continued:
•
•
•
•
•
Current based DACs-unit element versus binary weighted
Static performance
– Component matching-systematic & random errors
Practical aspects of current-switched DACs
Segmented current-switched DACs
DAC self calibration techniques
– Current copiers
– Dynamic element matching
ADC Converters
• Sampling
– Sampling switch induced distortion
– Sampling switch charge injection
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 1
Current Source DAC
Unit Element
……………
Iref
……………
•
•
•
•
•
Iout
Iref
Iref
Iref
“Unit elements ”
2B-1 current sources & switches
Monotonicity does not depend on element matching
Suited for both MOS and BJT technologies
Output resistance of current source causes gain error
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 2
Current Source DAC
Unit Element
R
……………
Vout
+
Iref
……………
•
Iref
Iref
Iref
Output resistance of current source à gain error problem
à Use transresistance amplifier
- Current source output held @ virtual ground
- Error due to current source output resistance eliminated
- New issues: offset & speed of the amplifier
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 3
Current Source DAC
Binary Weighted
……………
2B-1 Iref
……………
Iout
4 Iref
2Iref
Iref
• “Binary weighted”
• B current sources & switches (2B-1 unit current
sources but less # of switches)
• Monotonicity depends on element matching
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 4
Static DAC INL / DNL Errors
• Component matching
• Systematic errors
–
–
–
–
Finite current source output resistance
Contact resistance
Edge effects in capacitor arrays
Process gradient
• Random errors
– Lithography
– Often Gaussian distribution (central limit
theorem)
*Ref: C. Conroy et al, “Statistical Design Techniques for D/A Converters,” JSSC Aug. 1989, pp.
1118-28.
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 5
Probability density p(x)
Gaussian Distribution
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
( x−µ )
2
p( x ) =
1
2πσ
−
e
2σ
-3
-2
-1
0
1
2
3
x /σ
2
where standard deviation : σ = E( x2 ) − µ 2
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 6
P (− X ≤ x ≤ + X ) =
=
1
+X −
2π
−X
∫
e
x2
2 dx
Probability density
p(x)
Yield
P(-X ≤ x ≤ +X)
 X 
= erf 

 2
0.4
0.3
0.2
0.1
0
1
0.8
0.6
0.4
0.2
0
95.4
68.3
38.3
0
0.5
1
1.5
2
2.5
3
X
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 7
Yield
X/σ
0.2000
0.4000
0.6000
0.8000
1.0000
1.2000
1.4000
1.6000
1.8000
2.0000
P(-X ≤ x ≤ X) [%]
15.8519
31.0843
45.1494
57.6289
68.2689
76.9861
83.8487
89.0401
92.8139
95.4500
EECS 247 Lecture 16: Data Converters
X/σ
2.2000
2.4000
2.6000
2.8000
3.0000
3.2000
3.4000
3.6000
3.8000
4.0000
P(-X ≤ x ≤ X) [%]
97.2193
98.3605
99.0678
99.4890
99.7300
99.8626
99.9326
99.9682
99.9855
99.9937
© 2005 H.K. Page 8
Example
• Measurements show that the offset voltage of
a batch of operational amplifiers follows a
Gaussian distribution with σ = 2mV and µ = 0.
• Fraction of opamps with |Vos| < 6mV:
– X/σ = 3
à 99.73 % yield
• Fraction of opamps with |Vos| < 400µV:
– X/σ = 0.2 à 15.85 % yield
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 9
Component Mismatch
Example: Side-by-side resistors
…….
Large # of devices
measured & curved à
typically if sample size is
large shape is Gaussian
No. of resistors
…….
400
300
∆R
200
R
100
0
988
992
996
1000
1004
1008 1012
R[ Ω ]
E.g. Let us assume in this example large # of Rs with
average of 1000OHM measured:
68.5% within +-4OHM or +-0.4% of average
à 1σ for resistorsà 0.4%
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 10
Probability density p(x)
Component Mismatch
Two side-by-side
Resistors
R=
R1 + R2
2
0.4
0.35
0.3
0.25
∆R
0.2
R
0.15
0.1
0.05
0
−3σ −2σ
dR = R1 − R2
σ d2R ∝
R
−σ
0
σ
2σ
For typical technologies & geometries
1σ for resistorsà 0.02 το 5%
1
Area
3σ
dR
R
In the case of resistors σ is a function of area
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 11
DNL Unit Element DAC
E.g. Resistor string DAC:
Vref
∆ = Rmedian I ref
Iref
∆i = Ri I r e f
DNLi =
=
∆median − ∆i
∆median
Ri − R
median
R
median
=
dR
R
median
≈
dR
Ri
∆i = Ri I ref
σ DNL = σ d Ri
Ri
DNL of unit element DAC is
independent of resolution!
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 12
DNL Unit Element DAC
E.g. Resistor string DAC:
Example:
If σdR/R = 0.4%, what
DNL spec goes into
the datasheet so that
99.9% of all converters
meet the spec?
σ DNL = σ d R
i
Ri
DNL of unit element DAC is independent of resolution!
Note similar results for all unit-element based DACs
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 13
Yield
X/σ
0.2000
0.4000
0.6000
0.8000
1.0000
1.2000
1.4000
1.6000
1.8000
2.0000
P(-X ≤ x ≤ X) [%]
15.8519
31.0843
45.1494
57.6289
68.2689
76.9861
83.8487
89.0401
92.8139
95.4500
EECS 247 Lecture 16: Data Converters
X/σ
2.2000
2.4000
2.6000
2.8000
3.0000
3.2000
3.4000
3.6000
3.8000
4.0000
P(-X ≤ x ≤ X) [%]
97.2193
98.3605
99.0678
99.4890
99.7300
99.8626
99.9326
99.9682
99.9855
99.9937
© 2005 H.K. Page 14
DNL Unit Element DAC
Example:
If σdR/R = 0.4%, what DNL spec
goes into the datasheet so that
99.9% of all converters meet
the spec?
E.g. Resistor string DAC:
σ DNL = σ d R
i
Ri
Answer:
From table: for 99.9%
à X/σ = 3.3
σDNL = σdR/R = 0.4%
3.3 σDNL = 1.3%
àDNL= +/- 0.013 LSB
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 15
DAC INL Analysis
Output [LSB]
N
B
E
n
A
n
N=2B-1
Input [LSB]
A=n+E
Ideal
n
B=N-n-E
N-n
Variance
n.σε2
(N-n).σε2
E = A-n
r =n/N
N=A+B
= A-r(A+B)
= A (1-r) -B.r
à Variance of E:
σE2 =(1-r)2 .σΑ2 + r 2 .σB2
=N.r .(1-r).σε2
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 16
DAC INL
n

σ E 2 = n  1 −  ×σ ε 2
 N
To find m a x . v a r i a n c e :
→ n=N/2
•
dσ E 2
dn
=0
Error is maximum at mid-scale (N/2):
σ INL =
1
2B − 1 σ ε
2
with N = 2 B − 1
•
INL depends on DAC resolution and element matching σε
•
While σDNL = σε
Ref: Kuboki et al, TCAS, 6/1982
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 17
Untrimmed DAC INL
Example:
σ INL ≅
1 B
2 −1 σε
2
σ 
B ≅ 2 + 2 log2  INL 
 σε 
EECS 247 Lecture 16: Data Converters
Assume the following requirement:
σINL = 0.1 LSB
Then:
σε = 1%
σε = 0.5%
σε = 0.2%
σε = 0.1%
à
à
à
à
B = 8.6
B = 10.6
B = 13.3
B = 15.3
© 2005 H.K. Page 18
Simulation Example
12 Bit converter DNL and INL
DNL [LSB]
2
1
-0.04 / +0.03 LSB
0
-1
500
1000
1500 2000 2500 3000 3500 4000
σε = 1%
B
= 12
Random #
generator used
in MatLab
bin
INL LSB]
2
1
-0.2 / +0.8 LSB
Computed INL:
0
-1
500
1000
1500 2000 2500 3000 3500 4000
σDNL = 0.01 LSB
σINL = 0.3 LSB
(midscale)
bin
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 19
Binary Weighted DAC INL/DNL
• INL same as for unit element
DAC
• DNL depends on transition
– Example:
0 to 1 àσDNL2 = σ(dΙ/Ι) 2
1 to 2 à σDNL2 = 3σ(dΙ/Ι) 2
• Consider MSB transition:
0111 … à 1000 …
EECS 247 Lecture 16: Data Converters
Iout
2B-1 Iref
……………
4 Iref
2Iref
Iref
© 2005 H.K. Page 20
MOS Device Matching Effects
Id =
Id1 + Id 2
2
Id1
dId Id1 − Id 2
=
Id
Id
Id2
dId
dW L
dVth
=
+
W
Id
VGS −Vth
L
• Current matching depends on:
- Device W/L ratio matching
à Larger device area less mismatch effect
- Threshold voltage matching
à Larger gate-overdrive less threshold voltage mismatch effect
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 21
Current-Switched DACs in CMOS
Iout
Iref
d Id
Id
=
dW L
W
L
+
Switch Array
d Vth
……
VG S −Vth
256
•Advantages:
Can be very fast
Small area for < 9-10bits
128
64 ………..…..1
Example: 8bit Binary Weighted
•Disadvantages:
Accuracy depends on device W/L & Vth matching
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 22
Binary Weighted DAC DNL
•
Worst-case transition occurs at
mid-scale:
15
(
)
(
)
σDNL2/ σε2
2
σ DNL
= 2B−1 − 1 σε2 + 2B−1 σε2
10
144244
3
14243
0111...
1000...
≅ 2Bσε2
σ DNLmax = 2B / 2σε
5
σ I N Lmax ≅
•
0
2
4
6
8
10
12
14
1
2
2B − 1 σ ε ≅
1
2
σ DNLmax
Example:
B = 12, σε = 1%
DAC input code
EECS 247 Lecture 16: Data Converters
à σDNL = 0.64 LSB
à σINL = 0.32 LSB
© 2005 H.K. Page 23
“Another” Random Run …
DNL and INL of 12 Bit converter
DNL [LSB]
2
-1 / +0.1 LSB,
1
Now (by chance) worst
DNL is mid-scale.
0
-1
-2
500 1000 1500 2000 2500 3000 3500 4000
bin
Close to statistical result!
INL [LSB]
2
-0.8 / +0.8 LSB
1
0
-1
500 1000 1500 2000 2500 3000 3500 4000
bin
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 24
Unit Element versus Binary Weighted DAC
Unit Element DAC
Binary Weighted DAC
σ D N L = σε
σ DNL ≅ 2
B
2σ
σ INL ≅ 2
B
2 −1
σ INL ≅ 2
B
2 −1 σ
ε
ε = 2σ INL
σε
Number of switched elements:
S=B
S = 2B
Key point: Significant difference in performance and complexity!
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 25
Unit Element versus Binary Weighted DAC
Example: B=10
Unit Element DAC
Binary Weighted DAC
σ DNL = σ ε
σ DNL ≅ 2 2σ ε = 3 2σ ε
σ INL ≅ 2
B
2
B
−1
σ ε = 16σ ε
σ INL ≅ 2
B
2
−1
σ ε = 16σ ε
Number of switched elements:
S = 2B = 1024
S = B = 10
Significant difference in performance and complexity!
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 26
DAC INL/DNL Summary
• DAC architecture has significant impact on DNL
• INL is independent of DAC architecture and requires
element matching commensurate with overall DAC
precision
• Results are for uncorrelated random element
variations
• Systematic errors and correlations are usually also
important
Ref: Kuboki, S.; Kato, K.; Miyakawa, N.; Matsubara, K. Nonlinearity analysis of resistor string A/D
converters. IEEE Transactions on Circuits and Systems, vol.CAS-29, (no.6), June 1982. p.383-9.
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 27
Segmented DAC
•
Objective:
Compromise between unit element and binary weighted DAC
MSB (B1 bits)
(B2 bits)
…
…
LSB
Unit Element Binary Weighted
•
•
•
•
Approach:
B1 MSB bits à unit elements
B2 LSB bits à binary weighted
VAnalog
BTotal = B1+B2
INL: unaffected
DNL: worst case occurs when LSB DAC turns off and one more MSB
DAC element turns on- same as binary weighted DAC with B2+1 bits
Number of switched elements: (2B1-1) + B2
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 28
Comparison
Example:
B = 12, B1 = 5,
B1 = 6,
B2 = 7
B2 = 6
MSB
( B2 +1)
σ DNL ≅ 2
σ INL ≅ 2
B
2
LSB
2
σ ε = 2σ INL
−1
σε
S = 2B1 − 1 + B2
σε = 1%
DAC Architecture
Unit element (12+0)
Binary weighted(0+12)
Segmented (5+7)
Segmented (6+6)
σINL[LSB]
σDNL[LSB]
# of switched
elements
0.32
0.32
0.32
0.32
0.01
0.64
0.16
0.113
4095
12
31+7=38
63+6=69
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 29
Practical Aspects
Current-Switched DACs
•
•
•
•
Unit element DACs ensure monotonicity by turning
on equal-weighted current sources in succession
Typically current switching performed by differential
pairs
Based on the code only one of the diff. pair devices
are onà device mismatch not an issue
Issue: While binary weighted DAC can use the
incoming binary digital code directly, unit element
requires a decoder
à N to (2N-1) decoder
Binary
Thermometer
000
0000000
001
0000001
010
0000011
011
0000111
100
0001111
101
0011111
110
0111111
111
1111111
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 30
Segmented
Current-Switched DAC
• 4-bit MSB Unit
element DAC +
4-bit binary
weighted DAC
• Note: 4-bit MSB
DAC requires
extra 4-to-16 bit
decoder
• Digital code for
both DACs
stored in a
register
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 31
Segmented Current-Switched DAC
Cont’d
•
•
•
4-bit MSB
Unit element
DAC + 4-bit
binary
weighted
DAC
Note: 4-bit
MSB DAC
requires extra
4-to-16 bit
decoder
Digital code
for both
DACs stored
in a register
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 32
Segmented Current-Switched DAC
Cont’d
•
Domino Logic
MSB Decoder
à Domino logic
à Example: D4,5,6,7=1
OUT=1
•
Register
à Latched NAND gate:
à CTRL=1 OUT=INB
IN
Register
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 33
Segmented Current-Switched DAC
Reference Current Considerations
• Iref is
referenced to
VDD
à Problem:
Reference
current
varies with
supply
voltage
EECS 247 Lecture 16: Data Converters
+
-
© 2005 H.K. Page 34
Segmented Current-Switched DAC
Reference Current Considerations
• Iref is
referenced to
VssàGND
+
-
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 35
Segmented Current-Switched DAC
Considerations
•
•
Example: 2-bit MSB
Unit element DAC +
3-bit binary
weighted DAC
To ensure
monotonicity at the
MSBà LSB
transition: First OFF
MSB current source
is routed to LSB
current generator
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 36
Dynamic DAC Error: Glitch
•
Ideal
10
DAC output depends on
timing
5
0
Plot shows situation where
– LSB/MSBs on time
– LSB early, MSB late
– LSB late, MSB early
Early
•
Consider binary weighted
DAC transition 011 à 100
10
1
1.5
2
2.5
3
1
1.5
2
2.5
3
1
1.5
2
2.5
3
5
0
10
Late
•
5
0
Time
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 37
Glitch Energy
•
Glitch energy (worst case) proportional to: dt x 2B-1
dt à error in timing & 2B-1 associated with half of the switches
changing state
LSB energy proportional to: T=1/fs
•
Need dt x 2B-1 << T or dt << 2-B+1 T
•
Examples:
•
•
fs [MHz]
B
dt [ps]
1
20
1000
12
16
10
<< 488
<< 1.5
<< 2
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 38
DAC Reconstruction Filter
B
• Need for and
requirements depend
on application
fs/2
DAC Input
1
0.5
0
0
0.5
1
1.5
2
2.5
sinc
– Correct for sinc distortion
– Remove “aliases”
(stair-case
approximation)
x 10
0.5
0
DAC Output
• Tasks:
3
6
1
0
0.5
1
1.5
2
2.5
3
6
1
x 10
0.5
0
0
0.5
1
1.5
Frequency
EECS 247 Lecture 16: Data Converters
2
2.5
3
6
x 10
© 2005 H.K. Page 39
Reconstruction Filter Options
D igital
F ilter
DAC
SC
Filter
ZOH
CT
F ilter
• Digital and SC filter possible only in combination with
oversampling (signal bandwidth B << fs/2)
• Digital filter
– Bandlimits the input signal à prevent aliasin
– Could also provide high-frequency pre-emphasis to
compensate in-band sinc amplitude droop associated with
the inherent DAC ZOH function
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 40
DAC Implementation Examples
•
Untrimmed segmented
– T. Miki et al, “An 80-MHz 8-bit CMOS D/A Converter,” JSSC
December 1986, pp. 983
– A. Van den Bosch et al, “A 1-GSample/s Nyquist Current-Steering
CMOS D/A Converter,” JSSC March 2001, pp. 315
•
Current copiers:
– D. W. J. Groeneveld et al, “A Self-Calibration Techique for
Monolithic High-Resolution D/A Converters,” JSSC December
1989, pp. 1517
•
Dynamic element matching:
– R. J. van de Plassche, “Dynamic Element Matching for HighAccuracy Monolithic D/A Converters,” JSSC December 1976, pp.
795
EECS 247 Lecture 16: Data Converters
8x8 array
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 41
2µ tech., 5Vsupply
6+2 segmented
© 2005 H.K. Page 42
Two sources of systematic error:
- Finite current source output resistance
- Voltage drop due to finite ground bus resistance
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 43
Current-Switched DACs in CMOS
I1 = k (VGSM 1 −Vth )
VGSM 2 = VGSM 1 − 3RI
VGSM 3 = VGSM 1 − 5RI
VGSM 4 = VGSM 1 − 6RI
2
Iout
3RI 

2
I 2 = k (VG SM 2 −Vth ) = I1  1 −

V
G SM 1 −Vth 

2I1
gmM 1 =
VGSM 1 − Vth
VDD
2
M1
I1
M2
I2
M3
I3
M4
I4
2
 3RgmM 1 
→ I 2 = I1  1 −
 ≈ I1 (1 − 3RgmM 1 )

2 
2
 5RgmM 1 
→ I3 = I1  1 −
 ≈ I1 (1 − 5RgmM 1 )

2 
2
 6RgmM 1 
→ I 4 = I1  1 −
 ≈ I1 (1 − 6RgmM 1 )

2 
3RI
2RI
RI
Example: 4 unit element current sources
•Assumption: RI is small compared to transistor gate overdrive
à Desirable to have gm small
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 44
(5+5)
More recent published DAC using symmetrical switching built in 0.35micron/3V
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 45
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 46
16bit DAC (6+10)- MSB DAC uses calibrated current sources
I/2
Current
Divider
I/2
I
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 47
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 48
Current Divider Accuracy
Id =
d Id
Id
d Id
Id
=
=
I d1 + I d 2
2
I d1 − I d 2
I/2
I/2
M1
M2
I
I/2+dId /2
M1
I/2-dId /2
M2
I
Id
 d W L 

× 
 + d Vth 
W
VG S −Vt h  L 

2
Ideal Current
Divider
Real Current
Divider
M1& M2 mismatched
àProblem: Device mismatch could severely limit DAC accuracy
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 49
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 50
Dynamic Element Matching
During Φ2
During Φ1
I1(1) = 21 Io (1 + ∆1 )
I2(1) = 21 Io (1 − ∆1 )
I1( 2 ) = 21 Io (1 − ∆1 )
I2( 2 ) = 21 Io (1 + ∆1 )
Io/2
Io/2
I1
I2
fclk
I (1) + I2( 2 )
I2 = 2
2
Io (1 − ∆1 ) + (1 + ∆1 )
=
2
2
I
≈ o f o r ∆1 s m a l l
2
/ 2 error ∆1
Io
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 51
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 52
Dynamic Element Matching
During Φ2
During Φ1
I1(1) = 12 I o (1 + ∆1 )
I
(1)
2
I1( 2 ) = 12 I o (1 − ∆1 )
= I o (1 − ∆1 )
1
2
I
I 3(1) = 12 I1(1) (1 + ∆ 2 )
( 2)
2
= I o (1 + ∆1 )
1
2
Io/4
I3
= I o (1 + ∆1 )(1 + ∆ 2 )
I4
I2
fclk
I 3( 2 ) = 12 I1( 2 ) (1 − ∆ 2 )
/ 2 error ∆2
= 14 I o (1 − ∆1 )(1 − ∆ 2 )
1
4
Io/2
Io/4
I (1) + I 3( 2 )
I3 = 3
2
I o (1 + ∆1 )(1 + ∆ 2 ) + (1 − ∆1 )(1 − ∆ 2 )
=
2
4
I
= o (1 + ∆1∆ 2 )
4
I1
fclk
E.g. ∆1 = ∆2 = 1% à matching error is (1%)2 = 0.01%
EECS 247 Lecture 16: Data Converters
/ 2 error ∆1
Io
© 2005 H.K. Page 53
Summary
D/A Converter
•
D/A architecture
– Unit element – complexity proportional to 2B- excellent DNL
– Binary weighted- complexity proportional to B- poor DNL
– Segmented- unit element MSB(B1)+ binary weighted LSB(B2)à complexity
proportional (2B1-1) + B2 – DNL compromise between the two
•
Static performance
•
Dynamic performance
•
DAC improvement techniques
– Component matching
– Glitches
– Symmetrical switching rather than sequential switching
– Current source self calibration
– Dynamic element matching
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 54
MOS Sampling Circuits
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 55
Re-Cap
Analog Input
Analog
Preprocessing
• How can we
build circuits
that "sample"
A/D
Conversion
DSP
Anti-Aliasing
Filter
Sampling
+Quantization
000
...001...
110
D/A
Conversion
"Bits to
Staircase"
Analog
Post processing
Reconstruction
Filter
Analog Output
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 56
Ideal Sampling
φ1
• In an ideal world,
zero resistance
sampling switches
would close for the
briefest instant to
sample a continuous
voltage vIN onto the
capacitor C
• Not realizable!
vIN
vOUT
S1
C
φ1
T=1/fS
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 57
Ideal T/H Sampling
φ1
vIN
vOUT
S1
C
φ1
T=1/fS
• Vout tracks input when switch is closed
• Grab exact value of Vin when switch opens
• "Track and Hold" (T/H) (often called Sample & Hold!)
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 58
Ideal T/H Sampling
time
Continuous
Time
T/H signal
(SD Signal)
Clock
DT Signal
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 59
Practical Sampling
φ1
vIN
vOUT
M1
C
•
•
•
•
•
Switch induced noise power à kT/C
Finite Rsw à limited bandwidth
Rsw = f(Vin) à distortion
Switch charge injection
Clock jitter
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 60
kT/C Noise
k BT ∆2
≤
C
12
 2B − 1 

C ≥ 12k BT 
 VFS 
2
In high resolution ADCs kT/C noise usually dominates
overall error (power dissipation considerations).
B
Cmin (VFS = 1V)
8
12
14
16
20
0.003 pF
0.8 pF
13 pF
206 pF
52,800 pF
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 61
Acquisition Bandwidth
• The resistance R of
switch S1 turns the
sampling network into a
lowpass filter with
risetime = RC = τ
• Assuming Vin is
constant during the
sampling period and C
is initially discharged
EECS 247 Lecture 16: Data Converters
φ1
vIN
vOUT
R S1
C
vout (t ) = vin (1 − e − t /τ )
© 2005 H.K. Page 62
Switch On-Resistance

1 
Vin − Vout  t =
 << ∆
 2 fs 
−1
Vin e
2 f sτ
<< ∆
Vin = VFS
Worst Case:
τ << −
R << −
φ1
vIN
vOUT
R S1
C
1
T
2 ln 2 B − 1
(
)
1
1
2 f sC ln 2 B − 1
(
Example:
B = 14,
)
φ1
T=1/fS
C = 13pF, fs = 100MHz
T/τ >> 19.4, R << 40Ω
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 63
Switch On-Resistance
I D ( triode ) = µCox
RON =
dI D ( triode )
1
≅
RON
dVDS
VDS →0
1
1
=
W
W
µCox (VGS − Vth ) µCox (VDD − Vth − Vin )
L
L
for
RON =
W
VDS 
 VGS − VTH −
VDS ,
L
2 
Ro =
µCox
1
W
(VDD − Vth )
L
Ro
Vin
1−
VDD − Vth
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 64
Sampling Distortion
vout =
T
Vin  

−  1−


2τ  VDD −Vt h  
vi n  1 − e





10bit ADC & T/τ = 10
VDD – Vth = 2V
VFS = 1V
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 65
Sampling Distortion
• SFDR is very sensitive to
sampling distortion
• Solutions:
• Overdesignà Larger
switches
à increased switch
charge injection
• Complementary switch
• Maximize VDD/VFS
à decreased dynamic
range
• Constant VGS ? f(Vin)
à …
10bit ADC T/τ = 20
VDD – Vth = 2V
VFS = 1V
EECS 247 Lecture 16: Data Converters
© 2005 H.K. Page 66