Download RTH=2000 K/W - The University of Texas at Arlington

High Performance Analog
Integrated Circuit Design:
The Effect of Device SelfHeating on Design Optimization
Ronald L. Carter, Professor
Analog Integrated Circuit Design Lab
Electrical Engineering Department
The University of Texas at Arlington
Analog IC Design
with Self-Heating
Heat Source/Temperature Effects
 Thermal Equations/Analogy
 Thermal Resistance Models
 Effect of Thermal Resistance on
Device Biasing
 Effect of Thermal Resistance on the
Circuit Performance
RLCarter:
Analog IC
 Conclusions/Future
Work
Design with Self

Heating
2
Typical IC npn BJT
Figure 9.2a, Semiconductor Physics & Devices, 2nd ed., by Neamen, Irwin, Chicago, 1997
RLCarter: Analog IC
Design with Self
Heating
3
EB and CB Heat Sources
Figure 9.2a, Semiconductor Physics & Devices, 2nd ed., by Neamen, Irwin, Chicago, 1997
emitter
contact
collector
base
contact
RLCarter: Analog IC
Design with Self
Heating
EB Depletion Region, PE = iE*v BE
EB Depletion Region, PC = iC*v BC
4
Temperature Increase
Td-Ta=Ta{[1 + (n+1)(Dte+Dtc)/Ta)]1/(n+1)1}
Dte and Dtc are pseudo-temperatures via
the Kirchoff transformation,
assuming k(T) = k(300K)[T/300]n
 Dte = RTh,EB|ievbe|
 Dtc = RTh,CB|icvbc|
 RTh,EB, RTh,CB are thermal res. at Ta.

Following S. H. Whemple, and H. Huang, "Thermal Design of Power GaAs FETs", in GaAs FET Principles and
RLCarter:
Analog IC
Technology,
J. V. DiLorenzo and D. D. Khandelwal, eds., pp. 313-347, Artech House, 1982.
Design with Self
Heating
5
Circuit Simulation of
Temperature Effects



Typically TNOM (parameter spec.
temperature) and TEMP (circuit
operation temperature) only variables
However, Td =Tdevice is a function of ie,
vbe, ic and vbc.
More flexibility with Vertical Bipolar
Inter-Company model (VBIC)
RLCarter: Analog IC
Design with Self
Heating
6
Gummel-Poon Static
npn Circuit Model
C
B RBB
B’
RC
ILC
IBR
ILE
IBF
RLCarter: Analog IC
Design with Self
Heating
E
Intrinsic
Transistor
ICC - IEC =
IS(exp(vBE/NFVt) exp(vBC/NRVt)/QB
RE
7
VBIC Model Overview







RLCarter: Analog IC
Design with Self
Heating
Self-heating effects
included
Improved Early effect
modeling
Quasi-saturation modeling
Parasitic substrate
transistor modeling
Parasitic fixed (oxide)
capacitance modeling
An avalanche multiplication
model included
Base current is decoupled
from collector current
8
CAD Tools Support for VBIC

Hspice



Does not support PNP device
Does not scale with “Area” and “M” terms
Spectre



[4]
[5]
Support both NPN and PNP devices
scale with “Area” and “M” term
HPADS

No temperature nodes (“dt” and “tl”), so
unable to simulate thermal coupling effects
RLCarter: Analog IC
Design with Self
Heating
9
Temperature Designations for
VBIC
Parameters
Description
Spectre
[4]
Hspice
[5]
Name
Default
Name
Default
Temperature rise of
the device from
ambient
trise
0
dtemp
0
Ambient temperature
temp
27
temp
25
Parameters
measurement
temperature
tnom
27
tnom
25
tref
27
RLCarter: Analog IC
Design with Self
Heating
10
Using VBIC in Spectre
[5]
Name c b e [s] [dt] [tl] ModelName
parameter=value ...
 Selft=1 and Rth>0 to enable Self-heating
 1 volt at the temperature nodes = 1 degree in
temperature
 “tl” node represents the initial local temperature
of device which always corresponds to
trise+temp
 “dt” node represents the rise above trise+temp
caused by thermal dissipation, whose value equals
V(dt)-V(tl)
Analog
IC
 RLCarter:
Device
temperature=V(dt)-V(tl)+trise+temp
Design with Self
Heating
11
Using VBIC in Cadence

Need explicit external temperature nodes in the
symbol to model inter-device thermal coupling by



Connecting thermal network between “dt” nodes, or
Adding VCVS between “tl” and “tlr” node
Customized VBIC 6-terminal (5-pin) symbol
RLCarter: Analog IC
Design with Self
Heating
12
Model Conversion





Most BJTs are defined with SGP model
A conversion from SGP to VBIC is needed
Only approximate conversion is possible
Some parameters are unmapped such as Rth and Cth
Two approaches are provided


Manual conversion — done empirically and need Local
Ratio Evaluation [2]
Program conversion using program sgp_2_vbic [3]
RLCarter: Analog IC
Design with Self
Heating
13
Parameter Mapping using sgp_2_vbic
VBIC mapping
VBIC
Rcx
Rc
Mc
Rci
0
Cjcp
Rbx
Rbm
Ps
Rbi
Rb-Rbm
Ms
Re
Re
Nei
Is
Is
Iben
Nf
Nf
Nen
Nr
Nr
Ibei
Fc
Fc
Ibci
Cje
Cje
Nci
Pe
Vje
Ibcn
Me
Mje
Ncn
Cjc
Cjc·Xcjc
Ikf
Cjep
Cjc(1-Xcjc) Ikr
Pc
Vjc
Tf
RLCarter: Analog IC
Design with Self
Heating
mapping
Mjc
Cjs
Vjs
Mjs
Nf
Ise
Ne
Is/Bf
Is/Br
Nr
Isc
Nc
Ikf
Ikr
Tf
VBIC
Xtf
Vtf
Itf
Tr
Td
Ea
Eaie
Eaic
Eane
Eanc
Xis
Xii
Xin
Kfn
Afn
mapping
Xtf
Vtf
Itf
Tr
Tf·Ptf/180
Eg
Eg
Eg
Eg
Eg
Xti
Xti-Xtb
Xti-Xtb
Kf
Af
Early Effect model is
different
 Need Vbe, Vbc to solve
the 3 equations below

g OF
IC
g oR
Ie

1 / VAF
1  VbeF / VAR  VbcF / VAF

1 / VAR
1  VbeR / VAR  VbcR / VAF
 F CbcF
  1 
F
q

q
be
 bc F
  
g
/
I
c
o

  VEF    1

CbeR   1   1
R
R
qbe  R 
 qbc
g o / I e  VER 

14
Analog IC Design
with Self-Heating
Heat Source/Temperature Effects
 Thermal Equations/Analogy
 Thermal Resistance Models
 Effect of Thermal Resistance on
Device Biasing
 Effect of Thermal Resistance on the
Circuit Performance
RLCarter:
Analog IC
 Conclusions/Future
Work
Design with Self

Heating
15
Device Geometry and Boundary Conditions
RLCarter: Analog IC
Design with Self
Heating
16
Static Heat Flow Equation
and Poisson’s Equation
   T DT ( x, y, z )   g ( x, y, z )

 V 

2
DT = T-T0 (K) is the temperature rise
above local ambient
 = Thermal conductivity (Wcm-1K-1)
g= volumetric heat gen. rate (W cm-3)
RLCarter:
= charge
dens., and  = permittivity
Analog IC
Design with Self
Heating
17
The Electrical Analogy





The Kirchoff transformation factors
the (T)
Both equations become the Laplacian
DV[Volt] is the analog of DT[K]
I[Ampere] is the analog of P [Watts]
V = IR is the analog of DT = P RTH
RLCarter: Analog IC
Design with Self
Heating
18
Semiconductor Material
Properties at 300K
Parameter Name Si
SiO2
Al
Cu
Conductivity 
(Wcm-1K-1)
1.412
0.014
2.37
3.98
Density
(g cm-3)
2.328
2.648
2.7
8.96
Specific Heat
CP(Jg-1K-1)
0.7
0.787
0.898
0.384
RLCarter: Analog IC
Design with Self
Heating
19
Applying the Analogy to
Spreading Resistance
The potential field due to a point current
source on a wafer surface is
V = I/(2r)
The thermal analogy is T = P/(2r)
For a cylindrical contact of radius r, the
spreading resistance, Rsp = /4r
The thermal analogy is Rth = 1/4r
Dieter K.Analog
Schroder,
RLCarter:
IC “Semiconductor material and device characterization, 2nd Ed., Wiley-Interscience in
1998, Self
New
York Pages 31-33.
Design with
Heating
20
Analog IC Design
with Self-Heating
Heat Source/Temperature Effects
 Thermal Equations/Analogy
 Thermal Resistance Models
 Effect of Thermal Resistance on
Device Biasing
 Effect of Thermal Resistance on the
Circuit Performance
RLCarter:
Analog IC
 Conclusions/Future
Work
Design with Self

Heating
21
Thermal Resistance Model
for square emitter

For a square emitter of side w
RTh,CB
RTh, EB


w 

 RTh, F (Tnom )    w kSi,Tnom  1 
 tw 




w 

 RTh, R (Tnom )    w kSi,Tnom  1 
 tw 


S. H. Whemple,
RLCarter:
Analogand
IC H. Huang, op. cit.
Design with Self
Heating
-1
-1
22
Image effect of Heat
Sources Below Surface
base
contact
emitter
contact
collector
D
RTH 
EB Depletion Region, PE = iE*v BE
EB Depletion Region, PC = iC*v BC
1
4 lw  D / 2
2
, where the emitter
is l long and w wide, D below the surface and
the wafer is thick, tw  lw
RLCarter: Analog IC
Design with Self
Heating
23
Dielectric Isolated BJT
(DIBJT)




kSi ~ 100 kSi02
Perimeter of “well”
is approximately an
isotherm
Rtrench = Rwall +
Rsurface
Rbulk = Risolation +
Rsubstrate
RLCarter: Analog IC
Design with Self
Heating
24
DIBJT Rth Model
RLCarter: Analog IC
Design with Self
Heating
25
Analogy Modeling of Device
Thermal Resistance
RLCarter: Analog IC
Design with Self
Heating
26
Analog IC Design
with Self-Heating
Heat Source/Temperature Effects
 Thermal Equations/Analogy
 Thermal Resistance Models
 Effect of Thermal Resistance on
Device Biasing
 Effect of Thermal Resistance on the
Circuit Performance
RLCarter:
Analog IC
 Conclusions/Future
Work
Design with Self

Heating
27
Transient Analysis of a BJT
with Multiple Thermal Paths
Simulation circuit



The thermal network consists of 3 poles
t1=1us, t2=100us and t3=10ms
Spectre is used as a simulator
RLCarter: Analog IC
Design with Self
Heating
28
VBIC Model Parameters
used for the BJT
rcx
re
fc
cjc
cjcp
iben
nci
ver
xtf
td
eane
xin
1
0.5
0.5
417.5fF
0
3.471pA
1.07
333.331V
120V
0
1.11
0.7
rci
is
cje
cjep
ps
nen
ibcn
ikf
vtf
ea
eanc
kfn
0
4.479fA
910fF
417.5fF
0.7
3.66
0
1mA
0
1.11
1.11
rbx
nf
pe
pc
ms
ibei
ncn
ikr
itf
eaie
xis
36
1.07
0.661
1
0.5
0.0172269fA
1
0
0
1.11
3
0
afn
1
rbi
nr
me
mc
nei
ibci
vef
tf
tr
eaic
xii
0
1.07
0.294
0.28
1.07
4.479fA
195.325V
112ps
1ns
1.11
0.7
* Mapped from GP model
RLCarter: Analog IC
Design with Self
Heating
29
Transient Thermal
Response - JI BJT
Current and Temperature Rise of a BJT with 3-Pole Thermal Network
20
Current
Temperature Rise
10
t1
0
-10
10
RLCarter: Analog
IC
Design with Self
Heating
-8
10
-6
10
Time (s)
t2
-4
10
Temperature Rise (Degree)
Collector Current (mA)
1
t3
-2
0
10
30
Transient Thermal
Response - DIBJT
A DIBJT with 3-Pole Thermal Network
1.5
30

Current
Temperature Rise

RTH,epi=394 K/W
CTH,epi=79.4p sW/K
1
20
0.5
10
Temperature Rise (Degree)
Collector Current (mA)
(


tepi
0
-10
10
RLCarter:
-8
10
Analog
IC
Design with Self
Heating
tox
tw
-6
10
Time (s)
-4
10

-2
10
0
)
RTH,ox=2742 K/W
CTH,ox=39.75p
sW/K
(

tepi=31.3ns
tox=109ns
)
RTH,w=126 K/W
CTH,w=11.9p sW/K
(
tw=1.5ms
)
31
Build SDD BJT model in
ADS



SDD (Symbolic Defined Device)
Combination of the classical GP model and the
thermal network
For static model, IS, BF, BR, ISE and ISC
values changed by temperature rise
RLCarter: Analog IC
Design with Self
Heating
32
SDD Model verification
I-V Characteristics Comparison of Different Models
6
IB=100uA
5
IB=75uA
Collector current (mA)
4
IB=50uA
3
IB=25uA
2
1
Spectre VBIC model
ADS GP model
ADS SDD model
0
-1
RLCarter: Analog
IC
0
Design with Self
Heating
1
2
3
Vce (v)
4
5
6
33
Current Mirror Driving BJT
with 3 Emitter Fingers


Simulation Circuit
IC1
IC2
IC3


cme
cee
RLCarter: Analog IC
Design with Self
Heating

The multiple finger BJT
consists of 3 fingers, Q1,
Q2 and Q3. They have
the same geometrical
size with Qref
Q2 is the inner finger
Thermal coupling occurs
between 3 fingers. The
coupling factor is Cme
and Cee
No thermal coupling
between the multiply
finger BJT and Qref
34
VCVS Thermal Coupling
Model
RLCarter: Analog IC
Design with Self
Heating
35
Model Parameters
IS
ISE
ISC
IKF
IKR
IRB
BR
110-18 A BF
-18
110 A NF
0
10mA


0.7371
NR
NC
NE
VAF
VAR
100
RE
1.07
RC
1.07
2
1.259
74.03V
500V
RB
RBM
EG
XTI
XTB
5
5
10
10
1.11eV
3
1.5
* Typical values for 1um2um device
RLCarter: Analog IC
Design with Self
Heating
36
Current Ratio (IC/Iref) for
Different RTH
1um2um device
W
1um
L
2um
S
3um
cme 0.102
cee
RLCarter: Analog IC
Design with Self
Heating
0.051
37
Temperature Rise for
Different RTH
1um2um device
W
1um
L
2um
S
3um
cme 0.102
cee
RLCarter: Analog IC
Design with Self
Heating
0.051
38
Current Ratio for
Different Spacing
2.8
2.6
2.4
Inner emitter
Outer emitter
RTH=3000 K/W
3um
L=2um W=1um
5um
Current Ratio
2.2
7um
2
1.8
Cme
Cee
3um
0.102
0.051
1.4
5um
0.073
0.036
1.2
7um
0.057
0.028
1.6

No thermal coupling
1
0.8
0
0.5
RLCarter:
Analog1IC
Design with Self
Heating
1.5
2
Iref (mA)
2.5
3
3.5
4
39
Temperature Rise for
Different Spacing
120
Inner emitter
Outer emitter
100
Temperature Rise (Degree)
3um
5um
80
7um
L=2um W=1um
60
RTH=3000 K/W

40
20
0
0
0.5Analog1IC
RLCarter:
Design with Self
Heating
Cme
Cee
3um
0.102
0.051
5um
0.073
0.036
7um
0.057
0.028
No thermal coupling
1.5
2
Iref (mA)
2.5
3
3.5
4
40
Current Ratio (IC/Iref) for
Different RTH
2.6
2.4
Inner emitter
Outer emitter
2.2
1um5um device
Current Ratio
2
1.8
1.6
1.4
Rth=2000K/W 
Rth=1000K/W

1.2
1
0.8
0
0.5
RLCarter:
Analog1 IC 1.5
Design with Self
Heating
3
L
5um
S
3um
cee
Rth=200K/W
2.5
Iref (mA)
1um
cme 0.100

2
W
3.5
4
4.5
0.050
5
41
Temperature Rise for
Different RTH
100
90
Temperature Rise (Degree)
80
Inner emitter
Outer emitter
1um5um device
70
60
50
40
W
1um
30
L
5um
S
3um
20
Rth=1000K/W

Rth=2000K/W 
10
cme 0.100
Rth=200K/W

0
0
0.5
1
RLCarter:
Analog
IC
Design with Self
Heating
1.5
2
2.5
Iref (mA)
3
3.5
cee
4
4.5
0.050
5
42
Current Ratio for
Different Spacing
2.6
2.4
Inner emitter
Outer emitter
3um
2.2
L=5um W=1um
5um
Current Ratio
2
7um
1.8
RTH=2000 K/W
1.6
1.4
No thermal coupling
1.2
1
0.8
0
0.5 Analog
1
1.5
RLCarter:
IC
Design with Self
Heating
Cme
Cee
3um
0.100
0.050
5um
0.080
0.040
7um
0.067
0.033

2
2.5
Iref (mA)
3
3.5
4
4.5
5
43
Temperature Rise for
Different Spacing
100
90
Inner emitter
Outer emitter
3um
Temperature Rise (Degree)
80
70
L=5um W=1um
5um
7um
60
RTH=2000 K/W
50
40
Cme
Cee
3um
0.100
0.050
5um
0.080
0.040
7um
0.067
0.033
30

20
No thermal coupling
10
0 RLCarter: Analog IC
0
0.5
1
1.5
Design with Self
Heating
2
2.5
Iref (mA)
3
3.5
4
4.5
5
44
Analog IC Design
with Self-Heating
Heat Source/Temperature Effects
 Thermal Equations/Analogy
 Thermal Resistance Models
 Effect of Thermal Resistance on
Device Biasing
 Effect of Thermal Resistance on the
Circuit Performance
RLCarter:
Analog IC
 Conclusions/Future
Work
Design with Self

Heating
45
A741 Simulation
Simulated by Spectre (Ver. 4.4.6.061301)
 Analog Waveform is used to obtain graphic output
 Use the circuit posted on WEB (http://wwwee.uta.edu/Online/adavis/analog/f_opamp.cir)
 Transistor models are mapped to VBIC model using
sgp_2_vbic (only one npn and pnp model used)
 Area of Q13A is 0.25; Area of Q13B is 0.75
 Areas of Q14 and Q20 are 3
 Areas of other transistors are 1
 Connect A741 with 15V voltage supplies
RLCarter: Analog IC

Design with Self
Heating
46
μA741 Op-Amp Schematic
RLCarter: Analog IC
Design with Self
Heating
[1]
47
Relative Device
Temperatures
Configure A741
as a voltage
100
follower
80
 DC analysis result
60
 Rth for all npn
transistors is
40
5000K/W
20
 Rth for all pnp
0
transistors is
1000KW
Transistor
 No load is
connected
RLCarter:
Analog
IC
Q17
is
91
degrees
higher than the ambient temperature!
Design with Self

Heating
23
21
19
17
15
13
11
9
7
5
3
1
Degree
Temperature deflection
48
Temperature transitions of
Q1 and Q13 (without Cth)
Q1
Q13
7
RLCarter: Analog IC
Design with Self th,npn
Heating
(R
=5000 K/W;Rth,pnp=1000 K/W)
49
Temperature transition of
Q17 (1)




Rth,npn=5000K/W
Cth,npn=1 sW/K
Rth,pnp=1000K/W
Cth,pnp=10 sW/K
Need about 60ms
to reach the
stable temperature
RLCarter: Analog IC
Design with Self
Heating
50
Temperature transition of
Q13 (1)




Rth,npn=5000K/W
Cth,npn=1 sW/K
Rth,pnp=1000K/W
Cth,pnp=10 sW/K
Need about 60ms
to reach the
stable temperature
RLCarter: Analog IC
Design with Self
Heating
51
Temperature transition of
Q17 (2)






RLCarter: Analog IC
Design with Self
Heating
Rth,npn=5000K/W
Cth,npn=0.1sW/K
Rth,pnp=1000K/W
Cth,pnp=10 sW/K
Need about
40ms to reach
the stable
temperature
Temperature variation increases
52
Temperature transition of
Q13 (2)






RLCarter: Analog IC
Design with Self
Heating
Rth,npn=5000K/W
Cth,npn=1 sW/K
Rth,pnp=1000K/W
Cth,pnp=1 sW/K
Need about
10ms to reach
the stable
temperature
Temperature variations increase
53
Circuit used to measure the
open loop gain[2]
Simulation parameters:



Use a feedback technique to
determine the open loop gain
DUT is the op amp to be
tested
Nulling op amp is connected
in a feedback mode
RLCarter: Analog IC
Design with Self
Heating





R1=100
R2=1M
R3=1K
Vmid=0
VSRC1 sweeps
from 0 to 1V
54
Typical simulation output
RLCarter: Analog IC
Design with Self
Heating
55
Table of open loop gain
Note: Each value times 104
RLCarter: Analog IC
Design with Self
Heating
56
Surface of open loop gain
5
x 10

12
Open Loop Gain
10
Interpolation
used
8

6
4
2
1.8
Decreases
about a
factor of 60!
2
2.2
3.5
2.4
3
2.6
2.5
2
RLCarter: Analog
IC
log10(Rth,npn)
Design with Self
Heating
2.8
log10(Rth,pnp)
57
Surface of open loop gain
(dB view)
Open Loop Gain (dB)
120

110
100
Decreases
about
36dB!
90
1.8
2
80
3.5
2.2
3
2.4
2.5
RLCarter: Analog IC
log10(Rth,npn)
Design with Self
Heating
2.6
2
2.8
log10(Rth,pnp)
58
Slew rate (without Cth )


Voltage follower is
used
Input signal


5K pulse input
rise and fall time: 1S
RLCarter: Analog IC
Design with Self
Heating



Voltage level: 0 and 10V
Rising edge is measured
Unit: V/S
Only 2% variation
59
Slew rate (including Cth )
Set Rth,npn=5000 K/W and Rth,pnp=1000 K/W
Only 0.4% variation when Cth changes
 Comparing with Cth=0 case (0.6751, circled
value at previously table), only 1.5% variation
 Self-heating (isolated) has no significant effect
RLCarter: Analog IC
on slew rate
Design with Self

Heating
60
Thermal coupling effect on
open-loop gain





Use the same circuit discussed previously
Set Rth,npn=4000 K/W and Rth,pnp=900 K/W and
Cth,npn=Cth,pnp=0
The hottest transistor is Q17
The amplificatory transistors at 1st stage are Q3 and Q4
Temperature node of Q17 is connected with temperature
node of Q3 and Q4 by two identical thermal resistors RC
RLCarter: Analog IC
Design with Self
Heating
61
Open-loop gain reduced by
thermal coupling
4
2.7
x 10
2.6
Open Loop Gain
2.5

2.4
2.3
2.2
2.1

2
1.9
1
10
2
10
RLCarter: Analog
Design with Self
Heating
3
4
10
10
IC
Coupling Thermal Resistor
5
10
Interpolation
is used to
obtain this
curve
Decrease
about 25.4%!
6
10
62
Analog IC Design
with Self-Heating
Heat Source/Temperature Effects
 Thermal Equations/Analogy
 Thermal Resistance Models
 Effect of Thermal Resistance on
Device Biasing
 Effect of Thermal Resistance on the
Circuit Performance
RLCarter:
Analog IC
 Conclusions/Future
Work
Design with Self

Heating
63
Summary

VBIC model used to analyze thermal effects



Isolated self-heating in A741



Effect of individual device temperatures in a A741
Inter-device heating effects
Isolated self-heating can reduce the open loop gain
Not a significant change in slew rate
Preliminary study on thermal coupling effect


Open loop gain is reduced if significant thermal coupling
exists between 1st and 2nd stage
Current mirror temperature compensation schemes are
more critical when coupling is not optimum.
RLCarter: Analog IC
Design with Self
Heating
64
Acknowledgements: Support



TheTexas Higher Education Coordinating
Board (THECB)
National Semiconductor Corporation (NSC)
The National Science Foundation
Industry/University Center for Electronic
Materials, Devices and Systems
(NSF/CEMDAS)
RLCarter: Analog IC
Design with Self
Heating
65
Acknowledgements:
Analog IC Research Group








Professor W. Alan Davis
Zhipeng Zhu
Zheng Li
Siddharth Nashiney
Naveen Kumar Reddy Siddareddygari
Shankaranarayanan Rajaraman
Piyush Thacker
Anurag Lakhlani
RLCarter: Analog IC
Design with Self
Heating
66
References
Paul R. Gray, Robert G. Meyer, et al, Analysis and design of analog integrated circuits, New York: Wiley, c2001
Fujiang Lin, et al, “Extraction Of VBIC Model for SiGe HBTs Made Easy by Going Through Gummel-Poon Model”,
from http://eesof.tm.agilent.com/pdf/VBIC_Model_Extraction.pdf
http://www.fht-esslingen.de/institute/iafgp/neu/VBIC/
Avanti Star-spice User Manual, 04, 2001.
Affirma Spectre Circuit Simulator Device Model Equations
Zweidinger, D.T.; Fox, R.M., et al, “Equivalent circuit modeling of static substrate thermal coupling using VCVS
representation”, Solid-State Circuits, IEEE Journal of , Volume: 2 Issue: 9 , Sept. 2002, Page(s): 1198 -1206
Jonathan S. Brodsky, “Physics based impedance models for the simulation of self-heating in semiconductor
devices and circuits”, PhD Dissertation, Dept of Electrical and Computer Engineering, University of Florida,
Gainesville, Aug 1997.
McAndrew, C., Seitchik, J. and etal, ” VBIC95: An improved vertical, IC bipolar transistor model”,
Bipolar/BiCMOS Circuits and Technology Meeting, 1995., Proceedings of the 1995
Burns and Robert, An introduction to mixed-signal testing, Oxford University Press, 1999 Copyright Texas Instruments
RLCarter: Analog IC
Design with Self
Heating
67