Download Lecture 5 - Harvey Mudd College

Introduction to
CMOS VLSI
Design
Lecture 5:
DC & Transient Response
David Harris
Harvey Mudd College
Spring 2007
Outline






Pass Transistors
DC Response
Logic Levels and Noise Margins
Transient Response
RC Delay Models
Delay Estimation
5: DC and Transient Response
CMOS VLSI Design
Slide 2
Activity
1) If the width of a transistor increases, the current will
increase
decrease
not change
2) If the length of a transistor increases, the current will
increase
decrease
not change
3) If the supply voltage of a chip increases, the maximum
transistor current will
increase
decrease
not change
4) If the width of a transistor increases, its gate capacitance will
increase
decrease
not change
5) If the length of a transistor increases, its gate capacitance will
increase
decrease
not change
6) If the supply voltage of a chip increases, the gate capacitance
of each transistor will
increase
decrease
not change
5: DC and Transient Response
CMOS VLSI Design
Slide 3
Activity
1) If the width of a transistor increases, the current will
increase
decrease
not change
2) If the length of a transistor increases, the current will
increase
decrease
not change
3) If the supply voltage of a chip increases, the maximum
transistor current will
increase
decrease
not change
4) If the width of a transistor increases, its gate capacitance will
increase
decrease
not change
5) If the length of a transistor increases, its gate capacitance will
increase
decrease
not change
6) If the supply voltage of a chip increases, the gate capacitance
of each transistor will
increase
decrease
not change
5: DC and Transient Response
CMOS VLSI Design
Slide 4
Pass Transistors
 We have assumed source is grounded
 What if source > 0?
VDD
– e.g. pass transistor passing VDD
VDD
5: DC and Transient Response
CMOS VLSI Design
Slide 5
Pass Transistors
 We have assumed source is grounded
 What if source > 0?
VDD
– e.g. pass transistor passing VDD
VDD
 Vg = VDD
– If Vs > VDD-Vt, Vgs < Vt
– Hence transistor would turn itself off
 nMOS pass transistors pull no higher than VDD-Vtn
– Called a degraded “1”
– Approach degraded value slowly (low Ids)
 pMOS pass transistors pull no lower than Vtp
 Transmission gates are needed to pass both 0 and 1
5: DC and Transient Response
CMOS VLSI Design
Slide 6
Pass Transistor Ckts
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
5: DC and Transient Response
CMOS VLSI Design
Slide 7
Pass Transistor Ckts
VDD
VDD
VDD
VDD
VDD
VDD
Vs = VDD-Vtn
Vs = |Vtp|
VDD-Vtn VDD-Vtn
VDD
VDD-Vtn
VDD-Vtn
VDD
VDD-2Vtn
VSS
5: DC and Transient Response
CMOS VLSI Design
Slide 8
DC Response
 DC Response: Vout vs. Vin for a gate
 Ex: Inverter
– When Vin = 0
->
Vout = VDD
– When Vin = VDD
->
Vout = 0
VDD
– In between, Vout depends on
Idsp
transistor size and current
Vin
Vout
– By KCL, must settle such that
Idsn
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight
5: DC and Transient Response
CMOS VLSI Design
Slide 9
Transistor Operation
 Current depends on region of transistor behavior
 For what Vin and Vout are nMOS and pMOS in
– Cutoff?
– Linear?
– Saturation?
5: DC and Transient Response
CMOS VLSI Design
Slide 10
nMOS Operation
Cutoff
Linear
Saturated
Vgsn <
Vgsn >
Vgsn >
Vdsn <
Vdsn >
VDD
Vin
Idsp
Vout
Idsn
5: DC and Transient Response
CMOS VLSI Design
Slide 11
nMOS Operation
Cutoff
Linear
Saturated
Vgsn < Vtn
Vgsn > Vtn
Vgsn > Vtn
Vdsn < Vgsn – Vtn
Vdsn > Vgsn – Vtn
VDD
Vin
Idsp
Vout
Idsn
5: DC and Transient Response
CMOS VLSI Design
Slide 12
nMOS Operation
Cutoff
Linear
Saturated
Vgsn < Vtn
Vgsn > Vtn
Vgsn > Vtn
Vdsn < Vgsn – Vtn
Vdsn > Vgsn – Vtn
VDD
Vgsn = Vin
Vin
Vdsn = Vout
5: DC and Transient Response
Idsp
Vout
Idsn
CMOS VLSI Design
Slide 13
nMOS Operation
Cutoff
Linear
Saturated
Vgsn < Vtn
Vin < Vtn
Vgsn > Vtn
Vin > Vtn
Vdsn < Vgsn – Vtn
Vout < Vin - Vtn
Vgsn > Vtn
Vin > Vtn
Vdsn > Vgsn – Vtn
Vout > Vin - Vtn
VDD
Vgsn = Vin
Vin
Vdsn = Vout
5: DC and Transient Response
Idsp
Vout
Idsn
CMOS VLSI Design
Slide 14
pMOS Operation
Cutoff
Linear
Saturated
Vgsp >
Vgsp <
Vgsp <
Vdsp >
Vdsp <
VDD
Vin
Idsp
Vout
Idsn
5: DC and Transient Response
CMOS VLSI Design
Slide 15
pMOS Operation
Cutoff
Linear
Saturated
Vgsp > Vtp
Vgsp < Vtp
Vgsp < Vtp
Vdsp > Vgsp – Vtp
Vdsp < Vgsp – Vtp
VDD
Vin
Idsp
Vout
Idsn
5: DC and Transient Response
CMOS VLSI Design
Slide 16
pMOS Operation
Cutoff
Linear
Saturated
Vgsp > Vtp
Vgsp < Vtp
Vgsp < Vtp
Vdsp > Vgsp – Vtp
Vdsp < Vgsp – Vtp
VDD
Vgsp = Vin - VDD
Vtp < 0
Vin
Vdsp = Vout - VDD
5: DC and Transient Response
Idsp
Vout
Idsn
CMOS VLSI Design
Slide 17
pMOS Operation
Cutoff
Linear
Saturated
Vgsp > Vtp
Vin > VDD + Vtp
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp > Vgsp – Vtp
Vout > Vin - Vtp
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp < Vgsp – Vtp
Vout < Vin - Vtp
VDD
Vgsp = Vin - VDD
Vtp < 0
Vin
Vdsp = Vout - VDD
5: DC and Transient Response
Idsp
Vout
Idsn
CMOS VLSI Design
Slide 18
I-V Characteristics
 Make pMOS is wider than nMOS such that bn = bp
Vgsn5
Vgsn4
Idsn
Vgsn3
-Vdsp
Vgsp1
Vgsp2
-VDD
0
VDD
Vdsn
Vgsp3
Vgsp4
Vgsn2
Vgsn1
-Idsp
Vgsp5
5: DC and Transient Response
CMOS VLSI Design
Slide 19
Current vs. Vout, Vin
Idsn, |Idsp|
Vin0
Vin5
Vin1
Vin4
Vin2
Vin3
Vin3
Vin4
Vin2
Vin1
Vout
5: DC and Transient Response
CMOS VLSI Design
VDD
Slide 20
Load Line Analysis
 For a given Vin:
– Plot Idsn, Idsp vs. Vout
– Vout must be where |currents| are equal in
Idsn, |Idsp|
Vin0
Vin5
Vin1
Vin4
Vin2
Vin3
Vin3
Vin4
Vin2
Vin1
Vout
5: DC and Transient Response
CMOS VLSI Design
VDD
Vin
Idsp
Vout
Idsn
VDD
Slide 21
Load Line Analysis
 Vin = 0
Vin0
Idsn, |Idsp|
Vin0
Vout
5: DC and Transient Response
CMOS VLSI Design
VDD
Slide 22
Load Line Analysis
 Vin = 0.2VDD
Idsn, |Idsp|
Vin1
Vin1
Vout
5: DC and Transient Response
CMOS VLSI Design
VDD
Slide 23
Load Line Analysis
 Vin = 0.4VDD
Idsn, |Idsp|
Vin2
Vin2
Vout
5: DC and Transient Response
CMOS VLSI Design
VDD
Slide 24
Load Line Analysis
 Vin = 0.6VDD
Idsn, |Idsp|
Vin3
Vin3
Vout
5: DC and Transient Response
CMOS VLSI Design
VDD
Slide 25
Load Line Analysis
 Vin = 0.8VDD
Vin4
Idsn, |Idsp|
Vin4
Vout
5: DC and Transient Response
CMOS VLSI Design
VDD
Slide 26
Load Line Analysis
 Vin = VDD
Vin0
Idsn, |Idsp|
Vin5
Vin1
Vin2
Vin3
Vin4
Vout
5: DC and Transient Response
CMOS VLSI Design
VDD
Slide 27
Load Line Summary
Idsn, |Idsp|
Vin0
Vin5
Vin1
Vin4
Vin2
Vin3
Vin3
Vin4
Vin2
Vin1
Vout
5: DC and Transient Response
CMOS VLSI Design
VDD
Slide 28
DC Transfer Curve
 Transcribe points onto Vin vs. Vout plot
Vin0
Vin5
Vin1
Vin4
Vin2
Vin3
Vin3
Vin4
Vin2
Vin1
Vout
5: DC and Transient Response
VDD
Vin0
Vin1
Vin2
B
A
Vout
VDD
C
Vin3
D
0
Vtn
VDD/2
Vin4
E
VDD+Vtp
Vin5
VDD
Vin
CMOS VLSI Design
Slide 29
Operating Regions
 Revisit transistor operating regions
Region
nMOS
VDD
pMOS
A
A
B
B
Vout
C
C
D
D
0
E
Vtn
VDD/2
E
VDD+Vtp
VDD
Vin
5: DC and Transient Response
CMOS VLSI Design
Slide 30
Operating Regions
 Revisit transistor operating regions
Region
nMOS
A
Cutoff
Linear
B
Saturation
Linear
C
Saturation
Saturation
D
Linear
Saturation
E
Linear
VDD
pMOS
A
B
Vout
Cutoff
C
D
0
Vtn
VDD/2
E
VDD+Vtp
VDD
Vin
5: DC and Transient Response
CMOS VLSI Design
Slide 31
Beta Ratio
 If bp / bn  1, switching point will move from VDD/2
 Called skewed gate
 Other gates: collapse into equivalent inverter
VDD
bp
 10
bn
Vout
2
1
0.5
bp
 0.1
bn
0
Vin
5: DC and Transient Response
CMOS VLSI Design
VDD
Slide 32
Noise Margins
 How much noise can a gate input see before it does
not recognize the input?
Output Characteristics
Logical High
Output Range
VDD
Input Characteristics
Logical High
Input Range
VOH
NMH
VIH
VIL
Indeterminate
Region
NML
Logical Low
Output Range
VOL
Logical Low
Input Range
GND
5: DC and Transient Response
CMOS VLSI Design
Slide 33
Logic Levels
 To maximize noise margins, select logic levels at
Vout
VDD
b p/b n > 1
Vin
Vout
Vin
0
VDD
5: DC and Transient Response
CMOS VLSI Design
Slide 34
Logic Levels
 To maximize noise margins, select logic levels at
– unity gain point of DC transfer characteristic
Vout
Unity Gain Points
Slope = -1
VDD
VOH
b p/b n > 1
Vin
VOL
Vout
Vin
0
Vtn
5: DC and Transient Response
VIL VIH VDD- VDD
|Vtp|
CMOS VLSI Design
Slide 35
Transient Response
 DC analysis tells us Vout if Vin is constant
 Transient analysis tells us Vout(t) if Vin(t) changes
– Requires solving differential equations
 Input is usually considered to be a step or ramp
– From 0 to VDD or vice versa
5: DC and Transient Response
CMOS VLSI Design
Slide 36
Inverter Step Response
 Ex: find step response of inverter driving load cap
Vin (t ) 
Vin(t)
Vout (t  t0 ) 
dVout (t )

dt
5: DC and Transient Response
Vout(t)
Cload
Idsn(t)
CMOS VLSI Design
Slide 37
Inverter Step Response
 Ex: find step response of inverter driving load cap
Vin (t )  u(t  t0 )VDD
Vin(t)
Vout (t  t0 ) 
dVout (t )

dt
5: DC and Transient Response
Vout(t)
Cload
Idsn(t)
CMOS VLSI Design
Slide 38
Inverter Step Response
 Ex: find step response of inverter driving load cap
Vin (t )  u(t  t0 )VDD
Vin(t)
Vout (t  t0 )  VDD
dVout (t )

dt
5: DC and Transient Response
Vout(t)
Cload
Idsn(t)
CMOS VLSI Design
Slide 39
Inverter Step Response
 Ex: find step response of inverter driving load cap
Vin (t )  u(t  t0 )VDD
Vin(t)
Vout (t  t0 )  VDD
dVout (t )
I dsn (t )

dt
Cload


I dsn (t )  


5: DC and Transient Response
Vout(t)
Cload
Idsn(t)
Vout
Vout
t  t0
 VDD  Vt
 VDD  Vt
CMOS VLSI Design
Slide 40
Inverter Step Response
 Ex: find step response of inverter driving load cap
Vin (t )  u(t  t0 )VDD
Vin(t)
Vout (t  t0 )  VDD
dVout (t )
I dsn (t )

dt
Cload

0


2
b
I dsn (t )  
V

V


DD
2

V (t )
 b VDD  Vt  out 2
 
5: DC and Transient Response
Vout(t)
Cload
Idsn(t)
t  t0
Vout  VDD  Vt
 V (t ) V  V  V
 out
out
DD
t

CMOS VLSI Design
Slide 41
Inverter Step Response
 Ex: find step response of inverter driving load cap
Vin (t )  u(t  t0 )VDD
Vin(t)
Vout (t  t0 )  VDD
Vout(t)
Cload
dVout (t )
I dsn (t )

dt
Cload
Idsn(t)
Vin(t)

0


2
b
I dsn (t )  
V

V


DD
2

V (t )
 b VDD  Vt  out 2
 
 V (t ) V  V  V
 out
out
DD
t

5: DC and Transient Response
CMOS VLSI Design
t  t0
Vout  VDD  Vt
Vout(t)
t0
t
Slide 42
Delay Definitions
 tpdr:
 tpdf:
 tpd:
 t r:
 tf: fall time
5: DC and Transient Response
CMOS VLSI Design
Slide 43
Delay Definitions
 tpdr: rising propagation delay
– From input to rising output crossing VDD/2
 tpdf: falling propagation delay
– From input to falling output crossing VDD/2
 tpd: average propagation delay
– tpd = (tpdr + tpdf)/2
 tr: rise time
– From output crossing 0.2 VDD to 0.8 VDD
 tf: fall time
– From output crossing 0.8 VDD to 0.2 VDD
5: DC and Transient Response
CMOS VLSI Design
Slide 44
Delay Definitions
 tcdr: rising contamination delay
– From input to rising output crossing VDD/2
 tcdf: falling contamination delay
– From input to falling output crossing VDD/2
 tcd: average contamination delay
– tpd = (tcdr + tcdf)/2
5: DC and Transient Response
CMOS VLSI Design
Slide 45
Simulated Inverter Delay
 Solving differential equations by hand is too hard
 SPICE simulator solves the equations numerically
– Uses more accurate I-V models too!
 But simulations take time to write, may hide insight
2.0
1.5
1.0
(V)
Vin
tpdf = 66ps
tpdr = 83ps
Vout
0.5
0.0
0.0
200p
400p
600p
800p
1n
t(s)
5: DC and Transient Response
CMOS VLSI Design
Slide 46
Delay Estimation
 We would like to be able to easily estimate delay
– Not as accurate as simulation
– But easier to ask “What if?”
 The step response usually looks like a 1st order RC
response with a decaying exponential.
 Use RC delay models to estimate delay
– C = total capacitance on output node
– Use effective resistance R
– So that tpd = RC
 Characterize transistors by finding their effective R
– Depends on average current as gate switches
5: DC and Transient Response
CMOS VLSI Design
Slide 47
Effective Resistance
 Shockley models have limited value
– Not accurate enough for modern transistors
– Too complicated for much hand analysis
 Simplification: treat transistor as resistor
– Replace Ids(Vds, Vgs) with effective resistance R
• Ids = Vds/R
– R averaged across switching of digital gate
 Too inaccurate to predict current at any given time
– But good enough to predict RC delay
5: DC and Transient Response
CMOS VLSI Design
Slide 48