Download Static CMOS Logic

CPE/EE 427, CPE 527
VLSI Design I
Complementary CMOS Logic Gates
Department of Electrical and Computer Engineering
University of Alabama in Huntsville
Aleksandar Milenkovic ( www.ece.uah.edu/~milenka )
Static CMOS Logic
•VLSI Design I; A. Milenkovic
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CMOS Circuit Styles
• Static complementary CMOS - except during switching,
output connected to either VDD or GND via a lowresistance path
– high noise margins
• full rail to rail swing
• VOH and VOL are at VDD and GND, respectively
– low output impedance, high input impedance
– no steady state path between VDD and GND (no static power
consumption)
– delay a function of load capacitance and transistor resistance
– comparable rise and fall times (under the appropriate transistor
sizing conditions)
• Dynamic CMOS - relies on temporary storage of signal
values on the capacitance of high-impedance circuit nodes
– simpler, faster gates
– increased sensitivity to noise
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Static Complementary CMOS
Pull-up network (PUN) and pull-down network (PDN)
VDD
PMOS transistors only
…
In1
In2
PUN
InN
F(In1,In2,…InN)
…
In1
In2
InN
pull-up: make a connection from VDD to F
when F(In1,In2,…InN) = 1
PDN
pull-down: make a connection from F to
GND when F(In1,In2,…InN) = 0
NMOS transistors only
PUN and PDN are dual logic networks
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Threshold Drops
VDD
PUN
VDD
VDD
0→
0→
CL
CL
VDD →
PDN
VDD →
CL
VDD
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CL
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Threshold Drops
VDD
PUN
VDD
S
D
VDD
D
0 → VDD
VGS
S
CL
VDD → 0
PDN
D
VDD
CL
VGS
CL
S
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0 → VDD - VTn
VDD → |VTp|
S
CL
D
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Construction of PDN
• NMOS devices in series implement a NAND function
A•B
A
B
• NMOS devices in parallel implement a NOR function
A+B
A
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B
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Dual PUN and PDN
• PUN and PDN are dual networks
– DeMorgan’s theorems
A+B=A•B
[!(A + B) = !A • !B or !(A | B) = !A & !B]
A•B=A+B
[!(A • B) = !A + !B or !(A & B) = !A | !B]
– a parallel connection of transistors in the PUN corresponds to
a series connection of the PDN
• Complementary gate is naturally inverting (NAND,
NOR, AOI, OAI)
• Number of transistors for an N-input logic gate is 2N
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CMOS NAND
A
B
A•B
A
A
0
B
0
F
1
0
1
1
1
0
1
1
1
0
B
A
B
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CMOS NAND
Vdd
NAND
B
B
F
F = NAND(A,B)
A
A
GND
Vdd
B=0
F=1
A=0
GND
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Vdd
F=1
Vdd
B=0
B=1
A=1
A=0
GND
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F=1
Vdd
B=1
F=0
A=1
GND
GND
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CMOS NOR
B
A
0
B
0
F
1
0
1
1
1
0
1
0
0
0
A
A+B
A
B
A
B
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CMOS NOR
Vdd
A
NOR
B
F = NOR(A,B)
B
F
A
GND
Vdd
A=0
A=0
B=0
GND
•VLSI Design I; A. Milenkovic
Vdd
A=1
F=0
GND
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Vdd
A=1
B=0
B=1
F=1
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Vdd
B=1
F=0
GND
F=0
GND
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Complex CMOS Gate
OUT = !(D + A • (B + C))
A
D
B
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C
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Complex CMOS Gate
B
A
C
D
OUT = !(D + A • (B + C))
A
D
B
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C
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XNOR/XOR Implementation
XNOR
XOR
A
A
A⊕B
B
A
B
B
A⊕B
A
B
A⊕B
A⊕B
ƒ
How many transistors in each?
ƒ
Can you create the stick transistor
layout for the lower left circuit?
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Combinational Logic Cells
• CMOS logic cells
AOI221
– AND-OR-INVERT (AOI)
– OR-AND-INVERT(OAI)
And
2
Or
Inverter
A
B
C
Z
2
• Example: AOI221
D
E
1
Z = (A*B + C*D + E)’
Z = AOI221(A, B, C, D, E)
Exercise: Construct this logic cell?
• Example: OAI321
Z = [(A+B+C)*(D+E)*F]’
Z = OAI321(A, B, C, D, E, F)
Exercise: Construct this logic cell?
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AOI221
Vdd
A
B
C
D
E
Z
A
C
E
B
D
GND
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Standard Cell Layout Methodology
Routing
channel
VDD
signals
GND
What logic function is this?
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OAI21 Logic Graph
X
A
j
C
C
B
X = !(C • (A + B))
C
i
X
B
i
A
PUN
VDD
A
j
B
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PDN
GND
A
B
C
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Two Stick Layouts of !(C • (A + B))
A
C
B
A
B
C
VDD
VDD
X
X
GND
GND
uninterrupted diffusion strip
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Consistent Euler Path
ƒ
An uninterrupted diffusion strip is possible only if there exists a
Euler path in the logic graph
ƒ
Euler path: a path through all nodes in the graph such that each edge
is visited once and only once.
X
C
i
X
B
ƒ
VDD
j
A
GND
For a single poly strip for every input signal, the Euler
paths in the PUN and PDN must be consistent (the same)
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Consistent Euler Path
ƒ
An uninterrupted diffusion strip is possible only if there exists a
Euler path in the logic graph
ƒ
Euler path: a path through all nodes in the graph such that each edge
is visited once and only once.
X
C
i
X
B
VDD
j
A
GND
ƒ
A B C
For a single poly strip for every input signal, the Euler
paths in the PUN and PDN must be consistent (the same)
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OAI22 Logic Graph
A
C
B
D
X
C
D
A
B
C
D
X = !((A+B)•(C+D))
VDD
X
B
A
B
C
D
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PUN
A
GND
PDN
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OAI22 Layout
A
B
D
C
VDD
X
GND
‰
Some functions have no consistent Euler path like
x = !(a + bc + de) (but x = !(bc + a + de) does!)
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Combinational Logic Cells (cont’d)
• The AOI family of cells
with 3 index numbers or less
– X = {AOI, OAI, AO, OA}; a,b,c={2,3}
Cell Type
Cells
Number of Unique
Cells
Xa1
X21, X31
2
Xa11
X211, X311
2
Xab
X22, X33, X32
3
Xab1
X221, X321, X331
3
Xabc
X222, X333, X332, X322
4
Total
14
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VTC is Data-Dependent
A
M3 B
3
0.5µ/0.25µ NMOS
0.75µ /0.25µ PMOS
2
A,B: 0 -> 1
B=1, A:0 -> 1
A=1, B:0->1
M4
F= A • B
D
A
M2
VGS2 = VA –VDS1
S
D
B
M1
VGS1 = VB
weaker
PUN
1
Cint
S
0
0
ƒ
1
2
The threshold voltage of M2 is higher than M1 due to the
body effect (γ)
VTn1 = VTn0
VTn2 = VTn0 + γ(√(|2φF| + Vint) - √|2φF|)
since VSB of M2 is not zero (when VB = 0) due to the presence of Cint
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Static CMOS Full Adder Circuit
B
A
B
B
A
Cin
A
B
Cin
Cin
!Cout
!Sum
A
A
B
A
Cin
B
A
B
Cin
A
B
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Static CMOS Full Adder Circuit
!Sum = Cout & (!A | !B | !Cin) | (!A & !B & !Cin)
!Cout = !Cin & (!A | !B) | (!A & !B)
B
A
B
A
B
A
Cin
B
Cin
Cin
!Cout
!Sum
A
A
B
A
Cin
A
B
B
Cin
A
B
Cout = Cin & (A | B) | (A & B)
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Sum = !Cout & (A | B | Cin) | (A & B & Cin)
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