Download VL7102

DOC/LP/01/28.02.02
LESSON PLAN
Sub Code & Name: VL7102 VLSI DESIGN TECHNIQUES
Unit : I
Branch : M.E (AE)
Semester: II
UNIT I MOS TRANSISTOR THEORY
LP – VL7102
LP Rev. No: 00
Date: 16/01/14
Page 01 of 06
9
Syllabus:
NMOS and PMOS transistors, CMOS logic, MOS transistor theory – Introduction,
Enhancement mode transistor action, Ideal I-V characteristics, DC transfer characteristics,
Threshold voltage- Body effect- Design equations- Second order effects. MOS models and small
signal AC characteristics, Simple MOS capacitance Models, Detailed MOS gate capacitance
model, Detailed MOS Diffusion capacitance model
Objective: To understand the concepts of MOS transistors operations and their AC, DC
characteristics.
Session
No.
1.
2.
Topics to be covered
NMOS and PMOS transistors - Operation and its
characteristics, CMOS logic
MOS transistor theory - NMOS, PMOS Enhancement
transistor
Time
Ref
Teaching
Method
50m
1,6
BB
50m
1,6
BB
3.
MOS transistor-Ideal I-V characteristics
50m
4,6
BB
4.
CMOS inverter DC characteristics, Beta ratio effects
50m
1,4,6
BB
5.
Threshold voltage and Body effect
50m
1,4
BB
50m
1,4
BB
50m
1,4
BB
6.
7.
Second order effects - velocity saturation and
mobility degradation, channel length modulation,
subthreshold conduction
Second order effects - Junction leakage, Tunneling,
temperature dependence, Geometry dependence
8.
MOS models and small signal AC characteristics
50m
1
BB
9.
C-V Characteristics - Simple MOS capacitance
Models, Detailed MOS gate capacitance model,
Detailed MOS Diffusion capacitance model
50m
1,6
BB
DOC/LP/01/28.02.02
LESSON PLAN
Sub Code & Name: VL7102 VLSI DESIGN TECHNIQUES
Unit : II
Branch : M.E (AE)
Semester: II
UNIT II CMOS TECHNOLOGY AND DESIGN RULE
LP – VL7102
LP Rev. No: 00
Date: 16/01/14
Page 02 of 06
9
Syllabus:
CMOS fabrication and Layout, CMOS technologies, P -Well process, N -Well process,
twin –tub process, MOS layers stick diagrams and Layout diagram, Layout design rules, Latch
up in CMOS circuits, CMOS process enhancements, Technology – related CAD issues,
Fabrication and packaging.
Objective: To know the fabrication process of CMOS technology and its layout design rules.
Session
No.
Topics to be covered
Time
Ref
Teaching
Method
10.
CMOS fabrication and Layout
50m
1
BB
11.
CMOS technologies - P-well, N-well and Twin-Tub
process
50m
1,4,5
BB, PPT
12.
MOS - Stick diagram and Layout diagram
50m
1,3,5
BB, PPT
13.
Layout design rules-NAND, NOR gate
50m
1,4,5
BB, PPT
14.
Latch up in CMOS circuits
50m
1,3,4
BB, PPT
15.
CMOS Process enhancement - SOI Process,
Interconnects
50m
1,6
BB, PPT
16.
CMOS Process enhancement - circuit elements
50m
1,6
BB
17.
Technology related CAD issues
50m
6
BB
18.
Fabrication and packaging
50m
1
BB
CAT I
180m
-
-
DOC/LP/01/28.02.02
LESSON PLAN
Sub Code & Name: VL7102 VLSI DESIGN TECHNIQUES
Unit : III
Branch : M.E (AE)
Semester: II
UNIT III INVERTERS AND LOGIC GATES
LP – VL7102
LP Rev. No: 00
Date: 16/01/14
Page 03 of 06
9
Syllabus:
NMOS and CMOS Inverters, Inverter ratio, DC and transient characteristics , switching
times, Super buffers, Driving large capacitance loads, CMOS logic structures , Transmission
gates, Static CMOS design, dynamic CMOS design.
Objective: To understand the latch up problem in CMOS circuits.
Session
No.
Topics to be covered
Time
Ref
Teaching
Method
19.
NMOS and CMOS Inverters, Inverter ratio
50m
1,2
BB
20.
DC and transient characteristics
50m
1,2,3
BB
21.
Switching times
50m
1,2
BB
22.
Super buffers
50m
1,2
BB
23.
Driving large capacitance loads
50m
1,3
PPT
50m
1,3
PPT
50m
1
PPT
24.
25.
CMOS logic structures – BiCMOS logic, Pseudo
nMOS logic, Pass transistor logic,
CMOS logic structures – BiCMOS logic, Pseudo
nMOS logic, Pass transistor logic, transmission
gate, CMOS Domino logic
26.
Static CMOS design
50m
1
PPT
27.
Dynamic CMOS design
50m
1
PPT
DOC/LP/01/28.02.02
LP – VL7102
LP Rev. No: 00
Sub Code & Name: VL7102 VLSI DESIGN TECHNIQUES
Date: 16/01/14
Unit : IV
Branch : M.E (AE)
Semester: II Page 04 of 06
LESSON PLAN
UNIT IV CIRCUIT CHARACTERISATION AND PERFORMANCE ESTIMATION
9
Syllabus:
Resistance estimation, Capacitance estimation, Inductance, switching characteristics,
transistor sizing, power dissipation and design margining. Charge sharing .Scaling.
Objective: To study the concepts of power estimation in CMOS circuits and their sizing
methods.
Session
No.
Topics to be covered
Time
Ref
Teaching
Method
28.
Resistance estimation
50m
1,6
BB
29.
Capacitance estimation
50m
1,6
BB
30.
Inductance
50m
1,6
BB
31.
Switching Characteristics
50m
1,2,4
BB
32.
Transistor Sizing
50m
1,2,4
BB
33.
Power dissipation-Static and Dynamic power
dissipation
50m
1,6
BB
34.
Design margining
50m
1,6
BB
35.
Charge sharing
50m
1
BB
36.
Scaling
50m
1
BB
CAT II
180m
-
-
DOC/LP/01/28.02.02
LESSON PLAN
Sub Code & Name: VL7102 VLSI DESIGN TECHNIQUES
Unit : V
Branch : M.E (AE)
Semester: II
LP – VL7102
LP Rev. No: 00
Date: 16/01/14
Page 05 of 06
UNIT V VLSI SYSTEM COMPONENTS CIRCUITS AND SYSTEM LEVEL
PHYSICAL DESIGN
9
Syllabus:
Multiplexers, Decoders, comparators, priority encoders, Shift registers. Arithmetic
circuits – Ripple carry adders, Carry look ahead adders, High-speed adders, Multipliers. Physical
design – Delay modelling, cross talk, floor planning, power distribution. Clock distribution.
Basics of CMOS testing.
Objective: To know the concepts of delay calculations and testing in CMOS circuits.
Session
No.
Topics to be covered
Time
Ref
Teaching
Method
37.
Multiplexers, Decoders
50m
1,2
BB
38.
Comparators, priority encoders
50m
1,2
BB
39.
Shift registers. Arithmetic circuits – Ripple carry
adders
Carry look ahead adders, High-speed adders,
Multipliers.
50m
1
BB
50m
1
BB
40.
41.
Physical design – Delay modelling, Cross talk
50m
1,2
BB
42.
Floor planning, power distribution. Clock
distributionDesign margin
50m
1
BB
43.
Adhoc tesing, Scan based testing
50m
1,6
BB
44.
Built in self testing
50m
1,6
BB
45.
Boundary scan testing
50m
1,6
BB
DOC/LP/01/28.02.02
LESSON PLAN
Sub Code & Name: VL7102 VLSI DESIGN TECHNIQUES
Branch : M.E. (Applied Electronics)
Semester: II
LP – VL7102
LP Rev. No: 00
Date: 16/01/14
Page 06 of 06
Course Delivery Plan:
Week
Unit
Test
1
I II
2
I II
3
I II
4
I
II
I
T1
II
T2
5
I II
C
A
T
I
6
I II
-
7
I II
8
I II
IV
III
T3
9
I II
T4
10
I II
C
A
T
II
11
I II
I
12
II
13
I II
V
-
T5
Note: T1, …., T5: Fortnightly Test; CAT: Continuous Assessment Test
REFERENCES:
1. Neil H.E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design, Pearson
Education ASIA, 2nd edition, 2000.
2. John P.Uyemura “Introduction to VLSI Circuits and Systems”, John Wiley & Sons, Inc.,2002.
3. Eugene D.Fabricius, Introduction to VLSI Design McGraw Hill International Editions, 1990.
4. Pucknell, “Basic VLSI Design”, Prentice Hall of India Publication, 1995.
5. Wayne Wolf “Modern VLSI Design System on chip. Pearson Education. 2002.
6. Weste and Harris: CMOS VLSI DESIGN (Third edition) Pearson Education, 2005.
Prepared by
Approved by
Name
Ms.R.Kousalya
Dr.S.Ganesh Vaidyanathan
Designation
Assistant Professor
HoD - EC
Date
16/01/2014
16/01/2014
Signature
-
-