Download Reducing risk of electrical stress for mission critical items by stress

Reducing Risk of Electrical Stress for Mission Critical Items by
Stress Derating Analysis
Yizhak Bot, BQR, [email protected]
Abstract
Electronic assemblies are more and more smaller as well as complex and use very
complex IC's with more than 1000 pins. The power dissipation and the temperature
are increasing constantly for new design. This may cause high risk for mission critical
systems and as reliability engineers we need to help designers to reduce such risk.
One of the main analyses which is done manually or by SPICE programs is “Stress
Analysis and Derating”.
The challenge is to perform such analysis on the schematic level before layout on
large boars such as 100,000 pads with 25,000 components in short time before the
layout so we can still change the design in no cost.
In this article we will demonstrate a method that should be implemented during the
design phase of electronic boards which will help the designer and the reliability
analyst to detect components with high operational stress. The stress level can be
power, volt, current or temperature. This technique will reduce the time to market and
the risk that an electronic assembly can fail during a mission. In addition we will
demonstrate in this article how the stress data can be used to perform a MTBF
prediction using: Telcordia and Mil-hdbk-217 and service life for warranty
commitment.
Abbreviations:
SCDM: Stress calculation, Derating and MTBF
OS: Over Stressed
US: Under Stressed
SDC: Stress Derating Curves
The Stress Levels
Electrical stress is the important parameter which a designer should take under
consideration in order to control and to reduce the risk of failures. Picture 1 describes
the different areas of a stress. Normally the manufacturer of the component describes
the rating value as 100% at 25c going to zero at Tmax. For safety reasons we would
like to use the component up to 50% from the rating value going down to Ts. This
definition is called de-rating. We can define area "I" as the safe area, area "II" as over
derating and area "III" as the over stress. It is not acceptable to use a component in
area "II" and "III". We also need to take under consideration of the temperature of the
component, since it is also a parameter which affects the result.
Stress
100
%
(III) Over
stress area
(II) Over derating stress
50
%
area
(I) Acceptable operating
area
Temperature
25
c
Ts
Tma
x
Picture 1: Derating criteria fro electrical stress
The impact of Electrical Stress
From picture 2 we can see that the average risk of failure increases 2.5 times if we
increase the stress from 10% to 60% at 25c, in 85c the risk increased 3.5 times. This
means that the risk is also depends on the temperature, so we need to reduce the stress
and the temperature. The slope of the risk is depending on the type of component, for
example for semiconductors the 2.5 is replaced by 25. This means that for
semiconductors the risk will increase by 25 when the stress increased from 10% to
60% at 25c.
Risk (1e-6)
0.034
1.0
.9
.8
.7
.6
.5
.4
.3
.2
.1
0.03
0.029
0.026
3.5
0.022
0.018
0.014
0.01
0. 0084
0.006
2.5
0.0046
stress 10%
stress 20%
stress 30%
stress 40%
stress 50%
stress 60%
stress 70%
stress 80%
stress 90%
stress 100%
0.002
0 20 30 50 60 70 80 90 100 110 120 130 140 150 160
Temp (c)
Picture 2: Average Risk - versus - Stress & Temperature.
Types of Stress Analyses
Most of the designers are performing the stress analysis manually. This method
suffers from many hours of investment, low accuracy and the unwilling to perform it
again after a change in the design. Picture 3 describes the 3 main popular options used
by designers.
Option 1 - Defining stress defaults such as: all resistors 30% stress, all capacitors 40%
and so on or some manual calculations for some of the components. This method will
prove the stress analysis as not useful and will not reduce the risk of failures.
Option 2 - Using an automated CAD tool which will be described in the following
Paragraphs. In this case the stress levels will be calculated accurately and in a short
time. The use of such a tool is depending on a component data base which must exist
prior the calculation.
Option 3 - Use of a thermal analysis results together with the stress analysis to
perform a stress derating. This option is the best one to really reducing the risk of
component stress in electronic design
Stress
Defaults or
Manually
Bill of Materials,
External Sources
& Loads
Stress
Calc
Tool
Applied
Values
Option 1
Reliability
Prediction
MTBF
Option 2
Average Δt
Stress
Derating
Over/Under
Stressed
Component
s
Option 3
Data
Base
Thermal
Analysis
Thermal
Mapping
Option 1: Stress Defaults or Manually
Option 2: Automatic stress w/o Thermal mapping
Option 3: Automatic stress With Thermal mapping
Picture 3: Stress Analysis procedure
The decision work flow
Many companies are not performing any SCDM, counting on their designers for
doing a good job.
To perform a complete risk reduction we need to follow 3 steps (See Picture 4):
Stress Calculation: in this step we will use the Bill Of Materials (BOM), the NET list
(a file which describe the connection between the components), the voltages of the
external power supplies and external loads (the loads are needed to close the loops,
otherwise the stress calculation will be performed without loads). The result will be a
table with numerical results of the actual Volt, Power and Current (VPC) developed
on each component.
1. Stress Calculation
2. Stress Derating
3. MTBF
Net List
Bill of Materials
Loads &
Sources
Stress Calculation
Applied Stress
Stress
Derating
Re-Design
Critical (over stressed)
Components were found –
The Design is not Approved!!!
No Critical Components (over stressed)
were found - The Design is approved!!!
MTBF
Picture 4: The decision work flow
Stress Derating: In this step we will check the actual VPC with the required derated
value taken from the derating curves at the operating temperature. If the stress is
below the derating level we can continue to the 3'rd step for this component. This
action is done for each component. Any component which is Over Stressed or Under
Stressed needs redesign (See next Paragraph). After checking all components and if
the stress of all components is derated we can continue to the next step.
MTBF prediction: in this step we will calculate the failure rate of each component
based on the actual stress level. The failure rate of the component represents the risk
of failure. As mentioned before if the stress level is low the risk will be also low.
We can call the above steps as SCDM (Stress Calculation, Derating and MTBF).
The Over Stressed and Under Stressed Components
The rating of components depends on the physical size. This means that a larger
component have a higher rating and vise versa.
Over Stressed (OS) component is defined as the actual stress developed is over the
stress limit. In this case we need a larger component.
Under Stressed (US) component is defined as the actual stress is very low (Less than
10%, and can be predefined for each application). This means that we have selected a
large component. In this case we can select a smaller component.
By performing a good SCDM we can say that:
OS - Reducing stress  reducing risk.
US - Reducing size  reducing board size & weight -> saving money.
In both cases we see that we benefit from the process either by reducing Risk or
saving money.
Who will perform the SCDM
The most popular question we faced from my experience is who will perform the
SCDM.
Each company has different design culture and use several design CAD tools. In
addition there are different organizational hierarchies . In one company the SCDM is
the responsibility of the electronic designer and in another company the Reliability
engineer.
My personal proposal is to mix the responsibility as follows:
The Reliability Engineer: Is responsible for defining the Stress Derating criteria for
every application used such as: Ground, Mobile and Air Etc. To collect the results of
the SCDM performed by the designers to a system level analysis.
The Electronic Designer: To perform the SCDM integrated with the CAD tool. To
provide the final results to the Reliability engineer.
The components librarian: To maintain the components library so designers can
perform the SCDM without any delay during design.
When during the design cycle to perform the SCDM
We can define the following:
After we get failures from field (10,000$ damage cost)
After first article production and qualification test (1000$ damage cost)
After board layout (100$ damage cost)
After schematic diagram is ready (no damage cost).
For damage cost we mean, the cost involved to make a redesign to solve the stress
problem, so if we find a problem in field and not during the design we will need
10,000$ to correct the design.
My recommendation is to start performing the SCDM after the schematic is ready and
finalize it before the board layout. This will avoid using wrong components, reduce
the Risk and will reduce the design cycle and cost.
Standard for Stress Derating Curves
Each company must have an internal standard for SDC. There are several
international standards which are based mostly on the MTBF prediction models. If we
take the IEC62380 (Picture 5) model as example we can see the derating curve for
variable resistors.
Picture 5: IEC62380 model derating curve for variable resistors
Stress improving recommendation – example
See picture 6 as an example for an over stressed resistor for the PWavrg (Power
average) parameter. The max rating is 5Watts, the applied value is 4.5 Watts, the
derating limit is 29% @ 85c, this means that we can dissipate only 1.448Watts, the
derated stress is 310.7 % and from the max rating is 90%. The recommendation will
be to use a resistor with 15.5Watts rated at least.
Picture 6: Stress recommendation for a resistor
Automated procedure for stress analysis
To perform such analysis for each component for large Printed circuit boards we need
an automatic software tool.
The tools are divided into 2 technologies: SPICE and Stress-Calculators.
SPICE based tools are used for small analog circuits and not for large digital circuits,
mostly for power supplies. The main advantage of the SPICE tool is providing the
wave form of the signals. Some time the simulation can't converge and take very long
time to run. The models are also very complicated and cost a lot of money to generate,
some time impossible, for example consider a SPICE model for a CPU's, Memories or
DSP's.
Stress-Calculators are based on Electrical Loops used for very large digital/analog
circuits. This method runs very fast, the components models are very simple, even for
CPU, Memories and DSP's, and the results are presented in tabulated format exactly
as we need for the derating analysis.
More important, the SCDM method provides the maximum value for each parameter
that can evolve during the operation in this specific board, for example the component
IRFBG20 presenting in Picture 7. We can see from the graphical result that the Vtotal
is 640V Max and 424 VRMS, we can't see the Power or the Current. In the tabulated
report we can see all values with the corresponding Power, Voltage and Current. The
SPICE model provides the values for one operation mode, such as ON or OFF. In the
SC method we get the Voltage for the OFF mode and the Current for ON mode.
640V max
424V RMS
0V
Picture 7: Graphical versus tabulated results
The stress model solver uses new technique to build stress matrix by individual cells
as in Picture 8. Each cell is connected via the Netlist and compressing method reduces
the size of the matrix to receive quick results in minutes.
Input
Ground
Rin
Rin
Vcc
Vcc-out
Rout
Rout
Picture 8. General calculation model for single cell in the stress matrix
Output High
Output Low
The last step of MTBF prediction
After we have completed the stress calculation and derating we can predict the MTBF
by using the various models. As result we can see how the MTBF is reduced (Risk
increased) for a board if the temperature increased, see picture 9.
Picture 9: MTBF versus Temperature