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Multioperand Addition
 
Add up a bunch of numbers
 
Used in several algorithms
 
Signed (two’s comp) and unsigned
  Multiplication,
MULTIPLE OPERAND
ADDITION
  Don’t
recurrences, transforms, and filters
deal with overflow…
Chapter 3
Bit Arrays
 
Sign Extension
Simplify things by assuming that all arguments have
the same range of values
  Bit
arrays are rectangular
you may end up sign-extended operands
  If you are adding m operands where each operand is
an n-bit array: the sum has n+p bits
  Means
  Extend
operands (0-fill or sign-extend) to n+p bits
Sign Extension Trick
 
Sign extension requires that all the adder bits for
the sign extended bits be implemented
  A
trick for collecting all the sign extensions into one
extra term is:
  Recall:
Sign Extension Trick
 
Apply identity
 
So this transforms signed operand
to be replaced by
 
In other words: represent x as a fraction, and because
of two’s comp, x0 has negative weight
  Now
you can invert the x0’s and add up number of
times you did that
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Sign Extension Trick
Example for m=5
 
 
-5=1011
What happens if we add this to x0’ ?
  1+x0’
= 1+(1 - x0) = 2 - x0
10-0=10, 10-1=01,
1+x0’=x0’ x0
  0+x0’=x0’
(Show Example…)
Example for m=5
Reduction
-5=1011
  What happens if we add this to x0’ ?
 
 
Primitive operation in multioperand addition
  Produces
a smaller output bit-array by adding the
inputs bits
  Main approaches are:
  Reduction
  Reduction
by rows (using adders or compressors)
by columns (using counters)
  1+x0’
= 1+(1 - x0) = 2 - x0
10-0=10, 10-1=01,
1+x0’=x0’ x0
  0+x0’=x0’
[p:2] Adders
Example with [3:2] adders
Reduce p bit-vectors to 2 bit-vectors
  This means carry-save form at the output
 
  [3:2]
adder is a regular full adder
  [4:2] adder adds two carry-save inputs
  [5:2], [7:2] take even more rows as inputs and reduces
them to two output rows
3:2
4:2
5:2
P=3
vs
vc
x
y
z
••••
••••
••••
••••
• • • • • Cin
3:2
7:2
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Example with [4:2] adders
P=4
vs
vc
w
x
y
z
••••
••••
••••
••••
••••
• • • • • Cin
[4:2] Compressor Adder
4:2
Note that even though it looks like carry is propagated,
the Cout from each [4:2] cell is computed directly
from the A and B inputs…
General Case
k can be
Greater than 1
In General
General [p:2] adder
  Consider
p vectors
them up into kbit chunks
  End up with k-wide [p:
2] adder
  Imagine k=1, p=3
 
  Break
  Minimize
columns, but pay
attention to max possible
values
  Also minimize
carries H
  Then
you can use
regular [3:2] adders…
  Note hout doesn’t wait
for hin
Typical [p:2] modules
p
3
4
5
6
7
9
11
H
1
2
3
4
5
7
9
Complexity depends on #
of columns k
k
1
2
2
3
3
3
4
[4:2] Adder
W
1
4
3
10
9
7
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 
P=4
  4
rows of bit operands
2 carry save ops)
  (or
 
K=2
 
H=2
 
W=4
  Clumps
  2
of 2 bits
“carry” bits
  3
bits of intermediate
sum
  W is computed from
inputs only (no carries)
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[5:2] Adder
 
P=5
  5
 
 
K=3
 
H=5
 
W=9
H=3
  5
“carry” bits
W=3
of 3 bits
“carry” bits
  4
bits of
intermediate sum
Rows vs. Columns
(p:q] Counters
Reduction by rows adds up p rows and produces a
vector of 2 rows (carry save)
  Different
adders may take a different sized clump
  Deals with carries from previous stage, and produces
carries to next stage
  No
rows of operands
  Clumps
bits of intermediate
sum
 
 
of 2 bits
  2
 
P=7
  7
K=2
  3
 
rows of operands
  Clumps
 
[7:2] Adder
propagation further than one stage though!
Reduction by columns adds a whole column
 
Add up a column of p bits
  Result
is q bits that represent the sum of those column
bits
  If p inputs, then max output value is p (all ones)
  For example, ten rows (p=10)
  You
must be able to represent “ten” in q output bits
 
  Produces
  As
a single-row output
many bits as necessary for that size column
(p:q] Counters
(7:3] Counter
Add column of p bits of the same weight
Produce q bits of adjacent weights
(3:2], (7:3], and
(15:4] are examples
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Gate Network for (7:3]
 
Input is seven binary bit-vectors
 
Output is three bits
 
Gate Network for (7:3]
 
Partial sums of subvectors are
 
Sum qA is like a full adder (three inputs)
Partition the input array into two subvectors
X A = (x 2 , x1, x 0 )
X B = (x 6 , x 5 , x 4 , x 3 )
€
Gate Network for (7:3]
Gate Network for (7:3]
X6
X5
X4
X3
qB2
qB1
qB0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
1
0
1
0
0
1
0
0
0
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
0
0
1
1
1
0
1
1
1
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
1
0
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
0
Gate Network for (7:3]
 
Finally, q=qA+qB
sum
Carry from 0
G1
P1·G0
Multicolumn Counters…
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Sequential Implementation
 
Sequential Implementation
If your input array is
big
  You
can add rows
sequentially
  Uses only one adder
and a register
Sequential Implementation
Sequential Implementation
 
m operands
  4
  Each
  Using
  In
Combinational Implementation
 
m/(p-2) iterations
operands = 4/(3-2) = 4 iterations with [3:2] adders
iteration adds 1 row plus s and c
[4:2] adders = 4/(4-2) = 2 iterations
each iteration you add 2 rows plus s and c
Linear Array
Reduction by rows
  Linear
  Tree
 
array of [p:2] adders
of [p:2] adders
Reduction by columns
  Using
(p:q] counters
Last adder may have additional
bits for the sign extension trick
we saw at the beginning of the
chapter.
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Adder Trees
 
Adder Trees
Because addition is associative, you can organize as
a tree
  Number
of adders is the same (same number of
inputs…)
l
1
2
3
4
5
6
7
8
9
ml
3
4
6
9
13
19
28
42
63
Reduction sequence
Adder tree for 9 operands
Three-level tree (6 operands)
6
4
3
Four-level tree (7 vs 9 operands)
5-level Tree (13 inputs)
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Tree of [4:2] adders for m=16
Reduction by Columns
 
Use multiple levels of
(p:q] counters to reduce
the columns to rows
  This
example uses 4
(7:3] counters
  Each counter counts the
1’s in one column
  Then add the rows
Reduction by Columns
 
Why draw it that way?
Reduction by Columns
1 0 1 1 11
0010 2
1001 9
0110 6
1 0 1 0 10
1 1 1 1 15
0110 6
011
11 0
011
100
1 1 1 0 1 1 59
Number of Counter Levels
 
Why draw it that way?
1 0 1 1 11
0010 2
1001 9
0110 6
1 0 1 0 10
1 1 1 1 15
0110 6
011
11 0
011
100
1 1 1 0 1 1 59
Sequences of Counters
How many rows can be reduced with L levels of counters?
(3:2] counters
(7:3] counters
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Example with (7:3] and 15 rows
Systemic Design Method
Table says we can do
it in 2 levels of counters
(example…)
Reduction Process
Relation at Level l
FA takes 3 bits, produces 1 sum
(reduction of 2)
HA takes two bits, produces 1 sum
Use a mix of FA
and HA cells. Transfer
the other bits.
Plus carry bits from
column to right
Why not 4 FA?
Relation at Level l
Relation at Level l
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Example
m=8, n=5 (26 FA, 4HA)
 
Build array to compute
  Operands
are integers in the range –4 to 3
comp
  Compute range of result…
  Two’s
  Thus
f requires 6 bits
3b and 3c into 2b+b and 2c+c
  Decompose
Example: f=a+3b+3c+d
Example: f=a+3b+3c+d
Note left shifts
to compute 2b
and 2c…
Use sign extension trick
Keep track of weight of
sign extension bits!
-4x4 + -8x2 = -32
-32 = 100000
Example: f=a+3b+3c+d
Example: f=a+3b+3c+d
Remember the 100000 (-32)
Determine adder types at each level
* Helps by reducing the width of the CPA
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Example: f=a+3b+3c+d
Example: f=a+3b+3c+d
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Example: f=a+3b+3c+d
••••••
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Pipelined Arrays
You can always add pipelining to increase throughput!
Partially Combinational Arrays
Partially Combinational Arrays
Note that if the partial sum
is added to the top of the array,
you can’t pipeline.
Here’s a general technique for
summing q operands per
iteration
Non-pipelined
Pipelined
k operands are added per iteration (k = 4 in these examples)
m/k iterations required for complete result
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Conclusion
 
Lots of ways of adding up a bunch of numbers
  Arguments
are a bit-array
that bit array by reducing rows or columns
  End result is typically in carry-save form
  Reduce
  So
you might need a CPA if you want the answer in
conventional form
  Pipelining
is always an option
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