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Outline
Background of this work
Abnormal leakage suppression scheme
Circuit design
Measurement results
Summary
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Backgrounds
Portable equipments
Notebook PC, Phone, etc.
Long lifetime of batteries
SRAM = key component
Cache / main memory, etc.
Low standby current SRAM
Leakage current due to cell defects
has not been eliminated.
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
How to eliminate abnormal leakage
Systematically isolate error cells from
or
VDD lines
VSS lines
However…
VSS lines are usually structured as a mesh.
Difficult to cut off selectively
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Possible leakage sources in
standby mode
Word lines are fixed to ground.
Bit lines are precharged to V DD.
Leakage current sources
1 Cell V DD lines
2 Bit lines
3 N wells
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Leakage paths from cell V DD lines (1)
WL driver
V DD
V DD
Word line (=low)
Cell V DD
on
LP2
off
M5
Bit line
M6
M3
M4
Defect
Leakage path(LP)
© 2001 IEEE International Solid-State Circuits Conference
Bit line
LP5
© 2001 IEEE
Leakage paths from cell V DD lines (2)
V DD
V DD
Word line (=low)
on
off
M5
M6
M3
Bit line
Defect
Leakage path(LP)
M4
LP3
© 2001 IEEE International Solid-State Circuits Conference
Bit line
LP4
© 2001 IEEE
Leakage paths from bit lines
V DD
V DD
Word line (=low)
M1 M2
LP1
M5
Bit line
M6
M3
M4
Defect
Leakage path(LP)
© 2001 IEEE International Solid-State Circuits Conference
Bit line
LP6
© 2001 IEEE
Abnormal Leakage Suppression
(ALS) scheme
Monitor current through each cell VDD line
and bit line with a leakage sensor.
Sensors output 1(error) or 0(normal).
Read out the bit pattern by a shift register.
Identify the location of errors.
Isolate error cells from V DD by blowing
additional fuses.
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Whole structure of ALS SRAM
VDD
Sensor
Sensor
Shift register DFF
VDD
DFF
Fuse
Shift register
Fuse
Sensor DFF
Cell VDD
Bit
lines
Sensor
DFF
Column
sensors
output
Cell
Cell VDD
Cell
Array
Row sensors output
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
3.0mm
256
rows
Memory
cells
256
columns
Column leakage sensors
+ shift register
Row leakage sensors +
shift register
Microphotograph of SRAM chip
2.7mm
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Microphotograph of sensors
and fuses
Leakage sensor and DFF
Fuse
Cell VDD line
Leakage sensor : one per 2 rows/columns
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Chip design and technology
Technology
0.6µm CMOS
3 Metals
3.3V Power Supply
ALS SRAM design
64kb (256 rows and 256 columns)
Total area : 8.1mm 2
ALS area overhead : 7%
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Area overhead[%]
Area overhead vs memory capacity
7
6
5
4
3
2
1
0
For 4M bit SRAM,
area overhead is
less than 1%.
64k 256k 1M 4M 16M 64M
Memory capacity [bit]
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Schematic of ALS circuits
Leakage sensor
VDD
VLEAK MONITOR
M7
M8
Test
Enable
Leakage
Sensor
(=voltage
comparator)
V REF
Shift
Register
Sensor
Output #1
Fuse
to
bit lines
or cell VDD
DFF
Sensor
Output #2
Control signals
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Circuit schematic of leakage sensor
Leakage sensor
VDD
VLEAK MONITOR
V REF
Test
Enable
N2
Hold
Shift
Register
output
#1
N1
SE
fuse
to
bit lines
or cell V DD
DFF
output
#2
φ transfer
SE
Hold
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Operation of leakage sensor
VDD
VLEAK MONITOR
Control signals for sensors
Hold
φ transfer
Test
Enable
SE
Hold
SE
φ transfer
SE
VREF Hold
<Leakage sensor>
φ1
φ2
Non-overlapping clock for
shift register
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Shift register circuit and operation
Shift
Register
Output #1 Output #2
Leakage sensor
φ2
φ1
φ2
φ1
Control signals for
shift registers
φ1
φ2
Shift
register
output
© 2001 IEEE International Solid-State Circuits Conference
“1” “0”
error normal
© 2001 IEEE
Measured sensor sensitivity
VLEAK MONITOR [V]
VLEAK MONITOR
VDD M7
M8
VREF
<Leakage sensor>
VDD =3.3V
3
Measurement
1µA
2
1
10µA
ILEAK=50µA
0
0
1
© 2001 IEEE International Solid-State Circuits Conference
2
VREF [V]
© 2001 IEEE
3
Measured leakage reduction
V DD
do not blow
blow
Cell V DD
blow
Cell V DD
Normal memory cell
Error cell
(made intentionally)
150
Leakage current [µ
µA]
Cell V DD
100
Measurement
≈40µ
µA
50
0
0
1
2
3
4
Number of blown fuses
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE
Conclusion
ALS scheme for low standby current SRAMs
is proposed.
Leakage current due to device defects is
detected and eliminated by using leakage
sensors, shift registers, and fuses.
µm design rule
Test chip fabricated by 0.6µ
ALS detects 1µA order leakage current.
Area overhead is about 1% in 4Mb SRAM.
© 2001 IEEE International Solid-State Circuits Conference
© 2001 IEEE