Download Rapid Single Flux Quantum Logic

Rapid Single Flux Quantum Logic
15 March 2012
Anna Herr
Based on lectures at Chalmers University of Technology, Sweden
Unclassified // For Offical Use Only
Fundamental advantages of
superconducting digital electronics
•
Zero resistance wires
300 GHz interconnects
•
Meissner effect
Quantum accurate digital bits
Digital ”1”
Φ 0 = h ≈ 2.07 × 10 −15 Wb
2e
r
B
•
Josephson effect
S
I
Φ0
Js
Fast and low energy digital logic
V
0.5 mV
E = 2 10-19 J
0.5 ps
S
2
Based on lectures at Chalmers University of Technology, Sweden
Unclassified // For Offical Use Only
t
1600 devices
2.5 µW at 12 GHz
Digital bits encoded as Single Flux Quanta
(SFQ)
Magnetic Flux Quantization
Digital ”1”
Digital ”0”
Φ0 = h
r
B
Josephson junctions
Φ0
Js
≈ 2.07 × 10 −15 Wb
2e
Φ 0 = 2.07 mVps = 2 mApH
Superconducting state
I < I c , I = I C sin ϕ
Voltage stage
Φ 0 dϕ
I > I c , V (t ) =
2π dt
3
Based on lectures at Chalmers University of Technology, Sweden
Unclassified // For Offical Use Only
Josephson junction dynamics:
High Q vs. low Q
SPICE model
L=
Φ0 1
2π I c
L
C
Rt
Rs
Latching voltage
RN
I
Ic
Ic IcRN C
Unshunted
High Q, slow
Superconducting
branch
Resistive
branch
V
>1 ns
-Ic
U/Ec
Single Flux Quantum pulse
-1
-3
4
V (t) =
Φ0=2.07 mVps
<2 ps
-4
-5
RC
Shunted
V
Low Q, fast
-2
0
1
2
3
4
ϕ/2π
L/R
Based on lectures at Chalmers University of Technology, Sweden
Unclassified // For Offical Use Only
LC
t
Φ0 dϕ
2π dt
∫ V (t )dt = Φ
0
Josephson junctions
SPICE model
L=
Φ0 1
2π I c
L
C
Rt
Rs
ω=
2π
V (t )
Φ0
RC
Ic IcRN C
L/R
∫ V (t )dt = Φ = 2 mVps
• Quantum mechanically accurate digital bits
• Energy
∫ I (t )V (t )dt ≈ I Φ
c
0
ω p = LC
0
>> k BT 4.2 K
Ic ≥ 0.1 mA
IcΦ0 =2 10-19 J
Speed scales linearly with dimensions: √C
0.8 µm ->tSFQ = 1.5 ps (1.5 µm -> 3 ps)
Junction
Manufacturing grid of 10 nm
Junction precision 0.2 nA
Shunt resistor precision 40 mΩ
Shunt
5
Unclassified // For Offical Use Only
2 µm
SFQ logic: energy and speed
SFQ pulse energy scales with temperature
∫ I (t )V (t )dt ≈ I Φ
c
T= 4.2 K
0
>> k BT
IcΦ0 = 2 10-19 J
Ic ≥ 0.1 mA
IcΦ0 /kBT > 1000
BER = 10-40
Speed scales linearly with dimensions:
C
2
(
I
R
)
2
π
c
N
β c = RC (L R ) =
cf ≤ 2
Φ0
jc
jc – critical current density
IcRN – characteristic voltage
6
ωc =
2π
I c RN
Φ0
0.8 µm ->1.5 ps
IcRN = 1.0 mV
1.5 µm -> 3 ps
IcRN = 0.5 mV
S. Tolpygo, at el, IEEE TRANS ON APPLIED SUPERCOND, VOL. 17, 2007
Unclassified
// For Offical
Use Only of Technology, Sweden
Based on lectures
at Chalmers
University
RSFQ circuits
Non-quantizing loop
Josephson Transmission Line
Ic L < Φ0
Ib
Ic1 = Ic0 – transmission
2L
L
Ic1 > Ic0 - amplification
Ib
J0
J1
J1
J0
IcL ≈ Φ0/2
Pulse propagation
Ib= 0.7(Ic0 +Ic1)
Reset
Set-Reset Flip-Flop
Quantizing loop
Ic L > Φ0
Ic1 = Ic0 = Ic2
J0
S
Output
J1
1
0
Ib= 0.7Ic0
J2
Set
S
R
IcL ≈ Φ0
Ib
Reset
R/Output
Ib
J2
Set
J2 and J1 form balanced comparator
margins 30%
Unclassified
// For Offical
Use Only of Technology, Sweden
Based on lectures
at Chalmers
University
J0
J1
Output
RSFQ logic convention
Clock period
Clock period
Clock
”1”
hold time
Data input
”0”
setup time
”1”
Data output
Output delay
XOR (Exclusive Or)
A
B
XOR
0
0
0
1
0
1
0
1
1
1
1
0
B
A
Clock
Output
Unclassified
// For Offical
Use Only of Technology, Sweden
Based on lectures
at Chalmers
University
RSFQ fabrication process and mask layout
SiO2
Nb
Superconductive inductor over ground plane
• Localized field
wira (M2)
• Inductance is per square
• Negligible crosstalk
gnde (M0)
wira (M2)
w
dm
0.45 µm
• Negligible losses
• Scales with feature size
9
Unclassified
// For Offical
Use Only of Technology, Sweden
Based on lectures
at Chalmers
University
Ground plane
0.8 µm
RSFQ logic/memory family
• High speed up to 750 GHz for single asynchronous cells
and up to 200 GHz for LSI devices
• Low power consumption 0.2 nW/GHz per pulse
• Superconducting microstrip lines for ballistic transfer of
data over arbitrary distances
Prof. K.K. Likharev
• Complete library of digital gates
• Simple fabrication technology
• Operational temperature < 10K.
Prof. V.K. Semenov
RSFQ logic/memory family: a new Josephson-junction
technology for sub-terahertz-clock-frequency digital systems
IEEE Trans. On Applied Supercond, Vol. 1, No. 1, 1991
Dr. O.A. Mukhanov
Unclassified
// For Offical
Use Only of Technology, Sweden
Based on lectures
at Chalmers
University
Applications: Power, speed, accuracy,
operating temperature
Device
Junction count
Application
A/D and D/A converters
104
Radar and telecommunication
Digital Signal Processing
106
Radar and telecommunication
Digital SQUID
104
Biomagnetic applications,
nondestructive evaluation
Readout for large array of sensors
104
Radio astronomy, material science
Time-digital converters
103
High-energy and nuclear physics
Digital Correlator
104
Radio astronomy
General purpose microprocessor
>>106
Supercomputing
Control for qubit
103
Quantum computing
11
Unclassified
// For Offical
Use Only of Technology, Sweden
Based on lectures
at Chalmers
University
RSFQ progress
•
Japan: governmental project over 6 years with 50 M$ budget
– 2005: 10 metallization layer process
– 2006: demonstration of the microprocessor
– 2007: cryocooler packaged prototype of the packet switch
•
USA: military contracts at Hypres Inc.
– 2005: cryocooler packaged prototype of the Ka-band digital receiver
– 2006: cryocooler packaged prototype of the X-band digital receiver
– 2007: demonstration at ARMY and AIR FORCE facilities
•
USA: military contracts at Northrop Grumman Inc.
– 2002: demonstration of the 60 Gbps chip-to-chip communication
– 2006: demonstration of the 10 Gbps output link
– 2007: break through on the second order ADCs
•
Europe: Swedish national and EU projects at Chalmers University
– 2005: demonstration of Digital Signal Processor components
– 2007: assembling of the cryocooler based DSP system
12
Unclassified
// For Offical
Use Only of Technology, Sweden
Based on lectures
at Chalmers
University
Scaling to VLSI circuits is challenging
• High static power dissipation
• Power applied in parallel
• High overhead in Josephson junctions for clock distribution
7
10
CryoCMOS
6
Gate Power / kBT
10
RSFQ
5
10
4
10
3
10
Ebit=1000 kbT
2
10
1
10
0
10 -4
10
-3
10
-2
10
-1
10
Activity Factor
13
Unclassified
// For Offical
Use Only of Technology, Sweden
Based on lectures
at Chalmers
University
0
10
RSFQ power supply
DC power: increase in speed gives increase in static power dissipation
DC power
Rbias > 5 Rshunt
Vbias ≈ 5 mV (1.5 µm 2.6 mV)
Rbias
Rshunt
3 µm
DC power
Pstatic ≈ 0.5 mW/JJ
90 mA
Bias resistor
Superconducting shield (SuShi)
10x power dissipated in bias resistors than in Josephson junctions
Gates are biased in parallel: power network is a large current divider
14
High stray magnetic field
Superconducting shield
Nonuniform ground currents
Multiple bias lines
High heat load
Current recycling
Biasing 10,000 JJs requires 1 A of current
Unclassified
// For Offical
Use Only of Technology, Sweden
Based on lectures
at Chalmers
University
RSFQ timing
5
Clock period
0
Clock
-5
”1”
”1”
-10
setup time
hold time
-20
”1”
Data output
-25
-30
0
jitter
9σ
σ
State 1
-15
Data input
jitter
State 0
DC bias current
determines slope of
washboard
2
4
6
8
10
12
14
16
18
20
delay
DC power
•
•
•
•
thermal noise and fab spread related jitter
timings depend on state
timings depend on speed
timings depend on the state of the
neighboring cells
Clock
J3
J2
Data
J0
J1
Local clocks accumulate thermal noise and data dependent skews
Unclassified
// For Offical
Use Only of Technology, Sweden
Based on lectures
at Chalmers
University
Data
Data dependent timing parameters
• Extra junctions for separation of a clock like from the gates
• Extra junctions for adjustments of the delays between gates
• 80 % overhead in Josephson junctions for clock distribution
• 1 A of bias currents
• accumulated jitter
Unclassified
// For Offical
Use Only of Technology, Sweden
Based on lectures
at Chalmers
University
Large parallel circuits requires active
synchronization
1000 junctions in clock lines
9σ ≈ 1.5 ps Tclock = 50 ps
Clock
+
+
+
+
+
clock
+
+
+
+
+
carry
clock
carry
+
sum
sum
+
+
+
+
+
carry
clock
sum
FIFO
+
+
+
carry
clock
+
FIFO
+
+
+
∆T
sum
+
+
FIFO
clock
Clock skew
+
+
+
+
• Active synchronization adds even more junctions
• Global reset is needed to recover state of FIFOs
Unclassified
// For Offical
Use Only of Technology, Sweden
Based on lectures
at Chalmers
University
FIFO
FIFO
FIFO
+
+
+
Reciprocal Quantum
Logic: RQL
•
•
•
•
•
•
Zero static power dissipation
Serial bias
Stable timing
Many logic level per pipe-line
Low JJ count
Combinational logic similar to CMOS
Unclassified // For Offical Use Only
Removing Resistors Eliminates Power Dissipation
RSFQ
RQL
Power
AC power
DC power
Signal
A
A
L
IC
1
1
RQL Four-phase AC Clock Creates Directionality
1
3
Clock I
2
4
Clock Q
Negative
Positive
Ф0 = 2 mV٠ps = 2 mA٠pH
19
Unclassified // For Offical Use Only
0
RQL Logic Gate Schematics are
Simple Like CMOS
A
B
A
A
OR
B
A
AND
B
OR
B
AND
CLK
MVTL
CMOS
RSFQ
RQL
Power/Clock
CLK
A
OR
AND
B
A
OR
A
First input goes to
OR. Second input
goes to AND
B
B
AND
Critical current margins > 50%
20
Unclassified // For Offical Use Only
RQL Carry Look-Ahead Adder has been designed
using CMOS-like logic synthesis
Adder logic:
•
•
•
•
•
1647 total JJs
8 bits
1.25 clock latency
50 logic gates, 240 JTLs
800 Josephson junctions
< 1 µW power
Output amplifiers:
•
•
Distributed output amplifiers
2 mV up to 10 GHz
Power splitters:
•
•
•
8 way Wilkinson splitters
2-12 GHz clock rate
Bias current 2 mA/per line
5 mm
21
Unclassified // For Offical Use Only
Hypres 4500 process
RQL is low power and scalable
RSFQ JTL
RQL CLA
2.6 mV
0.200 mA
=
=
RQL pulse: 0.3 ICФ0f = 0.3 nW for 0.1 mA junction at 6 GHz
AC power: 6 mW for 15 mA on a 50 Ohm line
500 nW
Factor of
20,000,000
RQL is 10x better than CMOS in 300W
Power
Gates
Clock frequency
Computational power
CMOS 45 nm
300 W
90M/chip
1 GHz
1017 gates/s
50M/MCM
20 GHz
1018 gates/s
RQL 1 µm (0.1mA)
50 mW (300 W wall plug)
22
Unclassified // For Offical Use Only
Conclusion
SFQ logic is fast and with small signal power
300 GHz interconnects
Quantum accurate bits
SFQ logic
Digital ”1”
V
r
B
Φ0
0.5 mV
E = 2 10-19 J
Js
0.5 ps
t
High maturity level: applications, fabrication, packaging, design
RQL
500 nW
1600 devices
2.5 µW at 12 GHz
Reversible logic provides path to lower power dissipation
Unclassified
// For Offical
Use Only of Technology, Sweden
Based on lectures
at Chalmers
University