Download Homework 2 - UTK-EECS

ECE 533
Homework 1
1. Draw the schematic of the circuit the layout in Figure 2 represents.
VDD
pMOS
nMOS
E
D
B
A
C
GND
Figure 1.
2. Estimate all the junction areas and perimeters at the labeled nodes of the circuit in Figure
2. Assume that all the p-channel transistors have sizes of 10 m/0.5 m and all the nchannels have sizes of 4 m/0.5 m.
VDD
a
d
1
b
c
2
b
Out
a
3
c
4
d
Figure 2
3. Sketch the layout for the circuit in Figure 2 using  design rules.
Due 02.01.17
Homework 2
3.1, 3.6, 3.10, 3.11, 3.15
Due 02.10.17
Homework 3
5.4, 5.5, 5.7, 5.8
Due 02.20.17
Homework 4
7.1a, 7.5, 7.7, 7.10, 7.11
Due 02.27.17
Homework 5
1. Design an exclusive-nor (X-NOR) circuit using CMOS transmission gates.
2. The CMOS transmission gate shown has an input voltage of 1.5 V when it turns off. The
W/L of the n-channel is 4 m/0.6 m and the W/L of the p-channel is 8 m/0.6 m.
Estimate the change in output voltage due to clock feedthrough. You may assume the total
parasitic capacitance between the output node and ground is 50 fF, that VDD = 3.3 V, and
that the clock signal changes very fast. Ignore the changes due to overlap capacitance.
Assume, VTN0 = 1.1 V, VTP0 = -1.2 V, Cox = 3.4fF/m2.
clock
Vout
Vin
50 fF
clock
3. Design a fully differential CMOS gate with cross-coupled loads that realizes the
function: 𝑜𝑢𝑡 = 𝑥1 + ̅̅̅
𝑥2 . Give reasonable device size assuming Lmin = 0.5 m.
4. Realize a two input AND gate using differential logic and/or transmission gate logic.
Due 03.31.17