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Baker Ch. 3 The Metal Layers Introduction to VLSI Chapter 3 – The Metal Layers • • • • • Bond Pad Design and Layout Parasitics DRC Cross Talk, Ground Bounce Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor 1 Baker Ch. 3 The Metal Layers Bond Pad Introduction to VLSI DESCRIPTION – – INTERFACE: CHIP TO WORLD ESD PROTECTION • • – NECESSARY MORE DETAILS LATER SIZE DEPENDS ON USAGE • BOND PAD – • ETEST PAD – • SIZE SET BY MICRO-TIP LOCATION • BOND PAD – • • TOP METAL LAYER ETEST PAD – ALL ROUTING LAYERS MICRO PAD – – SIZE SET BY PROBE CARD MICRO PAD – – SIZE SET BY WIRE PROCESS ANY ROUTING LAYER PASSIVATION • • MUST REMOVE TO PROBE PAD.DG LAYER USED FOR MASK Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor 2 Baker Ch. 3 The Metal Layers Design and Layout Introduction to VLSI DESCRIPTION – CONNECTIVITY • – METAL1 VIA1 METAL2 RULES • VIA1 MUST BE ENCLOSED BY – – • – VIA1 IS ONE FIXED W/L CONNECTIVITY • • • – METAL1 METAL2 METAL1 VIA1 METAL2 NWELL IS NOT CONNECTED HOW TO CONNECT TO NWELL? CAN / SHOULD HAVE MANY VIAS • HOW MANY VIAS IN A DESIGN? Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor 3 Baker Ch. 3 The Metal Layers Parasitics DESCRIPTION – SEPARATE DEVICE FROM OTHER • • METAL SHEET RHO • • – WHAT ARE UNITS OF SHEET RHO? HOW IS SHEET RHO FOUND? VIA RESISTANCE • NO SHEET RHO, WHY? CAPACITANCE – METAL1 OVER SUBSTRATE • • – WHAT DEVICES ARE HERE? WHAT “OTHER” IS HERE? RESISTANCE – Introduction to VLSI WHERE ARE TERMINALS? DISTRIBUTED CAP LUMPED METAL2 OVER METAL 1 DISTRIBUTIONS – RESISTANCES, CAPS DO NOT HAVE ONE VALUE ONLY Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor 4 Baker Ch. 3 The Metal Layers ELECTOMIGRATION, DRC DESCRIPTION – ELECTROMIGRATION • • • 0.6um 0.7um 0.225um 0.35um 0.8um 0.6um Introduction to VLSI – DRC RULES • • – LIMITS Imax DUE TO BAMBOO FORMATION SEPARATION, FAILURE BOOK VALUES ARE NOT TYPICAL NEED DESIGN RULE PRIMER TERMINOLOGY • • • • ENCLOSURE SPACING WIDTH OVERLAP 1.0um KEY PHRASE, THESE ARE NOT THE RULES THAT YOU USE Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor 5 Baker Ch. 3 The Metal Layers Cross Talk, Ground Bounce Introduction to VLSI DESCRIPTION – CONDUCTORS INTERACT • – CROSS TALK • • – AC, DC SIGNALS V=IR • • • • – AC SIGNALS Imutual=Cmutual dVsignal/dt GROUND BOUNCE • – EM FIELD OVERLAP, V INDUCED CAUSE AND EFFECT V IS FROM POWER SUPPLY I IS FROM V/R R IS FIXED, BASED ON ROUTING DECOUPLING CAP • • STORES VDD CHARGE TRANSIENT CURRENT Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling Principal, Cypress Semiconductor 6
