Download 68 The average horizontal electric field across the channel in pinch

The average horizontal electric field across the
channel in pinch-off does not depend on the D-S
voltage but instead on the voltage across the
channel, which is VGS - Vt .
ID = μ n Cox W ⎡ 2( VGS −Vt )VDS −VDS2 ⎤
⎥⎦
2 L ⎢⎣
is not
′
= k W ⎡ 2( VGS −Vt )VDS −VDS2 ⎤
⎥⎦
2 L ⎢⎣
valid if VDS > VGS - Vt .
In the pinch-off region where VDS = VGS - Vt ,
ID = k′ W ⎡⎢ 2( VGS −Vt )( VGS −Vt )−( VGS −Vt ) ⎤⎥
2 L⎣
⎦
2
= k′ W ( VGS − Vt )
(1.157)
2 L
2
Hence, ID is independent of VDS in the pinch-off
region. In practice, however, ID in the pinch-off
region varies slightly as the drain voltage is
varied. This effect is due to the presence of a
depletion region between the physical pinch-off
point in the channel at the D end and the region
itself.
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Output characteristic
of NMOS
ID
Saturation/active
region
ΔID
ΔVDS
triode region
VDS
cut-off region
VDS
VGS
S
G
D
+ ++ + + ++ + +
n+
n+
Leff
depletion region
Xd
p-substrate (body)
Xd = depletion layer width between physical
pinch-off point in the channel at the D-end and
the D region itself.
Leff = L - Xd = effective channel length
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(1.158)
2
′
k
W
ID =
(V −V )
2 Leff GS t
(1.159)
Because Xd (and thus Leff) are functions of VDS
in the pinch-off region, ID varies with VDS. This
effect is called the channel-length modulation.
∂ID = − k′ W V − V 2 dLeff
(
)
2 Leff 2 GS t dVDS
∂VDS
∂ID = − ID dLeff
Leff dVDS
∂VDS
From (1.158), i.e. Leff = L - Xd,
dLeff = −1
dXd
dLeff = −dXd
∂ID = − ID ⎡⎢− dXd ⎤⎥ = ID ⎡⎢ dXd ⎤⎥
Leff ⎢⎢⎣ dVDS ⎥⎥⎦ Leff ⎢⎢⎣ dVDS ⎥⎥⎦
∂VDS
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ID
Slope =
∂ID
∂VDS
ΔVDS
VA
ΔID
VDS
dX
VA = − ID = IDLeff = Leff
dV
∂ID
dX D
ID
∂VDS
dVDS
⎛
⎜
⎜
⎜
⎝
⎞
D ⎟⎟
DS ⎟⎠
−1
(1.163)
For MOSFETs, a commonly used parameter for
the characterization of channel length
modulation is:
(1.164)
λ= 1
VA
The large-signal properties of the transistor can
be approximated by assuming that λ and VA are
constants independent of the bias conditions. If
the channel-length modulation effect is included,
2 ⎛⎜ VDS ⎞⎟
′
k
W
ID =
VGS − Vt ) ⎜1+
(
⎟
⎜
2 L
V
A ⎟⎠
⎝
2
= k′ W ( VGS − Vt ) ⎛⎜⎝1+ λVDS ⎞⎟⎠
2 L
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From
(1.163),
i.e.
VA = Leff
⎛
⎜
⎜
⎜
⎝
dX
dV
⎞
D ⎟⎟
DS ⎟⎠
−1
and
(1.164), i.e. λ = − 1 , λ∝− 1 . Typical λ is in
VA
Leff
the range 0.05 V-1 to 0.005 V-1.
Output characteristic
of NMOS
ID
VDS = VGS − Vt
Saturation/active/
pinch-off region
triode region VDS = VGS − VtΔID
VGS increases
VDS
cut-off region
VDS > VGS - Vt → pinch off / saturation region.
In saturation region, output characteristics are
almost flat. ID depends mostly on VGS and only
to a small extent on VDS.
If VDS < VGS - Vt , the device operates in the
ohmic or triode region where the device can be
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modeled as a non-linear voltage controlled
resistor connected between D and S.
In this region,
ID = k′ W ⎡⎢2 ( VGS − Vt ) VDS − VDS2 ⎤⎥
⎦
2 L⎣
(1.152)
The resistance in this region is non-linear
because VDS2 term in (1.152), causes the
resistance to depend on VDS. Since this term is
small when VDS is small, the non-linearity is
also small:
Triode region is also sometimes called the linear
region.
The boundary between the triode and the
saturation region occurs when VDS = (VGS - Vt).
On this boundary, both (1.152) and (1.157), i.e.
2
ID = k′ W ( VGS − Vt ) , correctly predict ID.
2 L
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Large-signal model for NMOS:
G
D
+
VGS
ID
−
Ri
S
In triode region:
ID = k′ W ⎡⎢2 ( VGS − Vt ) VDS − VDS2 ⎤⎥
⎦
2 L⎣
In saturation region:
ID = k′ W ( VGS − Vt )
2 L
2
In saturation region with channel-modulation
effect included:
2
ID = k′ W ( VGS − Vt )
2 Leff
2
= k′ W ( VGS − Vt ) ⎛⎜⎝1+ λVDS ⎞⎟⎠
2 L
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1.6 Small-signal model of MOSFET
Id = ID + id
vi +
VDD
−
VGS
Saturation/active mode of operation:
VGS > Vt
VDS > (VGS - Vt)
VGS and VDD are the bias voltages, producing ID.
vi is the small-signal input voltage producing id.
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1.6.1 Transconductance
ID = k′ W ( VGS − Vt ) ⎛⎜⎝1+ λVDS ⎞⎟⎠
2 L
gm = ∂ID = k′ W 2( VGS − Vt ) ⎛⎜⎝1+ λVDS ⎞⎟⎠
∂VGS 2 L
gm = k′ W ( VGS − Vt ) ⎛⎜⎝1+ λVDS ⎞⎟⎠
L
2
If λVDS << 1, then
ID
V
−
V
=
( GS t ) k′ W
2 L
gm = k′ W ( VGS − Vt )
L
=
k′2 ⎛⎜ W ⎞⎟
⎝ L ⎠
2
ID
k′ W
2 L
= 2k′ W ID
L
gm = k′ W ( VGS − Vt )
L
2
ID = k′ W ( VGS − Vt )
2 L
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gm = k′ W ( VGS − Vt )
L
2
ID = k′ W ( VGS − Vt )
2 L
VOV = VGS − Vt
W V
′
k
g m = L ( OV ) = 2
2 VOV
ID k ′ W V
(
)
2 L OV
VOV ≈ several hundred mV.
For the BJT:
Vt = 26 mV
Hence, g m <
ID
g m = IC
Vt
gm = 1
IC Vt
gm
IC
One of the key challenges in MOS analog circuit
design is designing high-quality analog circuits
with a low transconductance-to-current ratio.
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Id = ID + id
vi +
VDD
−
VGS
ID = k′ W ( VGS − Vt )
2 L
2
Id = k′ W ( VGS + vi − Vt )
2 L
⎛
⎞
2
′
k
W
2
⎜
=
V − Vt ) + 2( VGS − Vt ) vi + vi ⎟⎟
⎜⎜ ( GS
⎟
2 L⎝
⎠
= ID + k′ W ⎛⎜ 2( VGS − Vt ) vi + vi2 ⎞⎟
⎠
2 L⎝
id = Id − ID = k′ W ⎛⎜ 2( VGS − Vt ) vi + vi2 ⎞⎟
⎠
2 L⎝
⎛
⎞
W
V
V
v
−
v
(
)
t
⎜
⎟
GS
i
i
= k′
⎜ 1+
⎟
L
2
V
V
−
⎜
(
)
t ⎟⎠
GS
⎝
gm = k′ W ( VGS − Vt )
L
⎛
⎞
v
⎜
⎟
i
id = gmvi ⎜1+
⎟
⎜
⎟
−
2
V
V
(
)
t
GS
⎝
⎠
2
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⎛
⎜
i ⎜⎜1
⎝
vi
⎞
⎟
⎟
⎟
⎠
id = gmv +
2( VGS −Vt )
If vi << VGS − Vt, then id ≈ gmvi
gm = k′ W ( VGS − Vt ) can be used for smallL
signal analysis if vi << VOV .
1.6.2 Intrinsic Gate-Source and GateDrain Capacitance
G
n+
−−−−−−−−−
n+
W
p
L
Cox = oxide capacitance per unit area from G to
channel
Hence, total capacitance under the G is CoxWL.
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G
n+
−−−−−−−−−
n+
W
p
L
In the triode region of device operation, the
channel exists continuously from S to D. The Gchannel capacitance is usually lumped into two
equal parts at the D and S,
Cgs = Cgd = (1/2)CoxWL
In the saturation or active region, the channel
pinches off before reaching the D. The D voltage
has little influence on either the channel or the G
charge.
Cgd = 0
Cgs = (2/3)CoxWL
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1.6.3 Input resistance
G
n+
−−−−−−−−−
n+
W
p
L
G is insulated from the channel by the SiO2. At
low-frequencies, G current is essentially 0 and
input resistance is essentially ∞.
1.6.4 Output resistance
Output characteristic
of NMOS
ID
VDS = VGS − Vt
Saturation/active/
pinch-off region
triode region
VDS
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pinch-off
Output characteristic
of NMOS
VDS = VGS − Vt
ID
Saturation/active/
pinch-off region
triode region
pinch-off
VDS
VDS
VGS
S
G
D
+ ++ + + ++ + +
n+
n+
Leff
depletion region
Xd
p-substrate (body)
Increasing VDS will increase the width of the
depletion region around the D and reduces the
effective channel length of the device in the
saturation or active region. This effect is the
channel length modulation and causes ID to
increase when VDS is increased.
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VDS
VGS
S
G
D
+ ++ + + ++ + +
n+
n+
Leff
Xd
L
ΔID = ∂ID ΔVDS
∂VDS
ΔID = change in the D current
ΔVDS = change in the D-S voltage
Leff = L - Xd
∂ID = ID ⎡⎢ dXd ⎤⎥
∂VDS Leff ⎢⎣⎢ dVDS ⎥⎦⎥
−1
dXD ⎞⎟
VA = Leff
dVDS ⎟⎟⎠
Hence, ∂ID = ID
∂VDS VA
λ = 1 where VA is the Early voltage.
VA
ΔID = ∂ID = ID = λI = 1
D r
ΔVDS ∂VDS VA
o
⎛
⎜
⎜
⎜
⎝
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ΔID = ∂ID = ID = λI = 1
D r
ΔVDS ∂VDS VA
o
where:
λ = channel length modulation parameter
ro = small-signal output resistance of the
transistor
ID = drain current without channel length
modulation
2
= k′ W ( VGS − Vt )
2 L
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