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High Speed Digital Input Buffer Circuits
Krishna Duvvada, Vishal Saxena and R. Jacob Baker
ECE Dept., Boise State University, [email protected]
Abstract—This paper illustrates design, fabrication and testing of
novel differential high-speed digital input buffers. The delay of
the proposed input buffers are nearly independent of power
supply voltage and input signal amplitudes. The pulse shape of
the output signal is highly symmetric which mitigates skew
related errors.
Keywords- CMOS, Differential Amplifier, Digital design, Highfrequency Input Buffer.
I.
INTRODUCTION
nput buffer circuits are present at a chip’s input and convert
input signals with imperfections such as slow rise and fall
times into clean, full logic level digital signals for use inside
the chip. If the buffer doesn’t slice the data at the correct time
instants, timing errors can occur. If the input signal is sliced too
high or too low, the output signal’s width is incorrect. In the
high speed systems this reduces the timing budget in the
systems and can result in errors [1]. This paper presents design,
fabrication and test results of novel, differential high-speed
input buffers which mitigate these problems.
I
II.
Ideally, the delay of the buffer should be independent of
power supply voltage, temperature, input signal amplitudes or
pulse shape. In order to obtain better performance for lower
input level signals, a PMOS version of input buffer (fig.2) can
be used. However this scheme leads to the appearance of a
large offset. To avoid the offset, the NMOS buffer can be used
in parallel with a PMOS buffer as shown in fig.3, to form an
input buffer that operates well with input signals approaching
ground or VDD. The topology with the buffers in parallel
provides a robust input buffer that works for a wide range of
input voltages [1].
VDD
M6PT
M6PB
40/2
VDD
Vinp
M3P
M4P
M1P
Vs
Vinp
Vinm
80/2
VDD
M6PT
40/2
Vs
M6PB
40/2
Vinp
VDD
M3P
M4P
M2P
VDD
VDD
Vinm
160/2
Vout
M7
80/2
Unlabeled NMOS are 10/2
Unlabeled PMOS are 20/2
M4
M1
M2
20/2
Vs
Vs
M7P
Figure 2. PMOS input buffer
M3
Vout
Vout
Unlabeled NMOS are 10/2
Unlabeled PMOS are 20/2
VDD
Vom
160/2
Vom
M5P
M1P
Vs
VDD
Vinm
M2P
DIFFERENTIAL INPUT BUFFER CIRCUITS
In order to precisely ‘slice’ the input data, the data is
transmitted differentially as an input and its complement. A
differential amplifier input buffer amplifies the different
between the two inputs. The buffer topologies used in this
design employ self biased differential amplifiers as no external
reference is used to set the bias current in the diff-amp [1],[2].
Fig.1 shows an NMOS version of input buffer. When the input
falls belowVTHN , then the circuit will not work very quickly as
the NMOS are moved into subthreshold region. This will result
in an increase in the delay [1].
Vs
40/2
Vinp
Vinm
Vs
buffer
Vout
Schematic symbol
M5T
20/2
M5B
Figure 3. Rail-to-rail input buffer combining NMOS and PMOS buffers
Figure 1. NMOS input buffer
The input buffers are designed with ‘enable’ logic using the
NMOS and PMOS switches, like M5B and M6 in fig.1,
Delay vs Vref
controlled by signals Vs and Vs . When the enable signals are
off, the output of the diff-amp will be in high impedance state.
This can cause a large amount of current to flow in the
inverters and damage the chip. To avoid this scenario, a switch
M7 is connected to the output of the diff-amp which clips the
node to ground when the buffer is disabled.
The buffers are fabricated in AMI’s CN5 (0.5µm) process
with a VDD of 5V as shown in fig. 4. The buffers are designed
to drive a load of 30pF which accounts for the load offered by
the probe setup. A large inverter (160/80) is used to drive the
large load with optimal delay.
15
NMOS
PMOS
Parallel
14
Delay (ns)
13
12
11
10
9
1.5
2
2.5
3
3.5
4
Vref (V)
Figure 7. Delay vs common mode reference (Vref) plot for the input buffers.
Delay vs Vp
12.5
NMOS
PMOS
Parallel
Delay (ns)
12
11.5
11
10.5
10
0.8
1
1.2
1.4
1.6
Vp (V)
1.8
2
2.2
2.4
2.6
Figure 8. Delay vs input signal swing (Vp) plot for the input buffers.
Figure 4. Micrograph showing the input buffer circuits fabricated on a chip.
Delay vs Temperature
18
NMOS
PMOS
Parallel
17.5
III. TEST RESULTS
The input buffers were tested using the setup shown in
fig.5. The common mode reference voltage Vref was nominally
kept at 2.5V and the input differential signal v p (clock pulses
with 1MHz frequency) was applied at the positive terminal of
the buffer. The net delay was measured as the sum of charging
and discharging delays (i.e. t pLH + t pHL ). Figs.6-9 show the net
delay offered by the input buffers for varying supply voltage,
common mode reference voltage, input signal swing and
temperature respectively.
Vinp
Vinm
vp
Vref
Vout
Delay (ns)
15
14.5
Figure 9.
0
20
40
Delay vs VDD
NMOS
PMOS
Parallel
13
12.5
60
Temperature (C)
80
100
120
Simulated delay vs temperature plot for the input buffers.
The test results demonstrate that the designed input buffers
operate well for high-speed input signals. The delay is virtually
independent of power supply voltage, input common mode
reference and voltage swing. The output pulse is highly
symmetric and skew is absent. The parallel buffer topology
provides the optimal performance for wide range of input
voltages.
CONCLUSION
A set of differential high-speed input buffers have been
designed, fabricated and tested. The designed input buffers
provide high frequency operation with lower delays. The
delays are nearly independent of variations in power supply,
input signal common mode and differential voltages, and
temperature.
13.5
12
REFERENCES
11.5
11
[1]
10.5
10
9.5
3.5
16
15.5
IV.
Vref
Figure 5. Test setup for the input buffers
Delay (ns)
17
16.5
[2]
4
4.5
VDD (V)
5
5.5
Figure 6. Delay vs supply voltage (VDD) plot for the input buffers.
R. J. Baker, CMOS: Circuit Design, Layout and Simulation, 2nd ed.
Boise, ID: Wiley-IEEE, 2005, pp. 531-538
M. Bazes, “Two Novel Fully Complementary Self-Biased CMOS
Differential Amplifiers,” IEEE Journal of Solid State Circuits, vol. 26,
no. 2, Feb. 1991.