Download LTC5584 - 30MHz to 1.4GHz IQ Demodulator with IIP2 and DC

LTC5584
30MHz to 1.4GHz IQ
Demodulator with IIP2 and
DC Offset Control
Description
Features
I/Q Bandwidth of 530MHz or Higher
n High IIP3: 31dBm at 450MHz, 28dBm at 900MHz
n High IIP2: 70dBm at 450MHz, 65dBm at 900MHz
n User Adjustable IIP2 to >80dBm
n User Adjustable DC Offset Null
n High Input P1dB: 13.1dBm at 900MHz
n Image Rejection: 45dB at 900MHz
n Noise Figure: 9.9dB at 450MHz
10dB at 900MHz
n Conversion Gain: 5.4dB at 450MHz
5.7dB at 900MHz
n Shutdown Mode
n Operating Temperature Range (T ): –40°C to 105°C
C
n 24-Lead 4mm × 4mm QFN Package
The LTC®5584 is a direct conversion quadrature demodulator optimized for high linearity receiver applications in
the 30MHz to 1.4GHz frequency range. It is also usable
in the 10MHz to 30MHz and 1.4GHz to 2GHz ranges with
reduced performance. It is suitable for communications
receivers where an RF signal is directly converted into I
and Q baseband signals with bandwidth of 530MHz or
higher. The LTC5584 incorporates balanced I and Q mixers, LO buffer amplifiers and a precision, high frequency
quadrature phase shifter. In addition, the LTC5584 provides
four analog control voltage interface pins for IIP2 and DC
offset correction, greatly simplifying system calibration.
n
The high linearity of the LTC5584 provides excellent spurfree dynamic range for the receiver. This direct conversion
demodulator can eliminate the need for intermediate frequency (IF) signal processing, as well as the corresponding
requirements for image filtering and IF filtering. These
I/Q outputs can interface directly to channel-select filters
(LPFs) or to baseband amplifiers.
Applications
n
n
n
n
n
LTE/W-CDMA/TD-SCDMA Base Station Receivers
Wideband DPD Receivers
Point-To-Point Broadband Radios
High Linearity Direct Conversion I/Q Receivers
Image Rejection Receivers
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
Direct Conversion Receiver with IIP2 and DC Offset Calibration
5V
LNA
BPF
RF
INPUT
VCC
RF+
I+
LPF
VGA
I–
IIP2 vs IP2I, IP2Q Trim Voltage
A/D
130
RF–
IP2 AND DC
OFFSET CAL
LO INPUT
LO
IP2 ADJUST
120
D/A
100
LTC5584
IP2 AND DC
OFFSET CAL
D/A
DC OFFSET
EN
Q+
Q–
LPF
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
fRF = 450MHz
90
80
70
IP2 ADJUST
D/A
ENABLE
I, –40°C
I, 25°C
I, 85°C
I, 105°C
110
DC OFFSET
0°
90°
D/A
IIP2 (dBm)
BPF
60
50
VGA
A/D
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
IP2I, IP2Q (V)
5584 TA01b
5584 TA01a
5584f
1
LTC5584
Pin Configuration
VCC Supply Voltage.................................... –0.3V to 5.5V
VCAP Voltage..................................................VCC ±0.05V
I–, I+, Q+, Q –, CMI, CMQ Voltage.........2.5V to VCC + 0.3V
Voltage on Any Other Pin..................–0.3V to VCC + 0.3V
LO+, LO –, RF+, RF – Input Power............................20dBm
RF+, RF – Input DC Voltage......................... –0.3V to 2.7V
Maximum Junction Temperature (TJMAX).............. 150°C
Operating Temperature Range (TC)
(Note 3)................................................... –40°C to 105°C
Storage Temperature Range................... –65°C to 150°C
CMI
Q–
Q+
I–
I+
REF
TOP VIEW
24 23 22 21 20 19
IP2Q 1
18 CMQ
DCOQ 2
17 VCAP
DCOI 3
IP2I 4
RF
+
16 LO–
25
GND
15 LO+
5
14 GND
RF– 6
13 GND
EIP2
EDC
9 10 11 12
VCC
8
VBIAS
7
EN
(Note 1)
GND
Absolute Maximum Ratings
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 150°C, θJC = 7°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC5584IUF#PBF
LTC5584IUF#TRPBF
5584
24-Lead (4mm x 4mm) Plastic QFN
–40°C to 105°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Electrical
Characteristics C = 25°C, VCC = 5V, EN = 5V, EDC = EIP2 = 0V, REF = IP2I = IP2Q = DCOI = DCOQ
T
= 0.5V, PRF = –5dBm (–5dBm/tone for 2-tone IIP2 and IIP3 tests), PLO = 6dBm, unless otherwise noted. (Notes 2, 3, 5, 6, 9)
SYMBOL
PARAMETER
CONDITIONS
RF Input Frequency Range
(Note 12)
fRF(RANGE)
LO Input Frequency Range
(Note 12)
fLO(RANGE)
LO Input Power Range
(Note 12)
PLO(RANGE)
fRF1 = 140MHz, fRF2 = 141MHz, fLO = 130MHz, L6 = 68nH, C19 = 8.0pF, L5 = 82nH
RF Input Frequency Range
Return Loss > 10dB
fRF(MATCH)
LO Input Frequency Range
Return Loss > 10dB
fLO(MATCH)
Voltage Conversion Gain
Loaded with 100Ω Pull-Up (Note 8)
GV
NF
Noise Figure
Double-Side Band (Note 4)
Noise Figure Under Blocking Conditions
Double-Side Band, PRF = 0dBm (Note 7)
NFBLOCKING
IIP3
Input 3rd Order Intercept
IIP2
Input 2nd Order Intercept
Unadjusted, EIP2 = 0V
Optimized Input 2nd Order Intercept
EIP2 = 5V, IP2I, IP2Q Adjusted for Minimum IM2
IIP2OPT
P1dB
Input 1dB Compression
DC Offset at I/Q Outputs
Unadjusted, EDC = 0V (Note 13)
DCOFFSET
I/Q Gain Mismatch
∆G
∆φ
I/Q Phase Mismatch
MIN
TYP
30 to 1400
30 to 1400
0 to 10
MAX
UNITS
MHz
MHz
dBm
95 to 190
105 to 180
5.7
9.9
15.5
33
70
80
12
1.5
0.02
MHz
MHz
dB
dB
dB
dBm
dBm
dBm
dBm
mV
dB
0.2
Deg
5584f
2
LTC5584
Electrical
Characteristics C = 25°C, VCC = 5V, EN = 5V, EDC = EIP2 = 0V, REF = IP2I = IP2Q = DCOI = DCOQ
T
= 0.5V, PRF = –5dBm (–5dBm/tone for 2-tone IIP2 and IIP3 tests), PLO = 6dBm, unless otherwise noted. (Notes 2, 3, 5, 6, 9)
SYMBOL
PARAMETER
CONDITIONS
IRR
Image Rejection Ratio
(Note 10)
LO-RF
LO to RF Leakage
RF-LO
RF to LO Isolation
fRF1 = 450MHz, fRF2 = 451MHz, fLO = 440MHz, L6 = 15nH, C19 = 1.0pF, L5 = 12nH, C14 = 4.0pF
RF Input Frequency Range
Return Loss > 10dB
fRF(MATCH)
LO Input Frequency Range
Return Loss > 10dB
fLO(MATCH)
Voltage Conversion Gain
Loaded with 100Ω Pull-Up (Note 8)
GV
NF
Noise Figure
Double-Side Band (Note 4)
Noise Figure Under Blocking Conditions
Double-Side Band, PRF = 0dBm (Note 7)
NFBLOCKING
IIP3
Input 3rd Order Intercept
IIP2
Input 2nd Order Intercept
Unadjusted, EIP2 = 0V
Optimized Input 2nd Order Intercept
EIP2 = 5V, IP2I, IP2Q Adjusted for Minimum IM2
IIP2OPT
P1dB
Input 1dB Compression
DC Offset at I/Q Outputs
Unadjusted, EDC = 0V (Note 13)
DCOFFSET
I/Q Gain Mismatch
∆G
MIN
I/Q Phase Mismatch
∆φ
IRR
Image Rejection Ratio
(Note 10)
LO-RF
LO to RF Leakage
RF-LO
RF to LO Isolation
fRF1 = 900MHz, fRF2 = 901MHz, fLO = 940MHz, C17 = 1.5pF, L6 = 5.6nH, C13 = 2.2pF, L5 = 3.9nH
RF Input Frequency Range
Return Loss > 10dB
fRF(MATCH)
LO Input Frequency Range
Return Loss > 10dB
fLO(MATCH)
Voltage Conversion Gain
Loaded with 100Ω Pull-Up (Note 8)
GV
NF
Noise Figure
Double-Side Band (Note 4)
Noise Figure Under Blocking Conditions
Double-Side Band, PRF = 0dBm (Note 7)
NFBLOCKING
IIP3
Input 3rd Order Intercept
IIP2
Input 2nd Order Intercept
Unadjusted, EIP2 = 0V
Optimized Input 2nd Order Intercept
EIP2 = 5V, IP2I, IP2Q Adjusted for Minimum IM2
IIP2OPT
P1dB
Input 1dB Compression
DC Offset at I/Q Outputs
Unadjusted, EDC = 0V (Note 13)
DCOFFSET
I/Q Gain Mismatch
∆G
I/Q Phase Mismatch
∆φ
IRR
Image Rejection Ratio
LO-RF
LO to RF Leakage
RF-LO
RF to LO Isolation
Power Supply and Other Parameters
Supply Voltage
VCC
Supply Current
ICC
Supply Current
ICC(LOW)
Shutdown Current
ICC(OFF)
Turn-On Time
tON
Turn-Off Time
tOFF
EN, EDC, EIP2 Input High Voltage (On)
VEH
EN, EDC, EIP2 Input Low Voltage (Off)
VEL
(Note 10)
EDC = EIP2 = VCC
EDC = EIP2 = 0V
EN < 0.3V
EN Transition from Logic Low to High (Note 14)
EN Transition from Logic High to Low (Note 15)
4.75
180
174
TYP
53
–85
74
MAX
UNITS
dB
dBm
dB
300 to 600
310 to 590
5.4
9.9
13.6
31
70
80
12.6
2
0.02
MHz
MHz
dB
dB
dB
dBm
dBm
dBm
dBm
mV
dB
0.25
Deg
52
–80
70
dB
dBm
dB
630 to 1200
470 to 1100
5.7
10
14.7
28
65
80
13.1
2.5
0.01
MHz
MHz
dB
dB
dB
dBm
dBm
dBm
dBm
mV
dB
0.7
Deg
45
–75
65
dB
dBm
dB
5.0
200
194
11
0.2
0.8
5.25
220
214
900
2.0
0.3
V
mA
mA
μA
µs
µs
V
V
5584f
3
LTC5584
Electrical
Characteristics C = 25°C, VCC = 5V, EN = 5V, EDC = EIP2 = 0V, REF = IP2I = IP2Q = DCOI = DCOQ
T
= 0.5V, PRF = –5dBm (–5dBm/tone for 2-tone IIP2 and IIP3 tests), PLO = 6dBm, unless otherwise noted. (Notes 2, 3, 5, 6, 9)
SYMBOL
IENH
IEDCH
IEIP2H
VREF
VREF(RANGE)
ZREF
VCM
ZOUT
BWBB
PARAMETER
EN Pin Input Current
EDC Pin Input Current
EIP2 Pin Input Current
REF Pin Voltage
REF Pin Voltage Range
REF Input Impedance
DCOI, DCOQ, IP2I, IP2Q Pin Voltage
DCOI, DCOQ, IP2I, IP2Q Voltage Range
DCOI, DCOQ, IP2I, IP2Q Impedance
DCOI, DCOQ, IP2I, IP2Q Settling Time
DC Offset Adjustment Range
CONDITIONS
EN = 5.0V
EDC = 5.0V
EIP2 = 5.0V
With REF Pin Unloaded
When Driven with External Source
(Note 11)
Unloaded
When Driven with External Source
(Note 11)
For Step Input, Output with 90% of Final Value
DCOI, DCOQ Swept from 0V to 1V, EDC = 5V
DC Offset Drift Over Temperature
I+, I–, Q+, Q– Common Mode Voltage
I+, I–, Q+, Q– Output Impedance
I+, I–, Q+, Q– Output Bandwidth
Unadjusted, EDC = 0V
Single Ended
100Ω External Pull-Up, –3dB Corner Frequency
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Tests are performed with the test circuit of Figure 1.
Note 3: The LTC5584 is guaranteed to be functional over the –40°C to
105°C case temperature operating range.
Note 4: DSB noise figure is measured at the baseband frequency of 15MHz
with a small-signal noise source without any filtering on the RF input and
no other RF signal applied.
Note 5: Performance at the RF frequencies listed is measured with external
RF and LO impedance matching, as shown in the table of Figure 1.
Note 6: The complementary outputs (I+, I– and Q+, Q–) are combined
using a 180° phase-shift combiner.
Note 7: Noise figure under blocking conditions (NFBLOCKING) is measured
at an output noise frequency of 60MHz with an RF input blocking signal at
fLO + 1MHz. Both RF and LO input signals are appropriately filtered, as well
as the baseband output. NFBLOCKING measured at fLO of 160MHz, 460MHz
and 885MHz.
MIN
TYP
52
33
50
0.5
0.4 to 0.7
2||1
0.5
0 to 2VREF
8||1
20
±20
20
VCC – 1.5
100||6
530
MAX
UNITS
μA
μA
μA
V
V
kΩ||pF
V
V
kΩ||pF
ns
mV
μV/°C
V
Ω||pF
MHz
Note 8: Voltage conversion gain is calculated from the average measured
power conversion gain of the I and Q outputs using the test circuit shown
in Figure 1. Power conversion gain is measured with a 100Ω differential
load impedance on the I and Q outputs.
Note 9: Baseband outputs have a 100Ω external pull-up resistor to VCC as
shown in the test circuit shown in Figure 1.
Note 10: Image rejection is calculated from the measured gain error and
phase error using the method listed in the appendix.
Note 11: The DCOI, DCOQ, IP2I, IP2Q pins have an 8k internal resistor to
ground. The REF pin has a 2k internal resistor to ground. If unconnected,
these pins will float up to 500mV through internal current sources. A low
output resistance voltage source is recommended for driving these pins.
Note 12: This is the recommended operating range, operation outside the
listed range is possible with degraded performance to some parameters.
Note 13: DC offset measured differentially between I+ and I– and between
Q+ and Q–. The reported value is the mean of the absolute values of the
characterization data distribution.
Note 14: Baseband amplitude is within 10% of final value.
Note 15: Baseband amplitude is at least 30dB down from its on state.
5584f
4
LTC5584
DC Performance Characteristics EN = 5V, EDC = 0V and EIP2 = 0V. Test circuit shown in Figure 1
Supply Current vs Supply Voltage
260
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
250
240
230
540
220
210
200
190
535
530
525
520
515
180
510
170
505
160
4.75
VCC = 4.75V
VCC = 5V
VCC = 5.25V
545
REF VOLTAGE (mV)
SUPPLY CURRENT (mA)
REF Voltage vs Temperature
550
500
–40
5.25
5
SUPPLY VOLTAGE (V)
–20
40
20
0
60
TEMPERATURE (°C)
80
100
5584 G02
5585 G01
Typical Performance Characteristics
140MHz application. VCC = 5V, EN = 5V, EDC = 0V,
EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 130MHz, fRF1 = 140MHz, fRF2 = 141MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm,
DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted.
Test circuit with RF and LO ports impedance matched as in Figure 1.
IIP3 and P1dB vs Supply Voltage
(VCC)
IIP3 and P1dB vs Temperature (TC)
IIP3, P1dB (dBm)
40
I, –40°C
I, 25°C
I, 85°C
I, 105°C
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
45
30
25
20
TC = 25°C
45
35
30
25
100
120
140
160
180
200
LO FREQUENCY (MHz)
10
80
TC = 25°C
35
30
25
15
P1dB
100
120
140
160
180
200
LO FREQUENCY (MHz)
5584 G03
Q, 0dBm
Q, 6dBm
Q, 10dBm
20
15
P1dB
I, 0dBm
I, 6dBm
I, 10dBm
40
IIP3
20
15
10
80
Q, 4.75V
Q, 5.0V
Q, 5.25V
40
IIP3
35
I, 4.75V
I, 5.0V
I, 5.25V
IIP3 vs LO Power
50
IIP3 (dBm)
45
50
IIP3, P1dB (dBm)
50
10
80
100
120
140
160
180
200
LO FREQUENCY (MHz)
5584 G04
5584 G05
5584f
5
LTC5584
Typical
Performance Characteristics
140MHz application. VCC = 5V, EN = 5V, EDC = 0V,
EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 130MHz, fRF1 = 140MHz, fRF2 = 141MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm,
DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted.
Test circuit with RF and LO ports impedance matched as in Figure 1.
2-Tone IIP3 vs RF Power
TC = 25°C
fRF1 = 140MHz
fRF2 = 141MHz
fLO = 130MHz
45
130
Q
I
IIP2 (dBm)
IIP3 (dBm)
35
30
25
–8
–6
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
–2
–4
0
RF POWER (dBm)
2
90
120
70
70
80
100
160
140
120
LO FREQUENCY (MHz)
60
200
180
110
fRF = 140MHz
EIP2 = 5V
TC = 25°C
fRF1 = 140MHz
fLO = 130MHz
100
110
I (UNCALIBRATED)
I (NULLED AT 1MHz)
Q (UNCALIBRATED)
Q (NULLED AT 1MHz)
180
200
Q
I
TC = 25°C
fLO = 140MHz
100
90
IIP2 (dBm)
80
160
140
120
LO FREQUENCY (MHz)
2x2 Half-IF IIP2
vs RF to LO Tone Spacing
90
90
100
5584 G08
IIP2 vs RF Tone Spacing
100
80
5584 G07
IIP2 (dBm)
IIP2 (dBm)
110
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
90
80
IIP2 vs IP2I, IP2Q Trim Voltage
I, –40°C
I, 25°C
I, 85°C
I, 105°C
TC = 25°C
100
80
5584 G06
130
Q, 0dBm
Q, 6dBm
Q, 10dBm
110
100
60
4
I, 0dBm
I, 6dBm
I, 10dBm
120
110
40
20
–10
I, –40°C
I, 25°C
I, 85°C
I, 105°C
120
Uncalibrated IIP2 vs LO Power
130
IIP2 (dBm)
50
Uncalibrated IIP2 vs Temperature
(TC)
80
70
80
70
70
60
60
50
0
50
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
IP2I, IP2Q (V)
60
ZFSCJ-2-1
BB COMBINER
1
10
100
RF TONE SPACING (MHz)
18
16
Noise Figure and Conversion
Gain vs LO Power
20
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
16
Q, 0dBm
Q, 6dBm
Q, 10dBm
12
10
8
GAIN
6
12
8
16
14
13
4
12
2
11
0
0
140
160
120
LO FREQUENCY (MHz)
180
200
5584 G12
80
100
140
160
120
LO FREQUENCY (MHz)
180
200
5584 G13
TC = 25°C
fRF = 160MHz
fLO = 159MHz
fNOISE = 60MHz
EIP2 = 5V
15
2
100
Q, –20dBm
Q, 0dBm
17
4
80
I, –20dBm
I, 0dBm
19
18
GAIN
6
20
TC = 25°C
NF
10
1000
Noise Figure vs RF Power and
IP2I, IP2Q Trim Voltage
14
NF, GAIN (dB)
14
NF, GAIN (dB)
I, 0dBm
I, 6dBm
I, 10dBm
18
NF
10
100
RF TO LO SPACING (MHz)
5584 G11
DSB NOISE FIGURE (dB)
Noise Figure and Conversion
Gain vs Temperature (TC)
I, –40°C
I, 25°C
I, 85°C
I, 105°C
1
5584 G10
5585 G09
20
50
1000
ZFSCJ-2-1
BB COMBINER
10
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
IP2I, IP2Q TRIM VOLTAGE (V)
5584 G14
5584f
6
LTC5584
Typical
Performance Characteristics
140MHz application. VCC = 5V, EN = 5V, EDC = 0V,
EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 130MHz, fRF1 = 140MHz, fRF2 = 141MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm,
DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted.
Test circuit with RF and LO ports impedance matched as in Figure 1.
DC Offset vs Temperature (TC)
10
10
9
8
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
I, –40°C
I, 25°C
I, 85°C
I, 105°C
80
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
100
160
140
180
120
LO FREQUENCY (MHz)
L-R, –40°C
L-R, 25°C
L-R, 85°C
L-R, 105°C
40
20
10
0
–2.5
–1.5
0.5
–0.5
DC OFFSET (mV)
200
DC Offset Distribution, Q-Side
30
1.5
40
fLO = 100MHz
30
20
10
0
2.5
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
–2.5
–1.5
0.5
–0.5
DC OFFSET (mV)
5584 G19
1.5
2.5
5584 G20
Image Rejection vs Temperature
100
R-L, –40°C
R-L, 25°C
R-L, 85°C
R-L, 105°C
90
–50
–60
–70
–80
–90
–100
TC = 25°C
160
140
180
120
LO FREQUENCY (MHz)
100
90
fLO = 100MHz
IMAGE REJECTION (dB)
–40
80
Q, 0dBm
Q, 6dBm
Q, 10dBm
5584 G17
PERCENTAGE DISTRIBUTION (%)
PERCENTAGE DISTRIBUTION (%)
0.8 0.9 1.0
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
LO to RF Leakage and RF to LO
Isolation
–30
I, 0dBm
I, 6dBm
I, 10dBm
DC Offset Distribution, I-Side
90
5584 G18
LEAKAGE (dBm), –ISOLATION (dB)
DC OFFSET (mV)
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
200
10
9
8
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
5584 G16
5584 G15
DC Offset vs DCOI, DCOQ Control
Voltage
40
I, –40°C
f = 140MHz
35 LO
I, 25°C
EDC = 5V
I, 85°C
30
I, 105°C
25
20
15
10
5
0
–5
–10
–15
–20
–25
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
DCOI, DCOQ (V)
DC Offset vs LO Power
DC OFFSET (mV)
DC OFFSET (mV)
DSB NOISE FIGURE (dB)
Noise Figure vs RF Input Power
24
PLO = 0dBm
23
PLO = 6dBm
22
PLO = 10dBm
21 T = 25°C
C
20 fLO = 159MHz
19 fRF = 160MHz
18 fNOISE = 60MHz
17
16
15
14
13
12
11
10
9
0
–20
–5
5
–15
–10
RF INPUT POWER (dBm)
80
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
70
60
50
40
30
80
100
160
140
120
LO FREQUENCY (MHz)
180
200
20
80
100
120
140
160
180
200
LO FREQUENCY (MHz)
5584 G21
5584 G22
5584f
7
LTC5584
Typical Performance Characteristics
450MHz application. VCC = 5V, EN = 5V, EDC = 0V,
REF = 0.5V, EIP2 = 0V, TC = 25°C, PLO = 6dBm, fLO = 440MHz, fRF1 = 450MHz, fRF2 = 451MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm, DC
Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test
circuit with RF and LO ports impedance matched as in Figure 1.
IIP3 and P1dB vs Supply Voltage
(VCC)
IIP3 and P1dB vs Temperature (TC)
IIP3, P1dB (dBm)
40
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
35
I, 4.75V
I, 5.0V
I, 5.25V
45
Q, 4.75V
Q, 5.0V
Q, 5.25V
TC = 25°C
IIP3
30
25
35
IIP3
30
25
10
200
300
400
600
500
LO FREQUENCY (MHz)
P1dB
10
200
700
300
400
600
500
LO FREQUENCY (MHz)
TC = 25°C
fRF1 = 450MHz
fRF2 = 451MHz
fLO = 440MHz
130
Q
I
25
–2
–4
0
RF POWER (dBm)
2
120
110
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
90
TC = 25°C
90
80
70
70
300
600
500
400
LO FREQUENCY (MHz)
60
200
700
300
600
500
400
LO FREQUENCY (MHz)
110
TC = 25°C
fRF1 = 450MHz
fLO = 440MHz
100
700
5584 G28
2x2 Half-IF IIP2
vs RF to LO Tone Spacing
IIP2 vs RF Tone Spacing
110
I (UNCALIBRATED)
I (NULLED AT 1MHz)
Q (UNCALIBRATED)
Q (NULLED AT 1MHz)
TC = 25°C
fLO = 450MHz
100
Q
I
90
IIP2 (dBm)
IIP2 (dBm)
80
Q, 0dBm
Q, 6dBm
Q, 10dBm
100
80
90
90
I, 0dBm
I, 6dBm
I, 10dBm
120
5584 G27
fRF = 450MHz
EIP2 = 5V
700
110
60
200
4
100
400
600
500
LO FREQUENCY (MHz)
Uncalibrated IIP2 vs LO Power
130
100
IIP2 vs IP2I, IP2Q Trim Voltage
I, –40°C
I, 25°C
I, 85°C
I, 105°C
300
5584 G25
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
5584 G26
130
10
200
700
IIP2 (dBm)
IIP2 (dBm)
IIP3 (dBm)
30
–6
25
15
110
35
–8
I, –40°C
I, 25°C
I, 85°C
I, 105°C
120
40
20
–10
30
Uncalibrated IIP2 vs Temperature
(TC)
2-Tone IIP3 vs RF Power
45
35
5584 G24
5584 G23
50
TC = 25°C
20
15
P1dB
Q, 0dBm
Q, 6dBm
Q, 10dBm
40
20
15
I, 0dBm
I, 6dBm
I, 10dBm
45
40
20
IIP2 (dBm)
IIP3 vs LO Power
50
IIP3 (dBm)
I, –40°C
I, 25°C
I, 85°C
I, 105°C
45
50
IIP3, P1dB (dBm)
50
80
70
80
70
70
60
60
50
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
IP2I, IP2Q (V)
5584 G29
50
60
ZFSCJ-2-1
BB COMBINER
1
10
100
RF TONE SPACING (MHz)
1000
5584 G30
50
ZFSCJ-2-1
BB COMBINER
1
10
100
RF TO LO SPACING (MHz)
1000
5584 G31
5584f
8
LTC5584
Typical Performance Characteristics
450MHz application. VCC = 5V, EN = 5V, EDC = 0V,
REF = 0.5V, EIP2 = 0V, TC = 25°C, PLO = 6dBm, fLO = 440MHz, fRF1 = 450MHz, fRF2 = 451MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm, DC
Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test
circuit with RF and LO ports impedance matched as in Figure 1.
Noise Figure and Conversion
Gain vs Temperature (TC)
Noise Figure vs RF Input Power
19
17
I, –40°C
I, 25°C
I, 85°C
I, 105°C
18
16
11
–15
16
–10
–5
0
RF INPUT POWER (dBm)
5
10
8
GAIN
2
2
300
500
600
400
LO FREQUENCY (MHz)
–2.5
300
600
500
400
LO FREQUENCY (MHz)
700
40
35
30
25
20
15
10
5
0
–5
–10
–15
–20
–25
I, –40°C
I, 25°C
I, 85°C
I, 105°C
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
0
L-R, –40°C
L-R, 25°C
L-R, 85°C
L-R, 105°C
TC = 25°C
2.5
0
300
600
500
400
LO FREQUENCY (MHz)
5584 G36
700
5584 G37
Image Rejection vs Temperature
100
R-L, –40°C
R-L, 25°C
R-L, 85°C
R-L, 105°C
90
–50
–60
–70
–80
–90
–100
200
Q, 0dBm
Q, 6dBm
Q, 10dBm
5.0
–5.0
200
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
DCOI, DCOQ (V)
LO to RF Leakage and RF to LO
Isolation
–40
7.5
I, 0dBm
I, 6dBm
I, 10dBm
–2.5
5584 G35
–30
700
DC Offset vs LO Power
10.0
fLO = 450MHz
EDC = 5V
IMAGE REJECTION (dB)
–5.0
200
500
600
400
LO FREQUENCY (MHz)
5584 G34
DC OFFSET (mV)
DC OFFSET (mV)
0
300
5584 G33
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
2.5
GAIN
0
200
700
DC Offset vs DCOI, DCOQ Control
Voltage
5.0
LEAKAGE (dBm), –ISOLATION (dB)
DC OFFSET (mV)
7.5
8
4
DC Offset vs Temperature (TC)
I, –40°C
I, 25°C
I, 85°C
I, 105°C
TC = 25°C
NF
10
6
5584 G32
10.0
12
4
0
200
10
Q, 0dBm
Q, 6dBm
Q, 10dBm
14
NF
12
6
13
I, 0dBm
I, 6dBm
I, 10dBm
18
14
15
9
–20
20
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
NF, GAIN (dB)
DSB NOISE FIGURE (dB)
21
20
PLO = 0dBm
PLO = 6dBm
PLO = 10dBm
TC = 25°C
fLO = 460MHz
fRF = 461MHz
fNOISE = 60MHz
NF, GAIN (dB)
23
Noise Figure and Conversion
Gain vs LO Power
80
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
70
60
50
40
30
300
600
500
400
LO FREQUENCY (MHz)
700
20
200
300
400
500
600
700
LO FREQUENCY (MHz)
5584 G38
5584 G39
5584f
9
LTC5584
Typical Performance Characteristics
900MHz application. VCC = 5V, EN = 5V,
EDC = 0V, EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 890MHz, fRF1 = 900MHz, fRF2 = 901MHz, fBB = 10MHz,
PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement
unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.
IIP3 and P1dB vs Supply Voltage
(VCC)
IIP3 and P1dB vs Temperature (TC)
IIP3, P1dB (dBm)
40
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
Q, 4.75V
Q, 5.0V
Q, 5.25V
TC = 25°C
IIP3
25
P1dB
15
10
400
600
35
IIP3
30
25
1200
1000
LO FREQUENCY (MHz)
P1dB
10
400
1400
600
800
1200
1000
LO FREQUENCY (MHz)
TC = 25°C
fRF1 = 900MHz
fRF2 = 901MHz
fLO = 890MHz
120
Q
I
25
–2
–4
0
RF POWER (dBm)
2
120
80
80
TC = 25°C
80
70
60
60
600
1200
1000
800
LO FREQUENCY (MHz)
50
400
1400
600
1200
1000
800
LO FREQUENCY (MHz)
2x2 Half-IF IIP2
vs RF to LO Tone Spacing
IIP2 vs RF Tone Spacing
110
TC = 25°C
fRF1 = 900MHz
fLO = 890MHz
100
1400
5584 G45
110
I (UNCALIBRATED)
I (NULLED AT 1MHz)
Q (UNCALIBRATED)
Q (NULLED AT 1MHz)
TC = 25°C
fLO = 900MHz
100
Q
I
90
IIP2 (dBm)
90
Q, 0dBm
Q, 6dBm
Q, 10dBm
90
70
90
100
I, 0dBm
I, 6dBm
I, 10dBm
110
5584 G44
fRF = 900MHz
EIP2 = 5V
1400
100
50
400
4
IIP2 (dBm)
IIP2 (dBm)
110
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
800
1200
1000
LO FREQUENCY (MHz)
Uncalibrated IIP2 vs LO Power
120
90
IIP2 vs IP2I, IP2Q Trim Voltage
I, –40°C
I, 25°C
I, 85°C
I, 105°C
600
5584 G42
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
5584 G43
130
10
400
1400
IIP2 (dBm)
IIP2 (dBm)
IIP3 (dBm)
30
–6
25
15
100
35
–8
I, –40°C
I, 25°C
I, 85°C
I, 105°C
110
40
20
–10
30
Uncalibrated IIP2 vs Temperature
(TC)
2-Tone IIP3 vs RF Power
45
35
5584 G41
5584 G40
50
TC = 25°C
20
15
800
Q, 0dBm
Q, 6dBm
Q, 10dBm
40
20
20
I, 0dBm
I, 6dBm
I, 10dBm
45
40
35
30
I, 4.75V
I, 5.0V
I, 5.25V
45
IIP3 vs LO Power
50
IIP3 (dBm)
I, –40°C
I, 25°C
I, 85°C
I, 105°C
45
50
IIP3, P1dB (dBm)
50
80
70
80
70
70
60
60
50
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
IP2I, IP2Q (V)
5585 G46
50
60
ZFSCJ-2-1
BB COMBINER
1
10
100
RF TONE SPACING (MHz)
1000
5584 G47
50
ZFSCJ-2-1
BB COMBINER
1
10
100
RF TO LO SPACING (MHz)
1000
5584 G48
5584f
10
LTC5584
Typical Performance Characteristics
900MHz application. VCC = 5V, EN = 5V,
EDC = 0V, EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 890MHz, fRF1 = 900MHz, fRF2 = 901MHz, fBB = 10MHz,
PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement
unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.
Noise Figure and Conversion
Gain vs Temperature (TC)
Noise Figure vs RF Input Power
19
17
I, –40°C
I, 25°C
I, 85°C
I, 105°C
18
16
11
–15
16
–10
–5
0
RF INPUT POWER (dBm)
5
10
8
GAIN
4
2
600
1000
1200
800
LO FREQUENCY (MHz)
10.0
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
I, 0dBm
I, 6dBm
I, 10dBm
7.5
0
600
1200
1000
800
LO FREQUENCY (MHz)
Q, 0dBm
Q, 6dBm
Q, 10dBm
TC = 25°C
5.0
2.5
0
–5.0
400
1400
600
1200
1000
800
LO FREQUENCY (MHz)
5584 G52
R-L, –40°C
R-L, 25°C
R-L, 85°C
R-L, 105°C
90
–50
–60
–70
–80
–90
–100
400
80
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
70
60
50
40
30
600
1200
1000
800
LO FREQUENCY (MHz)
1400
20
400
600
800
1000
1200
1400
LO FREQUENCY (MHz)
5584 G55
I, –40°C
I, 25°C
I, 85°C
I, 105°C
0
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
fLO = 900MHz
EDC = 5V
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
DCOI, DCOQ (V)
Conversion Gain Distribution
70
PERCENTAGE DISTRIBUTION (%)
L-R, –40°C
L-R, 25°C
L-R, 85°C
L-R, 105°C
1400
5584 G54
Image Rejection vs Temperature
100
IMAGE REJECTION (dB)
–40
1400
40
35
30
25
20
15
10
5
0
–5
–10
–15
–20
–25
5584 G53
LO to RF Leakage and RF to LO
Isolation
–30
1000
1200
800
LO FREQUENCY (MHz)
DC Offset vs DCOI, DCOQ Control
Voltage
–2.5
–5.0
400
600
5584 G51
DC OFFSET (mV)
2.5
–2.5
LEAKAGE (dBm), –ISOLATION (dB)
0
400
1400
DC Offset vs LO Power
5.0
GAIN
5584 G50
DC OFFSET (mV)
DC OFFSET (mV)
7.5
NF
8
2
DC Offset vs Temperature (TC)
I, –40°C
I, 25°C
I, 85°C
I, 105°C
TC = 25°C
10
6
5584 G49
10.0
12
4
0
400
10
Q, 0dBm
Q, 6dBm
Q, 10dBm
14
NF
12
6
13
I, 0dBm
I, 6dBm
I, 10dBm
18
14
15
9
–20
20
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
NF, GAIN (dB)
DSB NOISE FIGURE (dB)
21
20
PLO = 0dBm
PLO = 6dBm
PLO = 10dBm
TC = 25°C
fLO = 884MHz
fRF = 885MHz
fNOISE = 60MHz
NF, GAIN (dB)
23
Noise Figure and Conversion
Gain vs LO Power
5584 G56
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
60
50
40
30
20
10
0
4.7
4.9
5.1 5.3 5.5 5.7
CONVERSION GAIN (dB)
5.9
5584 G57
5584f
11
LTC5584
Typical Performance Characteristics
900MHz application. VCC = 5V, EN = 5V,
EDC = 0V, EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 890MHz, fRF1 = 900MHz, fRF2 = 901MHz, fBB = 10MHz,
PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement
unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.
70
60
50
40
30
20
10
70
60
50
40
30
20
10
0
26.5 27 27.5 28 28.5 29 29.5 30
IIP3 (dBm)
70
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
27
27.5
28
28.5
29
29.5
TC = 85°C
TC = 105°C
40
30
20
10
9
9.4
9.8
10.2
80
70
60
50
40
30
20
0
10.6
69
69.5
70
70.5 71
IIP2 (dBm)
71.5
5584 G61
90
50
40
30
20
10
–0.04 –0.02
80
70
0.02 0.04
0
GAIN ERROR (dB)
0.06
5584 G64
70
60
50
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
50
40
30
20
0
72
64.5
65.5
67.5
66.5
IIP2 (dBm)
68.5
5584 G63
50
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
30
20
10
0.4
0.5 0.6 0.7 0.8 0.9
PHASE ERROR (DEGREES)
69.5
Image Rejection Distribution
(Note 10)
40
0
11
60
Phase Error Distribution
PERCENTAGE DISTRIBUTION (%)
PERCENTAGE DISTRIBUTION (%)
60
0
100
5584 G62
Gain Error Distribution
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
10.2
10.6
9.4
9.8
DSB NOISE FIGURE (dB)
9
10
DSB NOISE FIGURE (dB)
70
10
5584 G60
10
0
20
IIP2 Distribution, Q-Side
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
90
50
30
IIP2 Distribution, I-Side
100
PERCENTAGE DISTRIBUTION (%)
PERCENTAGE DISTRIBUTION (%)
TC = –40°C
TC = 25°C
40
5584 G59
DSB Noise Figure Distribution,
Q-Side
60
50
IIP3 (dBm)
5584 G58
70
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
60
0
30
PERCENTAGE DISTRIBUTION (%)
0
80
PERCENTAGE DISTRIBUTION (%)
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
PERCENTAGE DISTRIBUTION (%)
PERCENTAGE DISTRIBUTION (%)
80
DSB Noise Figure Distribution,
I-Side
IIP3 Distribution, Q-Side
PERCENTAGE DISTRIBUTION (%)
IIP3 Distribution, I-Side
1.0
5584 G65
40
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
30
20
10
0
41
42
46 47
43 44 45
IMAGE REJECTION (dB)
48
5584 G66
5584f
12
LTC5584
Pin Functions
IP2Q, IP2I (Pin 1, Pin 4): IIP2 Adjustment Analog Control
Voltage Input for Q and I Channel. A decoupling capacitor
is recommended on this pin. A low output resistance voltage source is recommended for driving these pins. These
pins should be left floating if unused.
DCOQ, DCOI (Pin 2, Pin 3): DC Offset Analog Control
Voltage Input for Q and I Channel. A decoupling capacitor is recommended on this pin. A low output resistance
voltage source is recommended for driving these pins.
These pins should be left floating if unused.
RF+, RF– (Pin 5, Pin 6): RF Differential Inputs. An external
balun transformer with matching is used to obtain good
return loss across the RF input frequency range. The RF
pin should be DC-blocked with a 0.01µF coupling capacitor.
GND (Pins 8, 13, 14, Exposed Pad Pin 25): Ground.
These pins must be soldered to the RF ground plane
on the circuit board. The backside exposed pad ground
connection should have a low inductance connection and
good thermal contact to the printed circuit board ground
plane using many through-hole vias. See Figures 2 and 3.
EN (Pin 7): Enable Pin. When the voltage on the EN pin
is a logic high, the chip is completely turned on; the chip
is completely turned off for a logic low. An internal 200k
pull-down resistor ensures the chip remains disabled if
there is no connection to the pin (open-circuit condition).
VBIAS (Pin 9): This pin can be pulled to ground through
a resistor to lower the current consumption of the chip.
See Applications Information.
VCC (Pin 10): Positive Supply Pin. This pin should be
bypassed with shunt 0.01µF and 1µF capacitors.
EDC (Pin 11): DC Offset Adjustment Mode Enable Pin.
When the voltage on the EDC pin is a logic high, the DC
offset control circuitry is enabled. The circuitry is disabled
for a logic low. An internal 200k pull-down resistor ensures
the circuitry remains disabled if there is no connection to
the pin (open-circuit condition).
EIP2 (Pin 12): IP2 Offset Adjustment Mode Enable Pin.
When the voltage on the EIP2 pin is a logic high, the IP2
adjustment circuitry is enabled. The circuitry is disabled
for a logic low. An internal 200k pull-down resistor ensures
the circuitry remains disabled if there is no connection to
the pin (open-circuit condition).
LO+,LO– (Pin 15, Pin 16): LO Inputs. External matching
is required to obtain good return loss across the LO input
frequency range. Can be driven single ended or differentially with an external transformer. The LO pins should be
DC-blocked with 0.01µF coupling capacitors.
VCAP, CMQ, CMI (Pin 17, Pin 18, Pin 19): Common Mode
Bypass Capacitor Pins. It is recommended that CMI and
CMQ be connected to VCAP through 0.1µF capacitors.
Nothing else should be connected to VCAP since it is connected to VCC inside the chip.
I+, I–, Q+, Q– (Pin 23, Pin 22, Pin 21, Pin 20): Differential
Baseband Output Pins for the I Channel and Q Channel.
The DC bias point is VCC – 1.5V for each pin. These pins
must have an external 100Ω or an inductor pull-up to VCC.
REF (Pin 24): Voltage Reference Input for Analog Control
Voltage Pins. A decoupling capacitor is recommended
on this pin. A low output resistance voltage source is
recommended for driving this pin. This pin should be left
floating if unused.
5584f
13
LTC5584
Block Diagram
5
6
10
VCC
RF+
17
VCAP
CMI
I+
I–
RF–
IP2 AND DC
OFFSET CAL
15
16
0°
LO–
EIP2
90°
REF
7
VBIAS
EN
IP2I
EDC
LO+
IP2 AND DC
OFFSET CAL
9
DCOI
IP2Q
DCOQ
Q+
Q–
BIAS
CMQ
GND
8
GND
13
GND
14
EXPOSED
PAD
25
19
23
22
3
4
11
12
24
1
2
21
20
18
5584 BD
5584f
14
LTC5584
Test Circuit
0.015"
0.062"
RF
GND
DC
GND
NELCO N4000-13
0.015"
C29
R9
C21
R11
C22
R13
C30
R14
I– OUT
Q+ OUT
I+ OUT
Q– OUT
C10
REF
C32
C33
5
C35
C34
6
RF
L6
6
C17 C19
4
•
T2
C40
•
1
2
C41
Q–
Q+
I–
REF
CMI
LO–
LTC5584IUF
IP2I
LO+
+
RF
RF–
7
8
9
EIP2
IP2I
DCOI
EDC
4
VCAP
VCC
DCOI
DCOQ
VBIAS
3
CMQ
GND
2
DCOQ
IP2Q
EN
1
IP2Q
I+
24 23 22 21 20 19
C31
18
C11
17
16
15
C38
GND
13
GND
25
GND
T1
3
2
14
C39
1
4
•
•
6
10 11 12
LO
C13 C14
EIP2
EDC
3
EN
L5
C15
C16
VCC
4.75V TO 5.25V
5584 F01
RF MATCH
FREQUENCY RANGE
C17
140MHz
450MHz
900MHz
REF DES
VALUE
1.5pF
SIZE
LO MATCH
L6
C19
68nH
8.0pF
15nH
1.0pF
5.6nH
VENDOR
C13
L5
C14
82nH
12nH
2.2pF
4.0pF
3.9nH
REF DES
VALUE
SIZE
VENDOR
C10, C11, C31-C35
0.1μF
0402
Murata
L5, L6
See Table
0402
Murata
C15, C38-C41
0.01µF
0402
Murata
R9, R11, R13, R14
100Ω
0402
Vishay
C13, C14, C17, C19
See Table
0402
Murata
T1, T2
1:1
AT224-1
Mini-Circuits
TC1-1-13M+
C16, C21, C22, C29, C30
1μF
0402
Murata
Figure 1. Test Circuit Schematic
5584f
15
LTC5584
Test Circuit
Figure 2. Component Side of Evaluation Board
Figure 3. Bottom Side of Evaluation Board
Applications Information
The LTC5584 is an IQ demodulator designed for high
dynamic range receiver applications. It consists of RF
transconductance amplifiers, I/Q mixers, quadrature LO
amplifiers, IIP2 and DC offset correction circuitry, and
bias circuitry.
Operation
As shown in the Block Diagram for the LTC5584, the RF
signal is applied to the inputs of the RF transconductor
V-to-I converters and is then demodulated into I/Q
baseband signals using quadrature LO signals which are
internally generated by a precision 90° phase shifter. The
demodulated I/Q signals are lowpass filtered on-chip with
a –3dB bandwidth of 530MHz. The differential outputs of
the I-channel and Q-channel are well matched in amplitude
and their phases are 90° apart.
RF Input Port
Figure 4 shows the demodulator’s differential RF input
which consists of high linearity transconductance amplifiers (V-I converters). External DC voltage should not be
applied to the RF input pins. DC current flowing into the
pins may cause damage to the transconductance amplifiers.
Series DC blocking capacitors should be used to couple
the RF input pins to the RF signal source.
The RF input port can be externally matched over the
operating frequency range with simple L-C matching.
An input return loss greater than 10dB can be obtained
over a fractional bandwidth of greater than 66% with
this method. Figure 5 shows the RF input return loss for
various matching component values. Table 1 shows the
differential and single-ended S parameters for the RF input
without using any external matching components. The
input transmission line length and balun are de-embedded
from the measurement.
5584f
16
LTC5584
Applications Information
RF
INPUT
(MATCHED)
L6
C17
T2
MINI-CIRCUITS
TC1-1-13M+
6 •
• 1
2
C19 4
3
C40
0.01µF
LTC5584
BIAS
RF+
RF–
C41
0.01µF
Larger bandwidths can be obtained by using more elements. For example Figure 6 shows an L-C match having
a bandwidth of about 98% where return loss is >10dB.
Figure 7 shows the RF input return loss for the wide
bandwidth match.
0
–5
5584 F04
RETURN LOSS (dB)
GND
Figure 4: Simplified Schematic of the RF Interface
Table 1. RF Input S Parameters
S11 (SINGLE ENDED)
MAG
ANGLE(°)
MAG
ANGLE(°)
10
0.5657
–2.416
0.3253
–5.287
20
0.55
–2.674
0.3055
–5.761
40
0.5391
–2.288
0.2938
–4.499
80
0.5349
–2.268
0.2984
–4.517
140
0.5336
–2.946
0.3097
–9.805
200
0.5329
–3.836
0.2989
–16.34
300
0.5317
–5.453
0.2732
–21.46
400
0.5301
–7.128
0.2614
–24.35
450
0.5292
–7.975
0.2583
–25.79
500
0.5282
–8.826
0.2562
–27.29
600
0.5258
–10.54
0.2536
–30.43
700
0.523
–12.25
0.2523
–33.66
800
0.5199
–13.97
0.2517
–36.88
900
0.5164
–15.7
0.2519
–39.97
1000
0.5124
–17.43
0.2529
–42.85
1100
0.5082
–19.17
0.2556
–45.49
1200
0.5035
–20.91
0.2609
–48.02
1300
0.4985
–22.66
0.2693
–50.73
1400
0.4931
–24.42
0.2804
–53.98
1500
0.4873
–26.19
0.2925
–57.96
1600
0.4812
–27.97
0.3035
–62.52
1700
0.4747
–29.77
0.3122
–67.36
1800
0.4678
–31.58
0.3187
–72.19
1900
0.4606
–33.41
0.3235
–76.87
2000
0.453
–35.26
0.3271
–81.36
Note: Differential S parameters measured with 1:1 balun and singleended S parameters measured with 50Ω termination on unused port.
–15
–20
TC = 25°C
L6 = 68nH, C19 = 8.0pF
L6 = 15nH, C19 = 1.0pF
C17 = 1.5pF, L6 = 5.6nH
NO MATCHING
–25
–30
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
FREQUENCY (GHz)
5584 F05
Figure 5. RF Input Return Loss
RF INPUT
650MHz TO
950MHz
L7
5.6nH
L6
7.5nH
C17
2.7pF
T2
MINI-CIRCUITS
TC1-1-13M+
6 •
• 1
2
4
3
C40
0.01µF
RF+
LTC5584
BIAS
RF–
C41
0.01µF
5584 F06
GND
Figure 6. Wide Bandwidth RF Input Match
0
TC = 25°C
C17 = 2.7pF
L6 = 7.5nH
L7 = 5.6nH
–5
RETURN LOSS (dB)
FREQUENCY
(MHz)
S11 (DIFFERENTIAL)
–10
–10
–15
–20
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
FREQUENCY (GHz)
5584 F07
Figure 7. RF Input Return Loss for Wideband Match
5584f
17
LTC5584
Applications Information
Broadband Performance
LO Input Port
To get an idea of the broadband performance of the
LTC5584, a 6dB pad can be put on the RF and LO ports,
and the ports can be left unmatched. The measured RF
performance for this configuration is shown in Figures 8,
9, 10 and 11 with the 6dB pad de-embedded. The RF
tone spacing is 1MHz, and fLO is 10MHz lower than fRF.
The conversion gain is lower than under the impedance
matched condition, and correspondingly the P1dB, IIP3,
and NF are higher. As shown, the part can be used at
frequencies outside its specified operating range with
reduced conversion gain and higher NF.
The demodulator’s LO input interface is shown in Figure 12. The input consists of a high precision quadrature
phase shifter which generates 0° and 90° phase shifted
LO signals for the LO buffer amplifiers to drive the I/Q
mixers. DC blocking capacitors are required on the LO+
and LO– inputs.
50
I, –40°C
I, 25°C
I, 85°C
I, 105°C
45
20
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
16
IIP3
30
25
NF
12
10
8
GAIN
6
20
4
P1dB
15
0
2
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LO FREQUENCY (GHz)
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LO FREQUENCY (GHz)
5584 F08
5584 F10
Figure 8. Broadband IIP3 and IP1dB
I, –40°C
I, 25°C
I, 85°C
I, 105°C
130
120
100
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
TC = –40°C
TC = 25°C
TC = 85°C
TC = 105°C
90
110
IIP2 (dBm)
Figure 10. Broadband NF and Gain
IMAGE REJECTION (dB)
140
100
90
80
70
60
80
70
60
50
40
30
50
40
Q, –40°C
Q, 25°C
Q, 85°C
Q, 105°C
14
35
10
I, –40°C
I, 25°C
I, 85°C
I, 105°C
18
NF, GAIN (dB)
IIP3, P1dB (dBm)
40
The differential and single-ended LO input S parameters
with the input transmission lines and balun de-embedded
are listed in Table 2.
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LO FREQUENCY (GHz)
5584 F09
Figure 9. Broadband IIP2
20
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LO FREQUENCY (GHz)
5584 F11
Figure 11. Broadband Image Rejection
5584f
18
LTC5584
Applications Information
VCC
LTC5584
LO
INPUT
(MATCHED)
L5
C14
C13
MINI-CIRCUITS
TC1-1-13M+
6 •
• 1
2
4
3
C39
0.01µF
TO IDENTICAL
Q-CHANNEL
LO+
LO–
PHASE SHIFTER
C38
0.01µF
5584 F12
GND
Figure 12. Simplified Schematic of LO Input Interface with External Matching Components
FREQUENCY
(MHz)
S11 (DIFFERENTIAL)
MAG
ANGLE(°)
S11 (SINGLE ENDED)
MAG
ANGLE(°)
10
0.8138
–1.736
0.7869
–1.896
20
0.8485
–6.615
0.8127
–6.425
40
0.7857
–18.67
0.7382
–16.33
80
0.6608
–25.61
0.6356
–20.1
140
0.5968
–33.93
0.5801
–25.43
200
0.5515
–42.29
0.5395
–30.5
300
0.4932
–54.56
0.4911
–37.49
400
0.4538
–65.21
0.4606
–43.5
450
0.4396
–70.18
0.4498
–46.36
500
0.4283
–75.01
0.441
–49.17
600
0.412
–84.37
0.4278
–54.67
700
0.4018
–93.45
0.4187
–60.04
800
0.3958
–102.3
0.4124
–65.26
900
0.3928
–110.9
0.4083
–70.32
1000
0.3921
–119.2
0.4059
–75.21
1100
0.3931
–127.2
0.405
–79.94
1200
0.3955
–135
0.4052
–84.52
1300
0.399
–142.4
0.4064
–88.94
1400
0.4035
–149.5
0.4084
–93.23
1500
0.4088
–156.3
0.411
–97.37
1600
0.4148
–162.9
0.4143
–101.4
1700
0.4213
–169.1
0.4181
–105.3
1800
0.4283
–175.1
0.4224
–109.1
1900
0.4357
–180.8
0.4271
–112.8
2000
0.4435
–186.2
0.4322
–116.4
Figure 13 shows LO input return loss using the MiniCircuits TC1-1-13M+ 1:1 balun with various matching
component values.
For optimum IIP2 and large-signal NF performance the LO
inputs should be driven differentially with a 1:1 balun such
as the Mini-Circuits TC1-1-13M+ or M/A Com ETC1-1-13.
As shown in Figure 14, the LO input can also be driven
single-ended from either the LO+ or LO– input. The unused
port should be DC-blocked and terminated with a 50Ω load.
Figure 15 compares the uncalibrated IIP2 performance of
single ended versus differential LO drive.
0
–5
RETURN LOSS (dB)
Table 2. LO Input S-Parameters
–10
–15
–20
–25
–30
TC = 25°C
L5 = 82nH
L5 = 12nH, C14 = 4.0pF
C13 = 2.2pF, L5 = 3.9nH
NO MATCHING
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
FREQUENCY (GHz)
5584 F13
Figure 13. LO Input Return Loss
Note: Differential S parameters measured with 1:1 balun and singleended S parameters measured with 50Ω termination on unused port.
5584f
19
LTC5584
Applications Information
VCC
LTC5584
LO
INPUT
(MATCHED)
C39
0.01µF
L5
C13
50Ω
LO+
LO–
C38
0.01µF
PHASE SHIFTER
5584 F14
GND
Figure 14. Recommended Single-Ended LO Input Configuration
100
90
IIP2 (dBm)
80
60
40
30
when the output port is terminated by RLOAD(SE). For instance, the gain is reduced by 6dB when each output pin is
connected to a 50Ω load (or 100Ω differentially). The output
should be taken differentially (or by using differential-tosingle-ended conversion) for best RF performance, including NF and IIP2. When no external filtering or matching
components are used, the output response is determined
by the loading capacitance and the total resistance loading
the outputs. The –3dB corner frequency, fC, is given by
the following equation:
fC = [2π(RLOAD(SE)||100Ω||RPULL-UP) (6pF)]–1
70
50
1

50Ω
20Log10  +
 dB
 2 RPULL-UP ||RLOAD(SE) 
TC = 25°C
SINGLE-ENDED LO, I-SIDE
DIFFERENTIAL LO, I-SIDE
SINGLE-ENDED LO, Q-SIDE
DIFFERENTIAL LO, Q-SIDE
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LO FREQUENCY (GHz)
5584 F15
Figure 15. Broadband IIP2 with Differential
and Single-Ended LO Drive
I-Channel and Q-Channel Outputs
The phase relationship between the I-channel output
signal and the Q-channel output signal is fixed. When the
LO input frequency is higher (or lower) than the RF input
frequency, the Q-channel outputs (Q+, Q–) lead (or lag)
the I-channel outputs (I+, I–) by 90°.
Each of the I-channel and Q-channel outputs is internally
connected to VCC through a 100Ω resistor. In order to
maintain an output DC bias voltage of VCC – 1.5V, external
100Ω pull-up resistors or equivalent 15mA DC current
sources are required. Each single-ended output has an
impedance of 100Ω in parallel with a 6pF internal capacitor. With an external 100Ω pull-up resistor this forms a
lowpass filter with a –3dB corner frequency at 530MHz.
Figure 16 shows the actual measured output response
with various load resistances.
Figure 17 shows a simplified model of the I, Q outputs
with a 100Ω differential load and 100Ω pull-ups. The –1dB
bandwidth in this configuration is about 520MHz, or about
twice the –1dB bandwidth with no load.
Figure 18 shows a simplified model of the I, Q outputs
with a L-C matching network for bandwidth extension.
Capacitor CS serves to filter common mode LO switching
noise immediately at the demodulator outputs. Capacitor
CC in combination with inductor LS is used to peak the
CONVERSION GAIN (dB)
C14
TO IDENTICAL
Q-CHANNEL
The outputs can be DC coupled or AC coupled to external loads. The voltage conversion gain is reduced by the
external load by:
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
TC = 25°C
RLOAD(DIFF) = 100Ω, BW = 850MHz
RLOAD(DIFF) = 200Ω, BW = 630MHz
RLOAD(DIFF) = 400Ω, BW = 530MHz
RLOAD(DIFF) = 1kΩ, BW = 460MHz
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
BASEBAND FREQUENCY (GHz)
Figure 16. Conversion Gain Baseband Output Response with
RLOAD(DIFF) = 100Ω, 200Ω, 400Ω and 1k and RPULL-UP = 100Ω
5584f
20
LTC5584
Applications Information
output response to give greater bandwidth of 650MHz. In
this case, capacitor CC was chosen as a common mode
capacitor instead of a differential mode capacitor to increase
rejection of common mode LO switching noise.
with a 5V supply, will ensure optimum performance. Each
output can sink no more than 30mA when the outputs are
connected to an external load with a DC voltage higher
than VCC – 1.5V.
When AC output coupling is used, the resulting highpass
filter’s –3dB roll-off frequency, fC, is defined by the R-C
constant of the external AC coupling capacitance, CAC, and
the differential load resistance, RLOAD(DIFF):
In order to achieve the best IIP2 performance, it is important to minimize high frequency coupling among the
baseband outputs, RF port, and LO port. Although it may
increase layout complexity, routing the baseband output
traces on the backside of the PCB can improve uncalibrated
IIP2 performance. Figure 19 shows the alternate layout
having the baseband outputs on the backside of the PCB.
fC = [2π • RLOAD(DIFF) • CAC]–1
Care should be taken when the demodulator’s outputs
are DC coupled to the external load to make sure that the
I/Q mixers are biased properly. If the current drain from
the outputs exceeds about 6mA, there can be significant
degradation of the linearity performance. Keeping the common mode output voltage of the demodulator above 3.15V,
VCC
VCC
LTC5584
6pF
100Ω
100Ω
1k
30mA
AC CURRENT
SOURCE
6pF
PACKAGE
PARASITICS
1.5nH
I+
1.5nH
I–
0.2pF
0.2pF
RPULL-UP
100Ω
RPULL-UP
100Ω
RLOAD(DIFF)
100Ω
–1dB BW = 520MHz
30mA
5584 F17
GND
Figure 17. Simplified Model of the Baseband Output
Figure 19. Alternate Layout of PCB with
Baseband Outputs on the Backside
VCC
VCC
LTC5584
6pF
100Ω
100Ω
1k
30mA DC
AC CURRENT
SOURCE
6pF
PACKAGE
PARASITICS
1.5nF
I
1.5nF
I–
0.2pF
0.2pF
+
30mA DC
CS
2pF
LS
10nH
LS
10nH
CS
2pF
CC
4pF
RPULL-UP
100Ω
6mA MAX DC
CC
4pF
RPULL-UP
100Ω
RLOAD(DIFF)
100Ω
LOWPASS
–1dB BW = 650MHz
5584 F18
GND
Figure 18. Simplified Model of the Baseband Output Showing Bandwidth Extension with External L, C Matching
5584f
21
LTC5584
Applications Information
Analog Control Voltage Pins
As shown in Figure 21, the REF pin is similar to the DCOI
pin, but the bias current source is 250µA, and the internal resistance is 2k. If this pin is left disconnected, it will
self-bias to 500mV. A low impedance voltage source with
a source resistance of less than 200Ω is recommended
to drive this pin. The control voltage range of the DCOI,
DCOQ, IP2I and IP2Q pins is set by the REF pin. This range
is equal to 0V to twice the voltage on the REF pin, whether
internally or externally applied.
It is recommended to decouple any AC noise present on
the signal lines that connect to the analog control-voltage
inputs. A shunt capacitor to ground placed close to these
pins can provide adequate filtering. For instance, a value
of 1000pF on the DCOI, DCOQ, IP2I and IP2Q pins will
provide a corner frequency of around 6 to 7MHz. A similar
corner frequency can be obtained on the REF pin with a
value of 3900pF. Using larger capacitance values such as
0.1µF is recommended on these pins unless a faster control
response is needed. Figure 22 shows the input response
–3dB bandwidth for the pins versus shunt capacitance
when driven from a 50Ω source.
DC Offset Adjustment Circuitry
Any sources of LO leakage to the RF input of a direct
conversion receiver will contribute to the DC offsets of
its baseband outputs. The LTC5584 features DC offset
adjustment circuitry to reduce such effects. When the
EDC pin is a logic high the circuitry is enabled and the
resulting DC offset adjustment range is typically ±20mV.
In a typical direct conversion receiver application, DC
offset calibration will be done periodically at a time when
no receive data is present and when the receiver DC levels
have sufficiently settled.
LTC5584
62.5µA
DCOI, DCOQ,
IP2I, IP2Q
8k
5584 F20
GND
Figure 20. Simplified Schematic of the Interface for the
DCOI, DCOQ, IP2I and IP2Q Pins
VCC
LTC5584
250µA
REF
2k
5584 F21
GND
Figure 21. Simplified Schematic of the REF Pin Interface
0
TC = 25°C
–1
–2
RESPONSE (dB)
Figure 20 shows the equivalent circuit for the DCOI, DCOQ,
IP2I, and IP2Q pins. Internal temperature compensated
62.5μA current sources keep these pins biased at a nominal
500mV through 8k resistors. A low impedance voltage
source with a source resistance of less than 200Ω is
recommended to drive these pins.
VCC
–3
–4
–5
–6
–7
–8
DCOI, DCOQ; C = 470pF
DCOI, DCOQ; C = 1000pF
IP2I, IP2Q; C = 100pF
–9
–10
0
2
4
6 8 10 12 14 16 18 20
5584 F22
FREQUENCY (MHz)
Figure 22. Input Response Bandwidth for the
DCOI, DCOQ, IP2I and IP2Q Pins
5584f
22
LTC5584
Applications Information
DC Offset Adjustment Example
Figure 23 shows a typical direct conversion receive path
having a DSP feedback path for DC offset adjustment.
Any sources of LO leakage to the RF input of the LTC5584
demodulator will contribute to the DC offset of the receiver.
This includes both static and dynamic DC offsets. If the
coupling is static in nature due to fixed board-level leakage
paths, the resulting DC offset does not typically need to
be adjusted at a high repetition rate. Dynamic DC offsets
due to transmitter transient leakage or antenna reflection
can be much harder to correct for and will require a faster
update rate from the DSP.
LO leakage into the RF port of the demodulator causes a
DC offset at the baseband outputs which is then multiplied
by the gain in the baseband path. The usable ADC voltage
window will be reduced by the amplified DC offset, resulting
in lower dynamic range. Using DSP, this DC offset value
can be averaged and sampled at a given update rate and
then a 1D minimization algorithm can be applied before
a new DCOI or DCOQ control signal is generated to minimize the offset. The 1-D minimization algorithm can be
implemented in many ways such as golden-section search,
backtracking, or Newton’s method.
limit of about 200MHz. Any IM2 component that falls in this
frequency range can be minimized. Beyond this frequency,
the gain of the IM2 correction amplifier falls off appreciably
and the circuit no longer improves IP2 performance. The
lower baseband frequency limit of the IM2 adjustment
circuitry is set by the common mode reference decoupling
capacitor at the CMI and CMQ pins. Below this frequency
the circuit can not minimize the IM2 component.
Figure 24 shows the CMI (and identical CMQ) pin interface.
These pins have an internal 40pF decoupling capacitance
to VCC, to provide a reference for the IP2 adjustment circuitry. The lower 3dB frequency limit, fC, of the circuitry
is set by the following equation:
fC = [2π • 500(40pF + CCM(EXT))]–1
Without any external capacitor on the CMI or CMQ pin the
lower limit is 8MHz. By adding a 0.1μF capacitor, CCM(EXT),
between the CMI and CMQ pins to VCAP, the lower –3dB
frequency corner can be reduced to 3kHz. Figure 25 shows
IIP2 as a function of RF frequency spacing versus common
mode decoupling capacitance values of 0.1µF and 1500pF.
There is effectively no limit on the size of this capacitor,
VCC
LTC5584
VCAP
IM2 Adjustment Circuitry
The LTC5584 also contains circuitry for the independent
adjustment of IM2 levels on the I and Q channels. When
the EIP2 pin is a logic high, this circuitry is enabled and
the IP2I and IP2Q analog control voltage inputs are able
to adjust the IM2 level. The IM2 level can be effectively
minimized over a large range of the baseband bandwidth.
The circuitry has an effective baseband frequency upper
40pF
CMI OR CMQ
5584 F24
GND
Figure 24. Equivalent Circuit of the CMI and CMQ Pin Interfaces
DSP
DAC
DCOI
BPF
LNA
ADC
DC
AVERAGING
LOWPASS
FILTER
1-D
MINIMIZATION
ALGORITHM
SAMPLE AND
HOLD
LTC5584
fLO = 900MHz
5585 F23
Figure 23. Block Diagram of a Receiver with a DSP Feedback Loop for DC Offset Adjustment
5584f
23
LTC5584
Applications Information
other than the impact it has on enable time for the IM2
circuitry to be operational. When the chip is disabled, there
is no current in the I or Q mixers, so the common mode
output voltage will be equal to VCC (if no DC common mode
current is being drawn by external baseband circuitry such
as a baseband amplifier). When the chip is enabled, the
off-chip common mode decouping capacitor must charge
up through a 500Ω resistor. The time constant for this is
essentially 500Ω times the common mode decoupling
capacitance value. For example, with a 0.01µF capacitor
this wait time is approximately 30μs. Figure 26 shows
the pulsed enable response of the common-mode output
voltage with 0.01µF on the CMI and CMQ pins.
130
0.1µF (UNCALIBRATED)
0.1µF (NULLED IP2I = 0.6V)
1500pF (UNCALIBRATED)
1500pF (NULLED IP2I = 0.6V)
110 T = 25°C
C
fRF1 = 1000MHz
100 f = 960MHz
LO
IIP2 (dBm)
120
90
80
70
60
0.1
1
10
RF FREQUENCY SPACING (MHz)
5584 F25
Figure 25. IIP2 vs Common Mode Decoupling Capacitance
VCM (V)
6
5
EN PULSE ON
0
5
–5
CMI, CMQ
4
3
ENABLE VOLTAGE (V)
EN
PULSE
OFF
–10
0
A simplified schematic of the EN pin is shown in Figure 28.
The enable voltage necessary to turn on the LTC5584 is 2V.
To disable or turn off the chip, this voltage should be below
0.3V. If the EN pin is not connected, the chip is disabled.
Figures 29 and 30 show the simplified schematics for the
EDC and EIP2 pins.
10
TC = 25°C
CCMI,Q = 0.01µF
7
IM2 adjustment circuitry can be used in a typical transceiver
loop-back application as shown in Figure 27. In this example
a 2-tone SSB training source of f1 = 20MHz and f2 = 21MHz
is generated in DSP and upconverted by the LTC5588-1
quadrature modulator to RF tones at 870MHz and 871MHz
using an LO source at 850MHz. A narrowband RF filter is
required to remove the IM2 component generated by the
LTC5588-1. During the loopback test these RF tones are
routed through high isolation switches and an attenuation
pad to the LTC5584 demodulator input. The tones are then
downconverted by the same LO source at 850MHz to
produce two tones at the baseband outputs of 20MHz and
21MHz plus an IM2 impairment signal at 1MHz. After baseband channel filtering and amplification the output of the
ADC is filtered by a 1MHz bandpass filter in DSP to isolate
the IM2 tone. The power in this tone is calculated in DSP
and then a 1-D minimization algorithm is applied to calculate
the correction signal for the IP2I control voltage pin. The
1-D minimization algorithm can be implemented in many
ways such as golden-section search, backtracking or
Newton’s method.
Enable Interface
50
0.01
8
IM2 Suppression Example
BASEBAND OUTPUTS
–15
10 20 30 40 50 60 70 80 90 100
TIME (µs)
5584 F26
Figure 26. Common Mode Output Voltage with a Pulsed Enable
It is important that the voltage applied to the EN, EDC and
EIP2 pins should never exceed VCC by more than 0.3V.
Otherwise, the supply current may be sourced through the
upper ESD protection diode connected at the pin. Under
no circumstances should voltage be applied directly to
the enable pins before the supply voltage is applied to
the VCC pin. If this occurs, damage to the IC may result.
A 1k resistor in series with the enable pin can be used to
limit current.
Reducing Power Consumption
Figure 31 shows the simplified schematic of the VBIAS
interface. The VBIAS pin can be used to lower the mixer
5584f
24
LTC5584
Applications Information
DSP
1-D
MINIMIZATION
ALGORITHM
DAC
1MHz BPF
IP2I
LNA
RMS
DETECTION
ADC
LTC5584
LOOPBACK
fLO = 850MHz
f1 = 20MHz
+
DAC
PA
f2 = 21MHz
LTC5588-1
5584 F27
Figure 27. Block Diagram for a Direct Conversion Transceiver with IM2 Adjustment. Only the I-Channel Is Shown
VCC
VCC
LTC5584
LTC5584
EIP2
EN
100k
100k
10k
100k
100k
5584 F28
5584 F30
GND
GND
Figure 28. Simplified Schematic of the EN Pin Interface
Figure 30. Simplified Schematic of the EIP2 Pin Interface
VCC
VCC
LTC5584
LTC5584
EDC
VBIAS
OPTIONAL R
TO REDUCE
CURRENT
100k
100Ω
EN
COPT
100k
EN
5584 F29
GND
5584 F31
GND
Figure 29. Simplified Schematic of the EDC Pin Interface
Figure 31. Simplified Schematic of the VBIAS Pin Interface
core bias current and total power consumption for the
chip. For example, adding 487Ω from the VBIAS pin to
GND will lower the DC current to 169mA, at the expense
of reduced IIP3 performance. Figure 32 shows IIP3 and
P1dB performance versus DC current and resistor value.
An optional capacitor, COPT in Figure 31, has minimal effect
on improving PSRR and IIP2.
5584f
25
LTC5584
Applications Information
50
45
P1dB, IIP3 (dBm)
40
35
I, 194mA
I, 169mA, 487Ω
I, 145mA, 294Ω
TC = 25°C
fRF = 900MHz
where P0 is the input noise power and –174dBm is the
input thermal noise power in a 1Hz bandwidth. A measured
2-tone output spectrum at 890MHz is shown in Figure 36.
IIP3 is calculated from the 2-tone IM3 levels:
Q, 194mA
Q, 169mA, 487Ω
Q, 145mA, 294Ω
IIP3
30
IIP3 = (–6.929 – (–88.33))/2 – 15.4
25
IIP3 = 25.3dBm
20
P1dB
15
10
5
0
400
600
1200
1000
800
RF FREQUENCY (MHz)
1400
5584 F32
Figure 32. IIP3 and P1dB vs DC Current
and VBIAS Resistor Value
For this example, receiver noise floor is approximated by
a measurement from 28MHz to 36MHz offset frequency,
where adequate filtering for RF and LO signals was possible. Using the test data from Figure 36, the receiver
noise figure for the I-channel (Ch 1) is calculated using the
–8.4dBm input power, 15kHz bin width, 40MHz bandwidth,
and –108dBFS measured in-band noise floor:
SNRIN = PIN – P0
900MHz Receiver Application
SNRIN = –8.4 – (–174 + 76) = 89.6dB
Figure 33 shows a typical receiver application consisting of
the chain of LNA, demodulator, lowpass filter, ADC driver,
and ADC. Total DC power consumption is about 2.1W. Fullscale power at the RF input is –8.4dBm. The Chebychev
lowpass filter with unequal terminations is designed using the method shown in the appendix. Filter component
values are then adjusted for the best overall response
and available component values. A positive voltage gain
slope with frequency is necessary to compensate for the
roll-off contributed by the ADC Driver and Anti-Alias Filter.
From the chain analysis shown in Figure 34, the IIP3-NF
dynamic range figure of merit (FOM) is 5.3dB at the LNA
input, 11.3dB at the demodulator input, and 16.8dB at the
ADC driver amp input.
SNROUT = –10 Log10(BinW/BW) – Floor
SNROUT = –43.3 + 108 = 73.7dB
NF = SNRIN – SNROUT
NF = 89.6 – 73.7 = 15.9dB
Finally, the receiver spurious free dynamic range can be
calculated using the measured data at 890MHz:
SFDR = 2(IIP3 – NF – P0)/3
SFDR = 2(25.3 – 15.9 – (–174 + 76))/3
SFDR = 73dB
The measured 6th order lowpass baseband response is
shown in Figure 35.
The receiver spurious free dynamic range (SFDR) in terms
of FOM can be calculated using the following equations:
FOM = IIP3 – NF
SFDR = 2/3(FOM – P0)
P0 = –174dBm + 10Log10(BW|Hz)
5584f
26
RF INPUT
800MHz
TO
1000MHz
C1
0.01µF
C5
100pF L2
33nH
C3
4.7µF
R1
0Ω
C2
0.01µF
LO INPUT
881MHz
6dBm
C25
0.01µF
C24
0.01µF
5V
200mA
6
1 2
RF–
LO+
RF+
L7 180nH
L8 180nH
C13
150pF
L5 470nH
L6 470nH
C12
47pF
T1
MINI-CIRCUITS
TC1-1-13M+
C10
0.01µF
C14
150pF
C9
47pF
C17
1µF
C15
150pF
C16
150pF
R4
110Ω
40MHz LOWPASS FILTER
C18
0.1µF
R7
20Ω
R6
20Ω
R5
110Ω
R8
402Ω
C20
0.5pF
+ –
R9
402Ω
VOCN LTC6409
– +
5V
52mA
C19
0.5pF
L9 270nH
R15
27.4Ω
R10
100Ω
R13
243Ω
R16
27.4Ω
R11
36.5Ω L10 270nH
R12
36.5Ω
R14
243Ω
R18
86.6Ω
C22
39pF
L12 180nH
L11 180nH
C21
39pF
R17
86.6Ω
40MHz ANTI-ALIAS FILTER
Figure 33. Simplified Schematic of 900MHz Receiver, (Only I-Channel Is Shown)
4
3
I–
LO–
VCC
+
LTC5584 I
C8
2.2pF
C11
0.01µF
C7
1.5pF
L3 5.6nH
C4
33pF
C6
4.7µF
L4 3.9nH
L2
33nH
T2
MINI-CIRCUITS
TC1-1-13M+
6 •
• 1
2
4
3
LNA
BIAS
AVAGO
MGA-633P8
R3
10Ω
5V
48mA
•
•
R2
5.6k
5585 F33
R19
150Ω
R20
150Ω
C23
1µF
AIN–
VCM
AIN+
CONTROL
LTC2185
ADC
VDD
1.8V
206mA
D13
•
•
•
D0
LTC5584
Applications Information
5584f
27
LTC5584
Applications Information
900MHz Receiver Chain Analysis
G = 34.2dB
NF = 1.7dB
IIP3 = 7dBm
FOM = 5.3dB
MGA-633P8
G = 18dB
NF = 0.37dB
OIP3 = 37dBm
G = 16.2dB
NF = 14.2dB
IIP3 = 25.5dBm
FOM = 11.3dB
G = 16.5dB
NF = 11.8dB
IIP3 = 28.6dBm
FOM = 16.8dB
LTC5584
40MHz LPF
G = –0.3dB
NF = 10.4dB
IIP3 = 27.9dBm
G = –0.3dB
NF = 0.3dB
G = 16.8dB
NF = 11.5dB
IIP3 = 28.3dBm
FOM = 16.8dB
LTC6409
G = –1.2dB
NF = 24.3dB
IIP3 = 48.7dBm
FOM = 24.4dB
40MHz AAF
G = 18dB
NF = 10dB
OIP3 = 50dBm
G = –1.2dB
NF = 1.2dB
G = 0dB
NF = 23.1dB
IIP3 = 47.5dBm
FOM = 24.4dB
LTC2185
G = 0dB
NF = 23.1dB
IP3 = 47.5dBm
5584 F34
Figure 34. 900MHz Receiver Chain Analysis
20
TC = 25°C
10
0
GAIN (dB)
–10
–20
–30
–40
–50
–60
–70
–80
0
20
40
60 80 100 120 140 160
5584 F35
FREQUENCY (MHz)
Figure 35. Baseband Gain Response without LNA
Figure 36. fRF = 889MHz and 890MHz 2-Tone Receiver Test, fLO = 881MHz.
Ch.1 Is the I Channel and Ch.2 Is the Q Channel. Tested without LNA
28
5584f
LTC5584
Appendix
Chebychev Filter Synthesis with Unequal
Terminations
To synthesize Chebychev filters with unequal terminations,
two equally terminated filters are synthesized at the two
different impedance levels and the resulting networks are
joined using the Impedance Bisection Theorem[1]. This
method only works with symmetrical odd-order filters. The
general lowpass prototype element values are generated
by the method shown [2]:
L | 

β =In coth Ar dB 
17.37 

β
γ = sinh  
 2n 
ak = sin
π ( 2k – 1)
, k = 1,2,...,n
2n
2
2 πk
b
=
γ
+
sin
, k = 1,2,...,n
k
n
where LAr|dB is the passband ripple in dB, and n is the
filter order.
The prototype element values will be:
g1 =
gk =
2a 1
γ
4a k a k–1
b k−1g k−1
, k = 1,2,...,n
where RIN is the input impedance and the terminating
impedance ROUT is equal to RIN for the n odd case but is
scaled by the gn+1 prototype value for the n even case.
The Impedance Bisection Theorem can be applied to symmetrical networks by dividing the element values along
the networks’ plane of symmetry, and then adding the
two networks together. The filter response is preserved.
For example, if LAr|dB = 0.2dB, fC = 40MHz, RIN = 100Ω,
ROUT = 20Ω and n = 5, the prototype element values and
resulting scaled filter values are listed:
Filter 1: RIN = ROUT = 100Ω
g1 = 1.339 → C1 = 53.3pF
g2 = 1.337 → L1 = 531.98nH
g3 = 2.166 → C2 = 86.19pF
g4 = 1.337 → L2 = 531.98nH
g5 = 1.339 → C3 = 53.3pF
Filter 2: RIN = ROUT = 20Ω
g1 = 1.339 → C1 = 266.48pF
g2 = 1.337 → L1 = 106.4nH
g3 = 2.166 → C2 = 430.93pF
g4 = 1.337 → L2 = 106.4nH
g5 = 1.339 → C3 = 266.48pF
The Impedance Bisection Theorem can be applied at the
plane of symmetry about C2 such that a new value of C2
can be computed with half the values of the two filters.
g n+1 = 1 for n odd
β
g n+1 = coth   for n even
 4
2
Assuming the first element is a capacitor, we can scale the
filter capacitor prototype values up to our desired cutoff
frequency fC:
Ck =
gk
, k = 1,3,...,n
2π • fC •RIN
The filter inductor values can be scaled with:
LK =
gk •RIN
, k = 2,4,...,n
2π • fC
C2→
86.19pF 430.93pF
+
= 258.56pF
2
2
The final unequally-terminated filter design values are
shown in Figure 37.
[1] A.C. Bartlett, “An Extension of a Property of Artificial Lines,” Phil. Mag., vol.4, p.902,
November 1927.
[2] G. Matthaei, L. Young, and E.M.T. Jones, Microwave Filters, Impedance-Matching Networks,
and Coupling Structures, p.99, 1964.
RIN
100Ω
+
–
L1
531.98nH
C1
53.3pF
L2
106.4nH
C2
258.56pF
C3
266.48pF
ROUT
20Ω
5585 F37
Figure 37. Final Design Schematic
5584f
29
LTC5584
Appendix
Image Rejection Calculation
The image rejection ratio (IRR) can then be written as:
Image rejection can be calculated from the measured gain
and phase error responses of the demodulator. Consider
the signal diagram of Figure 38:
where:
Written in terms of AERR and φERR as:
RF(t) = sin(ωLO + ωBB)t + sin(ωLO – ωIM)t
IRR|dB = 10log
IRR|dB = 10log
|desired|2
|image|2
|1+ AERR 2 + 2AERR cos ( φERR ) |
|1+ AERR 2 − 2AERR cos ( φERR ) |
LOI(t) = cos(ωLOt + φERR)
LOQ(t) = sin(ωLOt)
Figure 39 shows image rejection as a function of amplitude
and phase errors for a demodulator.
ωLO + ωBB is the desired sideband frequency and
ωLO – ωIM is the image frequency. The total phase error
of the I and Q channels is lumped into the I-channel LO
source as φERR. The total gain error is represented by
AERR, and is lumped into a gain multiplier in the I-channel.
AERR
LOQ(t)
AERR
sin ( ω BB t – φERR ) – sin ( ωIM t + φERR ) 
2 
1
Q(t) = cos ( ω BB t ) + cos ( ωIM t ) 
2
Shifting the Q channel by –90° can be accomplished by
replacing sine with cosine such that the shifted Q-channel
signal is:
1
Q –90 (t) = sin ( ω BB t ) + sin ( ωIM t ) 
2
We combine I(t) + Q–90(t) and choose terms containing
ωBB as the desired signal:
1
A
desired = sin ( ω BB t ) + ERR sin ( ω BB t – φERR )
2
2
Similarly, we choose terms containing ωIM as the image
signal:
Q(t)
5585 F38
Figure 38. Signal Diagram for a Demodulator
70
AERR = 0dB
AERR = 0.05dB
AERR = 0.1dB
AERR = 0.2dB
AERR = 0.3dB
AERR = 0.5dB
AERR = 1dB
60
IMAGE REJECTION (dB)
I(t) =
LOI(t)
RF(t)
After lowpass filtering the I and Q signals can be written as:
I(t)
50
40
30
20
10
0
1
2
3 4 5 6 7
PHASE ERROR (DEG)
8
9
10
5585 F39
Figure 39. Image Rejection as a Function of Gain and Phase Errors
1
A
image = sin ( ωIM t ) – ERR sin ( ωIM t + φERR )
2
2
5584f
30
LTC5584
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697 Rev B)
0.70 ±0.05
4.50 ±0.05
2.45 ±0.05
3.10 ±0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
4.00 ±0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
0.75 ±0.05
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
23 24
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
1
2
2.45 ±0.10
(4-SIDES)
(UF24) QFN 0105 REV B
0.200 REF
0.00 – 0.05
0.25 ±0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
5584f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC5584
Typical Application
Simplified Schematic of 900MHz Receiver, (Only I-Channel Is Shown)
RF INPUT
800MHz
TO
1000MHz
C2
0.01µF
L3
5.6nH
C7
1.5pF
T2
MINI-CIRCUITS
TC1-1-13M+
6 •
• 1
2
4
3
C17
1µF
5V
200mA
C24
0.01µF
C9
47pF
VCC
+
LTC5584 I
RF+
RF–
LO+
I–
LO–
C25
0.01µF
C11
0.01µF
C14
150pF
C16
150pF
L5 470nH
L7 180nH
L6 470nH
L8 180nH
C12
47pF
C13
150pF
R6
20Ω
R7
20Ω
C15
150pF
40MHz ANTI-ALIAS FILTER (AAF)
R8
402Ω
R5
110Ω
5V
52mA
VOCM LTC6409
+ –
C18
0.1µF
•
R14
243Ω
R12
36.5Ω
– +
R9
402Ω
C20
0.5pF
R15
27.4Ω
L9 270nH
R11
36.5Ω L10 270nH
R16
27.4Ω
R13
243Ω
R10
100Ω
3
R17
86.6Ω
1.8V
206mA
C21
39pF
AIN+
L11 180nH
VCM
L12 180nH
C22
39pF
R19
150Ω
AIN–
R20
150Ω
C23
1µF
R18
86.6Ω
VDD
LTC2185
ADC
D13
•
•
•
D0
CONTROL
5584 TA02
T1
MINI-CIRCUITS
TC1-1-13M+
•
L4 3.9nH
R4
110Ω
C10
0.01µF
1 2
LO INPUT
900MHz
6dBm
C19
0.5pF
40MHz LOWPASS FILTER
6
4
C8
2.2pF
Related Parts
PART
NUMBER
Infrastructure
LTC5569
LT5527
LT5557
LTC6409
LTC6412
LTC554X
LT5554
LTC5585
DESCRIPTION
COMMENTS
300MHz to 4GHz Dual Active Downconverting Mixer
400MHz to 3.7GHz, 5V Downconverting Mixer
400MHz to 3.8GHz, 3.3V Downconverting Mixer
10GHz GBW Differential Amplifier
31dB Linear Analog VGA
600MHz to 4GHz Downconverting Mixer Family
Ultralow Distortion IF Digital VGA
700MHz to 3GHz IQ Demodulator
2dB Gain, 26.7dBm IIP3 and 11.7dB NF at 1950MHz, 3.3V/180mA Supply
2.3dB Gain, 23.5dBm IIP3 and 12.5dB NF at 1900MHz, 5V/78mA Supply
2.9dB Gain, 24.7dBm IIP3 and 11.7dB NF at 1950MHz, 3.3V/82mA Supply
DC-Coupled, 48dBm OIP3 at 140MHz, 1.1nV/√Hz Input Noise Density
35dBm OIP3 at 240MHz, Continuous Gain Range –14dB to 17dB
8dB Gain, >25dBm IIP3, 10dB NF, 3.3V/200mA Supply
48dBm OIP3 at 200MHz, 2dB to 18dB Gain Range, 0.125dB Gain Steps
>530MHz IQ Bandwidth, 25.7dBm IIP3, IIP2 Adjustable to >80dBm, DC Offset Null
Adjustment
8.7dB Gain, 26dBm IIP3, 9.7dB Noise Figure
8.5dB Gain, 26.2dBm IIP3, 9.9dB Noise Figure
8.3dB Gain, 27.3dBm IIP3, 9.8dB Noise Figure
LTC5590
Dual 600MHz to 1.7GHz Downconverting Mixer
LTC5591
Dual 1.3GHz to 2.3GHz Downconverting Mixer
LTC5592
Dual 1.6GHz to 2.7GHz Downconverting Mixer
RF PLL/Synthesizer with VCO
LTC6946-1
Low Noise, Low Spurious Integer-N PLL with
Integrated VCO
LTC6946-2
Low Noise, Low Spurious Integer-N PLL with
Integrated VCO
LTC6946-3
Low Noise, Low Spurious Integer-N PLL with
Integrated VCO
ADCs
LTC2145-14 14-Bit, 125Msps 1.8V Dual ADC
LTC2185
16-Bit, 125Msps 1.8V Dual ADC
LTC2158-14 14-Bit, 310Msps 1.8V Dual ADC, 1.25GHz Full-Power
Bandwidth
373MHz to 3.74GHz, –157dBc/Hz WB Phase Noise Floor, –100dBc/Hz Closed-Loop
Phase Noise
513MHz to 4.9GHz, –157dBc/Hz WB Phase Noise Floor, –100dBc/Hz Closed-Loop
Phase Noise
640MHz to 5.79GHz, –157dBc/Hz WB Phase Noise Floor, –100dBc/Hz Closed-Loop
Phase Noise
73.1dB SNR, 90dB SFDR, 95mW/Ch Power Consumption
76.8dB SNR, 90dB SFDR, 185mW/Channel Power Consumption
68.8dBFS SNR, 88dB SFDR, 362mW/Ch Power Consumption, 1.32VP-P Input
Range
5584f
32 Linear Technology Corporation
LT 0412 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2012