Download MOS Inverters: Switching Characteristics and Interconnect Effects

CMOS
Digital Integrated
Circuits
Analysis and Design
Chapter 6
MOS Inverters: Switching
Characteristics and
Interconnect Effects
1
Introduction
•
The parasitic capacitance
associated with MOSFET
– Cgd, Cgs, gate overlap with diffusion
– Cdb, Csb, voltage dependant junction
capacitance
– Cg, the thin-oxide capacitance over
the gate area
– Cint, the limped interconnect
capacitance
– Load capacitance Cload= Cgd,n + Cgd,p
+ Cdb,n + Cdb,p + Cint + Cg
• Csb,n and Csb,p have no effect on the
transient behavior of the circuit,
since VSB=0
• The delay times calculated using
Cload may slightly overestimate the
actual inverter delay
– Charging, discharging
2
Delay-time definitions
V 50% = VOL + 1 / 2(VOH − VOL) = 1/ 2(VOH + VOL)
τPHL = t1 − t 0
τPLH = t 3 − t 2
τPHL + τPLH
τP =
2
V 10% = VOL + 0.1⋅ (VOH − VOL)
V 90% = VOL + 0.9 ⋅ (VOH − VOL)
τ fall = tB − tA
τ rise = tD − tC
3
Calculation of delay time
• The simplest approach for calculating the
propagation delay times τPHL and τPLH
– Estimating the average capacitance current during
charge down and charge up
– τPHL = Cload ⋅ ∆VHL = Cload ⋅ (VOH − V 50%)
Iavg , HL
Iavg , HL
Cload ⋅ ∆VLH Cload ⋅ (V 50% − VOL)
τPLH =
=
Iavg , LH
Iavg , LH
1
Iavg , HL = [iC (Vin = VOH ,Vout = VOH ) + iC (Vin = VOH ,Vout = V 50%)
2
1
Iavg , LH = [iC (Vin = VOL,Vout = V 50%) + iC (Vin = VOL,Vout = VOL)]
2
– Not very accurate estimate of the delay time
4
Calculation of delay time(1)
•
The propagation delay times can be found more accurately by solving the state equation
of the output node in the time domain
dVout
= iC = iD , p − iD ,n
dt
First, we consider t he resing - input case for a CMOS inverter
the nMOS on ⇒ starting to discharge, pMOS off
Cload
dVout
= −iD,n
dt
k
k
2
2
iD , n = n (Vin − VT ,n ) = n (VOH − VT , n ) for VOH -VT,n < Vout ≤ VOH
2
2
t = t1'
Vout =VOH −VT ,n ⎛ 1 ⎞
Vout =VOH −VT ,n
2C
dVout
2 ∫V =V
∫t =t0 dt = −Cload ∫Vout =VOH ⎜⎜ iD ,n ⎟⎟dVout = − k n (VOH load
out
OH
)
V
−
T ,n
⎝
⎠
2C load VT , n
⇒ t1' − t 0 =
2
k n (VOH − VT ,n )
iD,p ≈ 0 , C load
At t = t1' , the output vol tage is (V DD -VT,n ) and the transisto r will be
at the saturation - linear region boundary. Considerin g nMOS linear
k
k
2
2
iD,n = n 2(Vin −V T,n )Vout − Vout
forV out ≤ VOH − VT,n
= n 2(VOH −V T,n )Vout − Vout
2
2
t =t 1
Vout =V 50%
Vout =V 50%
1
1
∫t =t1′ dt = −Cload ∫Vout =VOH −VT ,n ( iD , n )dVout = −2Cload ∫Vout =VOH −VT ,n ( kn[2(VOH − VT , n)Vout − Vout 2 ] )dVou
[
]
[
Vout
2C load
1
ln(
)
kn 2(VOH − VT , n ) 2(VOH − VT , n ) − Vout
C load
2(VOH − VT , n ) − V 50%
t 1 − t 1′ =
ln(
kn (VOH − VT , n )
V 50%
C load
2VT , n
4(VOH − VT , n )
τPHL =
+ ln(
− 1)
[
kn (VOH − VT , n ) VOH − VT , n
VOH + VOL
C load
2VT , n
4(VDD − VT , n )
τPHL =
[
+ ln(
− 1)]
kn (VDD − VT , n ) VDD − VT , n
VDD
]
t 1 − t 1′ = −
5
Example 6.1
6
Example 6.2
7
Calculation of delay time (2)
In a CMOS inverter, the charge - up event of the output load capacitanc e for falling
input tran sition is completely analogous to the charge - down event for rising input
τPLH =
τPLH =
kp (V OH
⎡
2 VT , P
C load
⎛ 2 (V OH − V OL − | V T , p |) ⎞ ⎤
×⎢
+ ln ⎜
⎟ − 1⎥
− V OL − | V T , p |) ⎣ V OH − V OL − | V T , p |
V OH − V 50 %
⎝
⎠ ⎦
⎡
VT , P
C load
⎛ 4 (V DD − | V T , p |) ⎞ ⎤
×⎢
+ ln ⎜
⎟ − 1⎥
kp (V DD − | V T , p |) ⎣ V DD − | V T , p |
V DD
⎝
⎠ ⎦
the sufficient conditions for balanced propagatio n delays, i.e. for τ PHL = τ PLH
⇒ VT,n = VT,p and k n = k p (or W p /W n = µ n /µ p )
When the input volt age switches from high to low, nMOS off, pMOS on charging load
dV out
= iD , load (V out ), note the pMOS initially in saturation , and enter linear
dt
when the output vol tage is rises above (V DD + VT,load )
C load
k n , load
(| V T , load |) for Vout ≤ V DD - VT,load
2
k n , load
2 | V T , load | (V DD − V out ) − (V DD − V out ) 2 for V out > V DD − | V T , load |
iD , load =
2
⎡ V out =V DD −|V T ,load | ⎛ dV out ⎞ V out =V 50 %
⎛
⎞⎤
dV out
⎜⎜
⎟⎟ + ∫
⎜⎜
⎟
τPLH = C load ⎢ ∫
V out =V DD −|V T ,load | ⎝ iD , load (linear ) ⎟⎠ ⎥
V out =V OL
D , load ( sat ) ⎠
i
⎝
⎣
⎦
⎡ 2 (V DD − | VT , load | −V OL )
C load
⎛ 2 | V T , load | − (V DD − V 50 % ) ⎞ ⎤
+ ln ⎜
τPLH =
⎟⎥
⎢
| V T , load |
kn , load | V T , load | ⎣
V DD − V 50 %
⎝
⎠⎦
iD , load =
[
τPHL ( actual ) = τPHL
]
2
τPLH ( actual ) = τPLH
⎛ τr ⎞
( stepinput ) + ⎜ ⎟
⎝2⎠
2
2
⎛ τf ⎞
( stepinput ) + ⎜ ⎟
⎝2⎠
2
8
Calculation of delay time (3)
• Considering the input voltage waveform is not an ideal
(step) pulse waveform, but has finite rise and fall times
– Using an empirical expression as 6.29, 6.30
• The former expression based on the gradual channel
approximation
– Can still be used for sub-micron MOS transistors with proper
parameter adjustments
– Yet , the current driving capability of sub-micron transistors is
significantly reduced as a result of channel velocity saturation
• (W/L)-ratio
• In deep-sub-micron nMOS Bsaturation current no longer∝(VGS-VT)2
– Isat=κWn(VGS-VT)
– τPHL≈(CloadV50%)/Isat=[Cload(VDD/2)]/ κWn(VGS-VT)
– The propagation delay has only a weak dependence od the power
supply
– Better estimate can be obtain by using an accurate shortchannel MOSFET model
9
Inverter design with delay constrains
•
The load capacitance Cload consist of
– Intrinsic components B parasitic drain capacitances which depend on transistor
dimensions
– Extrinsic component B interconnect/wiring capacitance and fan-out capacitance
•
If Cload mainly consists of extrinsic components, and if this overall load
capacitance can be estimated accurately and independently of the transistor
dimensions
– Given a required (target) delay value of τ*PHL
– The (W/L)-ratio can be found as
⎡ 2VT , n
Cload
⎛ Wn ⎞
⎛ 4(VDD − VT , n) ⎞⎤
+
− 1⎟⎥
ln
⎜ ⎟=
⎜
⎢VDD − VT , n
∗
n
DD
L
V
−
PHL
n
ox
DD
T
n
(
)
C
V
V
,
τ
µ
⎝ ⎠
⎝
⎠⎦
⎣
⎡ 2 | VT , p |
Cload
⎛ Wp ⎞
⎛ 4(VDD − | VT , p |) ⎞⎤
+
− 1⎟ ⎥
ln
⎜ ⎟=
⎜
⎢
∗
VDD
⎝
⎠⎦
⎝ Lp ⎠ τPLH µpCox (VDD − VT , p ) ⎣VDD − | VT , p |
10
Example 6.3
11
Inverter design with delay constrains
If Cload have to take into accunt that the intrinsic component
Cload = Cgd , n(Wn) + Cgd , p (Wp ) + Cdb , n(Wn) + Cdb , p (Wp ) + C int + Cg = f (Wn, Wp )
the fan - out capacotance C g is also a function of the device dimensions in the next - stage gates
Condering the simplified layout in Fig. 6.8 ⇒
The relatively small gate - to - drain capacitances C gd,n and C gd,p will be neglected in the analysis
The drain parasitic capacitance are :
Cdb , n = WnDdrainCj 0, nKeq , n + 2(Wn + Ddrain )Cjsw, nKeq , n
Cdb , p = WpDdrainCj 0, pKeq , p + 2(Wp + Ddrain )Cjsw, pKeq , p
Cload = (WnCj 0, nKeq , n + WpCj 0, pKeq , p ) Ddrain + 2(Wn + Ddrain )Cjsw, nKeq , n + 2(Wp + Ddrain )Cjsw, pKeq , p + Cint + Cg
The total capacitive load can be expressed as :
Cload = α 0 + αnWn + αpWp
where α 0 = 2 Ddrain (Cjsw, nKeq , n + Cjsw, pKeq , p ) + C int + Cg
αn = Keq , n(Cj 0, nDdrain + 2Cjsw, n)
αp = Keq , p (Cj 0, pDdrain + 2Cjsw, p )
12
Inverter design with delay constrains
The propagatio n delay :
⎞ ⎡ 2VT , n
Ln
⎛ α 0 + α n W n + α pW p ⎞ ⎛
⎛ 4(V DD − VT , n ) ⎞ ⎤
⎟⎟ × ⎢
+ ln ⎜
− 1⎟ ⎥
⎟ × ⎜⎜
Wn
VDD
⎝
⎠ ⎝ µnC ox (VDD − VT , n ) ⎠ ⎣VDD + VT , n
⎝
⎠⎦
τPHL = ⎜
⎞ ⎡ 2 | VT , p |
Lp
⎛ α 0 + α nW n + α pW p ⎞ ⎛
⎛ 4(VDD − | VT , p |) ⎞ ⎤
⎟⎟ × ⎢
+ ln ⎜
− 1⎟ ⎥
⎟ × ⎜⎜
Wn
VDD
⎝
⎠ ⎝ µpC ox (VDD − | VT , p |) ⎠ ⎣ VDD − | VT , p |
⎝
⎠⎦
Note that the channel lengths Ln and L p are usually fixed and equal to each other
τPLH = ⎜
the transisto r aspect rat io be defined as : R(aspect r atio) ≡
⎛ α 0 + (α n + Rα p )W n ⎞
⎟, τPLH
Wn
⎝
⎠
τPHL = Γ n⎜
Wp
Wn
αn
⎛
⎞
⎜ α 0 + ( + α p )W p ⎟
R
⎟
= Γp⎜
Wp
⎟
⎜
⎟
⎜
⎝
⎠
⎛
⎞ ⎡ 2VT , n
Ln
⎛ 4(VDD − VT , n ) ⎞ ⎤
⎟⎟ × ⎢
+ ln ⎜
− 1⎟ ⎥
where Γ n = ⎜⎜
VDD
⎝
⎠⎦
⎝ µnC ox (VDD − VT , n ) ⎠ ⎣VDD − VT , n
⎛
⎞ ⎡ 2 | VT , P |
Lp
⎛ 4(VDD − | VT , P |) ⎞ ⎤
⎟⎟ × ⎢
Γ p = ⎜⎜
+ ln ⎜
− 1⎟ ⎥
VDD
⎝
⎠⎦
⎝ µpC ox (VDD − | VT , p |) ⎠ ⎣ VDD − | VT , p |
*
*
Given targ et delay valu e τ PHL and τ PLH the minimum channel widths of the nMOS transisto r and the pMOS transisto r which
satisfy th ese delay constraint s can be calculated from (6.46a) and (6.46b), by solving for Wn and W p , respective ly.
Increasing Wn and Wp to reduce the propagatio n delay time s will have a dimishing influence upon delay beyond certain va lues,
⎛α
⎞
limit
limit
= Γ n (α n + Rα p ), τ PLH
= Γ p⎜ n + αp ⎟
τ PHL
⎝ R
⎠
The propagatio n delay can not be reduced beyond these limit valu es, which are dictated by technol ogy - related parameters .
The propagatio n delay time is independen t of the extrinsic capacitanc e component, C int and C g
13
Example 6.4
14
Example 6.4
15
CMOS ring oscillator circuit
•
•
This circuit does not have a stable operating point
The only DC operating point:
–
•
the input and output voltages of all inverters are equal to the logic threshold Vth
(unstable)
A closed-loop cascade connection of any odd number of inverter will display
astable behavior
– will oscillate once any of the inverter input or output voltages deviate from the
unstable operating point, Vth
– V1, VOL→VOH B trigger V2 to fall, VOH→VOL, difference between the V50%crossing times of V1 and V2, τPHL2 B trigger V3 to rise, VOL→VOH, difference
between the V50%-crossing times of V2 and V3, τPHL3......
– T= τPHL1+ τPHL1+τPHL2+ τPHL2+τPHL3+ τPHL3 =6τP
– f=1/T=1/(2nτP), τP=1/2nf
16
Estimation of interconnect parasitics
•
The load
– Classical approach
Bcapacitive and lumped
• Internal parasitic capacitance
of the transistor
• Interconnect (line)
capacitances
• Input capacitances of the fanout gates
•
Now, the interconnect line
itself
– Three dimensional structure in
metal and/or polysilicon
• Non-negligible resistance
• The (length/width) ratio of the
wire B distributed B making
the interconnect a true
transmission line
• An interconnect is rarely
isolated from other influence
17
Estimation of interconnect parasitics
•
If the time of flight across the interconnection line
is much shorter than the signal rise/fall times
–
•
The wire can be modeled as a capacitive load, or
as a lumped or distributed RC network
If the interconnection lines are sufficient long and
the rise times of the signal comparable to …
–
–
–
The inductance becomes important
Modeled as transmission lines
⎛l⎞
⎝v⎠
τ rise (τ fall ) < 2.5 × ⎜ ⎟
⇒ {transmission − line modeling}
⎛l⎞
⎛ l ⎞ ⎧either transmission - line⎫
2.5 × ⎜ ⎟ < τ rise (τ fall ) < 5 × ⎜ ⎟ ⇒ ⎨
⎬
⎝v⎠
⎝ v ⎠ ⎩or lumped modeling
⎭
⎛l⎞
⇒ { lumped modeling}
⎝v⎠
Here, l is the interconnect line length, and v is the propagation speed
τ rise (τ fall ) > 5 × ⎜ ⎟
–
–
The longest wire on a VLSI chip (2cm)Öfright
time≅133ps, shorter than rise/fall timeÖ capacitive
or RC model
10 cm multi-chip module Ö1ns, the same order as
rise/fall time Öconsidering RLCG
18
The transmission line effect
•
IN CMOS VLSI chips
– Not serious concern
– The gate delay due to capacitive load component dominated the line delay
•
The sub-micron design rules
– The intrinsic gate delay tend to decrease significantly
– The overall chip size and the worse-case line length on a chip tend to increase
• Mainly due to increasing chip complexity
• The widths of metal lines shrink while thickness increase
– The transmission line effects and signal coupling between neighboring lines become even more
pronounced
•
To optimize a system for speed, chip designer must have reliable and
efficient means for
– Estimating the interconnect parasitics in a large chip
– Simulating the transient effect
19
Interconnection delay
• The hierarchical structure of most VLSI design
– Chip
– Modules
• Inter-module connection B longer
– Logic gates, transistors
• Intra-module connection Bshorter
20
Interconnect capacitance estimation
•
•
A complicated task
Fringing-field factor FF=Ctotal/Cpp
21
Estimation of interconnection capacitance
• The formulas provide accurate approximation of the
parasitic capacitance values to within 10% error, even
for very small values of (w/h) and (t/h)
– The linear dash-dotted line Bparallel-plate cap.
– W/T decreases Bcap. Decreases
• Level off at approximately 1pF/cm, when the wire width is
approximately equal to insulator thickness
⎤
⎡
t
⎛
⎞
⎥
⎢⎜ w − ⎟
2π
t
⎥
⎢
2⎠
C = ε ⎢⎝
+
for w ≥
⎥
h
2
⎛ 2h
2h ⎛ 2h
⎞ ⎞⎟ ⎥
⎢
⎜
ln 1 +
+
⎜ + 2⎟ ⎟
⎜
⎢
t
t
⎝ t
⎠ ⎠ ⎥⎦
⎝
⎣
⎤
⎡
t
⎛
⎞
⎥
⎢
π ⎜1 − 0.0543 ⋅ ⎟
t
⎥
⎢w
2h ⎠
⎝
C =ε⎢ +
+ 1.47 ⎥ for w <
h
2
⎛ 2h
2h ⎛ 2h
⎞ ⎞⎟
⎥
⎢
⎜
ln 1 +
+
⎜ + 2⎟ ⎟
⎜
⎥
⎢
t
t
⎝ t
⎠⎠
⎝
⎦
⎣
22
Capacitance coupling
• Considering the
interconnection line is not
completely isolated from
the surrounding
structures, but is coupled
with other lines running in
parallel
– The total parasitic
capacitance increased by
• Fringing-field effects
• Capacitive coupling
between the lines
– When the thickness of
the wire is comparable
to its width B coupling
capacitance↑
– Signal crosstalk
» Transitions in one
line can cause
noise in the other
lines
23
Capacitance of an interconnect line
•
The capacitance of a line which is coupled with two other lines on
both sides
– If both of the neighboring lines are biased at ground potential
– The total parasitic capacitance can be more than 20 times as large as the
simple parallel-plate capacitance
24
Capacitance between various layers
25
Interconnect resistance estimation
• The total resistance
l
⎛l ⎞
= Rsheet ⎜ ⎟
w⋅t
⎝ w⎠
Rsheet : the sheet resistivity of the line (Ω/square)
– Rwire = ρ ⋅
Rsheet =
ρ
t
– The sheet resistivity
•
•
•
•
•
Polysilicon: 20-40 Ω/square
Silicided ploysilicon: 2-4 Ω/square
Aluminum: 0.1 Ω/square
Metal-poly, metal-diffusion contact: 20-30 Ω
Via resistance: 0.3 Ω
• We can estimate the total parasistic resistance of a wire
segment based on its geometry
– Short distance Önegligible
– Long distance Öthe total lumped resistance connect in series
with the total lumped capacitance
26
Calculation of interconnect delay- RC delay models
•
If the time of flight across the
interconnect line is significant shorter
than the signal rise/fall times
– Can be modeled as a lumped RC
network
– Assuming that the capacitance is
discharged initially, and assuming that
the input signal is a rising step pulse
at time t=0
•
⎛
⎛ t ⎞⎞
Vout (t ) = VDD ⎜⎜1 − exp⎜ −
⎟ ⎟⎟
⎝ RC ⎠ ⎠
⎝
The rising output voltage reaches the 50% - point at t = τ PLH
⎛
⎛ τ
⎞⎞
V50% (t ) = VDD ⎜⎜1 − exp⎜ − PLH ⎟ ⎟⎟
⎝ RC ⎠ ⎠
⎝
and the propagation delay for the simple lumped RC network
is found as τ PLH ≈ 0.69 RC
• Unfortunately, this simple lumped RC
network provides a very rough
approximation
• The accuracy of the simple lumped RC
model can be significant improved by
– Dividing the total resistance into two
equal parts
• More accuracy
– RC ladder network
27
Calculation of interconnect delay- The Elmore delay
•
Consider a general RC tree network
– There are no resistor loops in this circuit
– All of the capacitors in an RC tree are connected between a node and a
ground
– There is one input node in the circuit
– There is a unique resistive path, from the input node to any other node
in the circuit
•
Path definitions
– Let Pi denote the unique path from the input node to node i, i=1,2,3..n
– Let Pij=Pi∩Pj denote the portion of the path between the input and the
node i, which is common to the path between the input and node j
28
Calculation of interconnect delay- The Elmore delay
τ D 7 = R1C1 + R1C2 + R1C3 + R1C4 + R1C5 + (R1 + R6 )C6 + (R1 + R6 + R7 )C7 + (R1 + R6 + R7 )C8
τ D 5 = R1C1 + (R1 + R2 )C2 + (R1 + R2 )C3 + (R1 + R2 + R4 )C4 + (R1 + R2 + R4 + R5 )C5 + R1C6 + R1C7 + R1C8
A specific case of the general RC tree network ⇒ simple RC ladder network
N
j
j =1
k =1
τ DN = ∑ C j ∑ Rk
If assume a uniform RC ladder network, consisting of identical element (R/N) and (C/N)
C j R ⎛ C ⎞⎛ R ⎞ N ( N + 1)
N +1
τ DN = ∑ ∑ = ⎜ ⎟⎜ ⎟
= RC
2
2N
⎝ N ⎠⎝ N ⎠
j =1 N k =1 N
RC
for N → ∞
τ DN =
2
Thus, we see that the propagation delay of a distributed RC line is considerable smaller than that of a lumped RC network
N
29
Example 5
30
Example 5
31
Switching power dissipation of CMOS inverters
1 T
v(t ) ⋅ i (t )dt
T ∫0
T
dV ⎞
dV ⎞ ⎤
1⎡ T
⎛
⎛
= ⎢ ∫ 2 Vout ⎜ − Cload out ⎟dt + ∫T (VDD − Vout )⎜ Cload out ⎟dt ⎥
T⎣0
dt ⎠
dt ⎠ ⎦
2
⎝
⎝
T ⎤
V out2 ⎞ T 2 ⎛
1 ⎡⎛⎜
2 ⎞
⎟ + ⎜VDD ⋅Vout ⋅ Cload − 1 CloadVout
= ⎢ − Cload
⎟ ⎥
T ⎢⎜⎝
2 ⎟⎠ 0 ⎝
2
⎠ T 2 ⎥⎦
⎣
1
2
= C loadVDD
T
2
=C load ⋅VDD
⋅f
Pavg =
Pavg
Pavg
Pavg
Pavg
32
Power meter simulation
•
Power meter
– Estimating the average power dissipation of an arbitrary device or circuit
driven by a periodic input, with transient circuit simulation
– Consisting
• A linear-controlled current source
• A capacitor
• A resistor
–
Cy
dV y
dt
= β is −
Vy
Ry
The initial condition of the node voltage V y is aet as V y( 0 ) = 0V
V y (t ) =
⎛ t −τ
⎜−
exp
⎜ RC
C y ∫0
y y
⎝
β
t
⎞
⎟iDD (τ )dτ
⎟
⎠
Assuming R y C y >> T , V y (T ) ≈
If β = VDD
Cy
T
β
Cy
then V y (T ) = VDD ⋅
∫
T
0
iDD (τ )dτ
1 T
iDD (τ )dτ
T ∫0
– The right-hand side of (6.75) corresponds to the average power drawn
from the power supply source over one period
– The value of the node voltage Vy at t=T gives the average power
dissipation
33
Example 6
34
Power-delay product
•
•
•
For measuring the quality and the performance of a CMOS process
and gate design
The average energy required for a gate to switch its output voltage
from low to high and from high to low
PDP=CloadV2DD (6.76)
– Dissipated as heat during switching
– To keep Cload and VDD as low as possible
•
PDP=2P*avgτp
(6.77)
– P*avg is the average switching power dissipation at maximum operating
frequency
– Τp is the average propagation delay
– The factor of 2, accounting two transitions of the output, from low to high
and from high to low
– This result may misleading interpretation that the amount of energy
required per switching event is a function of the operating frequency
(
)
2
PDP = 2 C load V DD
f max τ
⎡
2
= 2 ⎢ C load V DD
⎣
2
= C load V DD
p
⎛
1
⎜⎜
⎝ τ PHL + τ PLH
⎞ ⎤ ⎛ τ PHL + τ PLH ⎞
⎟⎟ ⎥ ⎜
⎟
2
⎝
⎠
⎠⎦
35
Super buffer design (1)
•
Super buffer
– A chain of inverters designed to drive a large capacitive load with minimal signal
propagation delay time
•
A major objective of super buffer design
– Given the load capacitance faced by a logic gate, design a scaled chain of N
inverters such that the delay time between the logic gate and the load
capacitance node is minimized
– The design task is to determine
• The number of stages, N
• The optimal scale factor, α
36
Super buffer design (2)
•
For the super buffer
–
–
–
–
–
Cg: the input capacitance of the first stage inverter
Cd: the chain capacitance of the first stage inverter
The inverters in the chain are scaled up by a factor of α per stage
Cload= αN+1Cg
All inverters have identical delay of τ0(Cd+ αCg)/(Cd+Cg)
• τ0: the per gate delay in the ring oscillator circuit with load capacitance (Cd+Cg)
⎛ C d + αC g ⎞
⎟
⎟
+
C
C
g ⎠
⎝ d
τ total = (N + 1)τ 0 ⎜⎜
⎛C ⎞
ln⎜ load ⎟
⎜ C ⎟
g ⎠
N +1
From Cload = α C g ⇒ ( N + 1) = ⎝
ln α
⎛C ⎞
ln⎜ load ⎟
⎜ C ⎟ ⎛ C + αC ⎞
g ⎠
g
⎟
τ total =& ⎝
τ 0 ⎜⎜ d
⎟
+
ln α
C
C
d
g
⎝
⎠
1
⎡
⎛
⎞
⎛ C d + αC g ⎞
⎛ Cg
⎢
∂τ total
C
⎟+ 1 ⎜
= τ 0 ln⎜ total ⎟ ⎢− α 2 ⎜
⎜ C ⎟ (ln α ) ⎜ C + C ⎟ ln α ⎜ C + C
∂α
g ⎠
g
⎝ g ⎠⎢
⎝ d
⎝ d
⎣
C
the optimal scale factor α (ln α − 1) = d
Cg
⎤
⎞⎥
⎟⎥ = 0
⎟
⎠⎥
⎦
A special case of the above equation occurs when the drain capacitance is neglected; i.e., Cd = 0. In that case, the optimal
scale factor becomes the natural number e = 2.718, However, in reality the drain parasitics cannot be ignored
37