Download ABCs of ADCs

ADC Training
Peter Qian
NSSH FAE
Agenda
•
•
•
•
Review of Definitions
Sources of Distortion and Noise
Common Design Mistakes
ADCs from National Semiconductor
2
Offset Error
111
110
ACTUAL
OUTPUT CODE
101
IDEAL
100
011
010
001
000
1/8
Offset
Error
1/4
3/8
1/2
5/8
3/4
7/8
FS
ANALOG INPUT (V)
3
NCG 9/99
Full-Scale (Offset) Error
ACTUAL
Full-Scale
Error
111
110
OUTPUT CODE
101
IDEAL
100
011
010
001
000
1/8
1/4
3/8
1/2
5/8
3/4
7/8
FS
ANALOG INPUT (V)
4
NCG 9/99
Gain Error (Full-Scale Gain
Error)
Gain Error
111
ACTUAL
110
SHIFTED ACTUAL
OUTPUT CODE
101
100
011
010
001
000
1/8
1/4
3/8
1/2
5/8
3/4
7/8
FS
ANALOG INPUT (V)
5
NCG 9/99
1
Signal-to-Noise and Distortion
(SINAD)
SINAD = -20 * Log
-SNR
10
10
+ 10
THD
10
1
SINAD = 10 * Log
-SNR
10 10
+ 10
THD
10
8
1
ENOB - Effective Number Of
Bits
• ENOB says that the ADC is equivalent to
this (ENOB) number of bits as far as
SINAD is concerned. That is, a converter
with an ENOB of 7.0 has the same SINAD
as a theoretically perfect 7-bit converter.
ENOB =
SINAD - 1.76
6.02
9
Input Dynamic Range
Dynamic Range is the ratio of the largest to the smallest
possible signals that can be resolved. DO NOT confuse
with Spurious Free Dynamic Range (SFDR).
Resolution (Bits)
6
8
10
12
14
16
18
20
Dynamic Range (dB)
36.0
48.1
60.2
72.2
84.3
96.3
108.4
120.4
Dynamic Range = 20 * Log(2n - 1)
10
NCG 9/99
SFDR - Spurious Free
Dynamic Range
0
-10
Signal
-20
-30
65dB SFDR
-40
-50
-60
Highest “Spur”
-70
-80
-90
11
Ideal Case
• THD and SNR curves are linear
• SINAD (and ENOB) maximum at –THD = SNR
75.0
70.0
65.0
60.0
SNR (dB)
-THD (dB)
55.0
SINAD (dB)
50.0
45.0
40.0
-40
-30
-20
-10
0
12
Actual Case
• THD and SNR curves nonlinear near 0 dBFS input
• SINAD (and ENOB) maximum a little below –THD = SNR
75.0
70.0
65.0
60.0
SNR (dB)
-THD (dB)
55.0
SINAD (dB)
50.0
45.0
40.0
-40
-30
-20
-10
0
13
Sources of Noise
and Distortion
Common Sources of Noise and
Distortion
•
•
•
•
•
•
Inadequate Supply Bypassing
Inadequate VA - VDR* Supply Decoupling
Noisy Components/Conditioning Circuitry
Quantization
Clock
Output to Input Coupling
* VDR (or DR VD) is the supply for the output drivers
15
Excessive Clock Jitter (cont’d)
Noise
Amplitude
Jitter
Max Jitter = VIN / (2(n+1)  VFS fIN)
18
3
Jitter Question
Max Jitter = VIN / (2(n+1)  VFS fIN)
?
How much jitter can be allowed in the following
- 8 bit ADC
- VREF = 2 Volts
- ADC Gain = 1
- Maximum input of 1VP-P at 40 MHz
Max Jitter = 2V / (2(8+1)  1V 40,000,000)
Max Jitter = 2V / (512  40,000,000)
Max Jitter = 31.1 ps
19
2
Jitter Question (2)
Max Jitter = VIN / (2(n+1)  VFS fIN)
?
How much jitter can be allowed in the following
- 8 bit ADC
- VREF = 1 Volts
- ADC Gain = 1
- Maximum input of 1VP-P at 40 MHz
Max Jitter = 1V / (2(8+1)  1V 40,000,000)
Max Jitter = 1V / (512  40,000,000)
Max Jitter = 15.5 ps
20
3
Jitter Question (3)
Max Jitter = VIN / (2(n+1)  VFS fIN)
?
How much jitter can be allowed in the following
- 12 bit ADC
- VREF = 2 Volts
- ADC Gain = 1
- Maximum input of 1VP-P at 40 MHz
Max Jitter = 2V / (2(12+1)  1V 40,000,000)
Max Jitter = 2V / (8192  40,000,000)
Max Jitter = 1.9 ps
21
2
Jitter Question (3)
Max Jitter = VIN / (2(n+1)  VFS fIN)
?
How much jitter can be allowed in the following
-12 bit ADC
- VREF = 2 Volts
- ADC Gain = 1
- Maximum input of 1VP-P at 248 MHz
Max Jitter = 2V / (2(12+1)  1V 248,000,000)
Max Jitter = 2V / (8192  248,000,000)
Max Jitter = 0.31 ps !
Allowable Jitter with 0.1VP-P input? 3.1 ps
22
Signal Integrity Problem
• Signals propagate down a line
• Improper termination causes reflections
• Reflections
– Cause signal distortion
– Cause signal radiation
• Distortion
– Leads to a change in timing
– Can lead to timing uncertainty (jitter)
– Jitter causes ADC output noise
23
Reflection Problem
• Signals propagate down a line
• Improper termination causes reflections
and signal distortion.
24
4
When is Termination Needed?
• Simple traces need not be terminated
• Transmission Lines should be terminated
• Trace becomes a transmission line at:
tr
Length >6 x tPR
Where tr is the digital signal rise time
tPR is the signal propagation rate
Typical tPR is about 150ps/inch on board of
FR-4 material
25
Terminating Analog Lines
• Analog signals are complex waveforms
• For single frequencies, traces carrying
analog signals become transmission
lines at
Length
>
-
440
140
=
x
x
A  f
Axf
Where A is the zero-to-peak signal amplitude
f is the signal frequency in MHz
26
2
Question: Is Termination
Needed?
?
An ADC clock Signal has a 2ns rise
time. The PCB is a typical one of FR-4
material. Beyond what line length
should the line be properly terminated?
-9
t
2
x
10
r
=
Length >6 x tPR
6 x 150 x 10-12 /in
3
10
= 2.2 inches (5.6 cm)
Maximum Length =
450
27
Termination Techniques
• Two Types of Termination
– Series – Matches Driver Output to Line
• Rsource + Rseries = ZO
– A.C. – Matches Receiving end to Line
• Series RC to Ground
28
3
Series Termination
• Series Termination: A Series Resistor
– Source Impedance + Resistor = ZO
– Resistor placed close to the source
• Series Terminate When Source to Resistor
Distance :
Length >-
tr
6 x tPR
tPR is approximately 150 ps/inch
or about 59 ps/cm
NOTE: See National Semiconductor’s Application Note
AN-1113 (http://www.national.com/an/AN/AN-1113.pdf)
for controlling line impedance.
29
7
Series Termination Question 1
Develop a Rule of Thumb for the relationship between
maximum line length and digital rise time before a trace
must be treated as a transmission line
tr
>
L = Max Length - 6 x t
PR
?
L = tR / (6 x tPR )
L = tPR / (6 x 150ps/in) = tPR / 900 x 10-12 = tPR / 9 x 10-10
If tPR = 1 ns, then L = 1 x 10-9 / 9 x 10-10 = 10/9 inch per ns
L = 1.1 inch per ns of rise time
Or, for centimeters
L = tPR / (6 x 59ps/cm) = tPR / 354 x 10-12 = tPR / 3.54 x 10-10
If tPR = 1 ns, then L = 10-9 / 3.54 x 10-10 =10/3.54 cm per ns
L = 2.8 cm per ns of rise time
30
7
Series Termination Question
?
An ADC sometimes has bad data at the output. It is noted
that the clock line is 6 inches long and the clock signal
rise time is 2 ns. It is also noted that the ADC data output
lines are 3 inches long and have 3.5 ns rise time. The
data outputs go directly to an ASIC. What is the first thing
you would do to try to solve this problem?
L = Max Length >-
tr
6 x tPR
Check to see if clock or data lines are long enough
to be considered transmission lines:
L = 1.1 inch per ns of rise time
tPR = 2ns, so max line length is 1.1 * 2 = 2.2 inches
At 6 inches, the clock line should be treated as a transmission line.
At 3.5 ns rise time, max length is 1.1 * 3.5 = 3.85 inches,
So the 3 inch output data line length is o.k.
31
2
A.C. Termination
• A.C. Termination: Series RC to Ground
at Destination. Needed for “Rat’s Nest”
–R = ZO
4 x tPR x L
–C:
C >-
ZO
Where L is the line length
ZO is the characteristic impedance of the
line
tPR is the signal propagation rate down a
board trace (about 150ps/inch with FR-4
board material)
32
2
Question (A.C. Termination)
?
A 7 inch long clock line with a 50-Ohm
characteristic impedance needs a.c.
termination on an FR-4 board. What is the
value of the series resistor and the smallest
capacitor that should be used?
R = ZO = 50W
-12 x 7
4
x
t
x
L
4
x
150
x
10
PR
>
>
C >- 84 pF
ZO
50
33
ADC Design
Considerations
Agenda: ADC Design
Considerations
•
•
•
•
The Analog Input
The Voltage Reference
The ADC Clock
The Digital Outputs
35
The Analog Input
3
Inadequate Conditioning
Circuitry
220
220
ADC Input
Input
+
51
4.7k
+5V
What is wrong with this circuit?
2K
430 pF
1) Gain of ~2 (could be unstable)
-5V
2) Possible problem driving
sampling input
37
7
Better Conditioning Circuitry
22
220
47
220
62
22pF
+
Input
ADC Input
47
430
+5V
2K
3.9 nF
-5V
What is overall gain of this circuit?
From Input Divider
Amplifier Gain Circuit
(47/(220+47)) * (220 / (22 * 430)/(22 + 430))
0.176 * 11.51 = 2.026
38
Single-Ended Input to
Differential Input ADC
NOT Preferred Way
Best Way
+VCM
+0.5V
2V
IN+
0V
+VCM
IN+
-0.5V
IN-
IN-
ADC12DL066
ADC12DL066
VCM
VCM can be any voltage from 1V to VA / 2. It is acceptable to use VRM.
NOTE: Performance with a single-ended input signal is not as
good as with a differential input signal !
39
Single-Ended Input to Differential
Input Without a Transformer
Best Solution for d.c. and low frequency applications
IN+
INLMH6550 ADC121S625
VCM
40
12
Single-Ended Customer Issue
VREF = 1.0V. What value of (IN+) – (IN-)
gives code of 000h?
2V
+1V
IN+
0V
Differential Input
IN-
1.0 V
–1V
ADC12DL066 (IN+) – (IN-) = –1V
(IN+) – (IN-) = 0 gives code of 800h
VREF
or 1000 0000 0000 decimal
(IN+) – (IN-) = +1V gives code of FFFh
or 1111 1111 1111 decimal
Actual output
Desired output
What are expected output codes?
– peak = 0.0V
Min code: 800h
+ peak = 1.0V & output clipped > 1V
Max code: FFFh
Is the output as predicted?
What is the problem with this circuit?
YES !
How should the input circuit look for
41
correct conversion results?
1
Recommended Single-Ended
Circuit
VCM
2VP-P
IN+
VCM
IN-
ADC12DL066
Here is a better way to bias the
input circuit, ensuring that the
input common mode voltage is at
the mid-scale voltage of the input
signal.
NOTE: Performance with a single-ended input signal is not as
good as with a differential input signal !
42
1
Recommended Single-Ended
Input Circuit for D.C. Applications
2V
IN+
0V
+1V
1.0 V
IN-
ADC
VREF
NOTE: Performance with a
single-ended input signal is
NOT as good as with a
differential input signal !
43
The Voltage Reference
Ramp with Quiet Reference
45
Ramp with Noisy Reference
46
1
Why Noisy Reference is Worse
at High Input Voltages
From ABCs of ADCs :
Output = 2n x G x AIN / VREF
So, as the input increases so does the
output code and an error in AIN is a
larger error when AIN is larger.
47
Clean Reference and a
Sine Wave
48
Noisy Reference Effect Upon a
Sine Wave
49
Clean Reference and a
Sine Wave – FFT
Note SNR
& Noise
Floor
50
Noisy Reference Effect Upon a
Sine Wave – FFT
Note SNR
& Noise
Floor
51
5
How NOT to Build a Reference
5K
15K
+3V
0.1
+3V
+3V
316
+
0.1
1K
+3V
2N3906
+
5.49K
10K
REFT
0.1
-
178
10K
11K
1.5K
CM
+3V
0.1
178
+3V
+
What is wrong with
this circuit?
0.1
10K
REFB
1K
0.1
10/10V
Too Many Components
Collector in Feedback Path
Too Many Amplifiers
Too many different resistor values
10/10V
2N3904
+
0.1
316
52
13
A Better Reference Circuit
10K
EXTT
+5V
+5V
10uF, 6V
0.1
+5V
0.1
-
82
750
100
2N3904
2K
4.7K
LM4040-4.1
+
750
2K
+5V
0.1
470
+
-V
What is the nominal range of
voltages for EXTT and EXTB?
EXTT min =
1.5K
4.1 * 0.75/(0.75+2+0.75)
= 0.88V
EXTT max =
4.1 * (0.75+2)/(0.75+2+0.75)
1.5K
= 3.22V
100
EXTB min =
2N3906
4.1 * (0.47)/(4.7+2+0.47)
10 uF, 6V
100
0.1
= 0.27V
EXTB max =
10K -V
EXTB
4.1 * (0.47+2)/(4.7+2+0.47)
= 1.41V
53
Keep Reference Quiet!
• Use a Tight Layout
• “Star” Ground for all Components and
Reference Grounds of ADC
• Ground Via Enters Ground at Quiet Point
54
The ADC Clock
2
Clock Noise
•
•
Clock Can Add Noise
Clock Can Be Noisy, Exhibiting Jitter
– For Ideal SNR,
Max Jitter = (VIN/VFS) / (2(n+1)  fIN)
•
Transmission Line
– Clock Line Longer Than tr / (6 * Delay)
Should Be Properly Terminated
What effect does sample rate have on max allowable jitter?
None
56
Effect of Jitter
Sampled with “clean” Clock
Sampled with Jittery Clock
57
The Digital Outputs
4
High Capacitance on
ADC Outputs
At what point is at “ground” potential on the die ?
VDR
Charge
Discharge
CBUS
ADC
RSUB
CIN
Driven Device
So, what does the input see when the
output current is dumped into “ground?
Noise
59
2
Output to Input Coupling
•
Output “Talks” to Input
– Because of Output Capacitance
– Through Substrate
•
Limiting Output Current (with Resistors)
Can Help
How is it that these resistors
V+
help reduce noise?
10uF
10uF
0.1uF
0.1uF
VA
By limiting the current that is
dumped into the substrate.
8 x 47
DR VD
ADC
Latch
60
Watch the Time Constant!
•
•
Reduced Amplitude With Increasing Data
Rate
Difficulty Capturing Data
– Shortened Capture Window
– May Not Cross Logic Threshold
61
Common Design Mistakes
• Inadequate Attention to Noise Minimization
–
–
–
–
–
–
–
–
–
Ignoring PSRR
No Power Decoupling/Bybassing
Noisy Support Components
Excessive Clock Jitter
Treating Clock Line as a Trace
Inadequate Conditioning Circuitry
Inadequate Reference Driver
Inadequate Supply Bypassing
High Capacitance on ADC Outputs
• Overdriving Any Input
62
ADC Layout
Considerations
The Skin Effect
• Current Seeks The Path of Least
Impedance
– Entire Conductor at d.c.
– Very Thin Skin Above a Few MHz
• Inductance Causes Current to Flow on
Skin
• Reduces Conductor Cross Sectional Area
• Increases Resistance
64
2
The Skin Effect: Skin Current
Current flow area
2.6 * K
Skin Depth =
inches
f
1
K= m
r
r
rCU
65
2
Skin Depth vs Frequency
Skin
Depth, %
100.00%
100.00%
100.00%
100.00%
100.00%
64.74%
37.38%
20.47%
11.82%
6.47%
3.74%
2.05%
1.18%
0.65%
120.00%
100.00%
80.00%
60.00%
40.00%
20.00%
0.00%
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Frequency, MHz
Skin Depth vs Frequency for 22 Guage Wire
40.00%
Skin Depth, %
Freq
(MHz)
0.0003
0.001
0.003
0.01
0.03
0.1
0.3
1
3
10
30
100
300
1000
Skin Depth, %
Skin Depth vs Frequency for 22 Guage Wire
30.00%
20.00%
10.00%
0.00%
0
200
400
600
800
1000
1200
Frequency, MHz
66
The Skin Effect: A.C. Resistance
The a.c. resistance of a conductor is much
higher than its d.c.resistance.
Rac =
where
2.61 x 10-7 f x rr
2 x (w + h)
Rac = AC resistance, Ohms/inch
f = frequency, Hz
rr = conductor relative resistivity, compared to copper = 1.00
w = flat trace width in inches
h = flat trace height or thickness in inches
67
A.C. Resistance vs Frequency
A.C. Resistance vs Frequency (Typical PCB Trace)
PCB Trace 0.006"
wide by 0.0015" high
Freq, MHz
0.3
1
3
10
30
100
300
1000
Rac
0.0095304
0.0174
0.0301377
0.0550236
0.0953037
0.174
0.3013768
0.5502363
Resistance, Ohms / Inch
0.6
0.5
0.4
0.3
0.2
0.1
0
0
200
400
600
800
1000
1200
Frequency, MHz
68
5
Question (A.C. Resistance)
?
What is the a.c. resistance in Ohms
per inch at 80 MHz of a typical copper
PCB trace that is 0.006 inch wide and
0.0015 inch thick?
Rac =
Rac =
2.61 x 10-7 f x rr
2 x (w + h)
2.61 x 10-7 80 x 106
0.015
=
=
2.61 x 10-7
80 x 106 x 1
2 x (0.006 + 0.0015)
0.00233
0.015
= 0.1556 Ohms/inch
69
1
Proximity Effect
The Proximity Effect on two conductors
carrying opposite high frequency currents
causes the a.c. current flow in those
nearby conductors to be primarily on the
side of the conductors nearest each other.
Current flow areas
70
3
Proximity Effect on a PCB
Signal Trace
PC Board
H
D
Ground Plane
Current Density
in Ground Plane
IRP =
i
H x  x (1
+(D/H)2
Amps/In
)
where IRP is the reference plane current density at horizontal distance “D” from
the outgoing signal trace
i is the signal current
H is the height of the signal trace above the reference plane
D is the horizontal distance from the edge of the trace.
71
Ground Resistance
ADC Resolution
(Bits)
ADC LSB Size
(uV)
ADC Noise
(LSB/Inch)
ADC Noise for 3 Inch
Trace Length
(LSB)
8
7813
0.07
0.2
10
1953
0.28
0.8
12
488
1.13
3.4
14
122
4.51
13.5
16
31
17.74
53.2
Ground plane resistance of 0.055 Ohms per inch (at 40 MHz)
with an ADC reference voltage of 2.0 Volts can result in
significant ground noise that can affect apparent ADC
performance with only 10mAP-P of 40 MHz ground current.
72
1
Skin Effect + Proximity Effect
Current flows in a small area of
the trace and reference plane.
73
Radiation
• Any Conductor Can
– Radiate
– Pick Up Signals
• Therefore, Any Conductor Can Be An
Antenna
• Greater Loop Area Leads to a Better
Antenna
• A Plane Can Radiate
• Copper With One Point Grounded can
Radiate
74
3
Built in Antenna
Antenna
75
1
Previous Suggestion
ANALOG
GROUND
PLANE
32 31
1
30
DIGITAL
GROUND
PLANE
29
28
27
26 25
24
2
23
3
22
4
21
5
20
High
Power
Digital
Components
Hi-Power Digital
Ground Current Flow
ADC10321CIVT 19
7
18
(TQFP)
6
89
10
11
12
13
14
15 17
16
ADC & Analog Ground
Current Flow
Switching
Power
Supply
76
2
Another Previous Suggestion
Digital
Components
SINGLE, UNIFIED
GROUND PLANE
Digital
Components
USE POWER TRACES,
NOT A PLANE
1
48 47 46 45 44 43 42 41 40 39 38 37
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
11
12
ADC10D040CIVS
(TQFP)
Digital Power Supply
path (blue)
Digital Return current
path (red)
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
ADC Power Supply path
(yellow)
ADC Return current
path (brown)
Power
Supply
77
Recommended ADC
Layout Example
Use a Single, Solid Ground Plane
Green dots are vias to appropriate PWR or GND plane
DIGITAL
POWER PLANE
ANALOG
POWER PLANE
1 V
REF
25
D9
D10
26
D8 24
2 V +
IN
D7 23
3 V IN
D6 22
4 AGND
ADC12020
5 V
A
VDR 21
10
11 12
13 14
D2
D1
D0
D3 17
VD
D4 18
8 PD
DGND
D5 19
7 AGND
9
15
HIGH PWR DIGITAL
COMPONENTS
DR GND 20
6 V
A
CLK
___
OE
ANALOG
CIRCUITRY
28 27
D11
VA
30 29
AGND
VRP
VRN
VRM
32 31
DGND
11
16
ADC DIGITAL
OUTPUT POWER
PLANE
DIGITAL
PWR SUP
ANALOG
PWR SUP
NOTE: ADCs DO NOT like Switching Supplies !
78
Signal Traces vs. Transmission
Line
• “Long” Lines Are Not Traces
• Transmission Lines Can Distort Signals
• Distorted Digital Signals Produce:
– Timing Uncertainty
– Clock Jitter
• Through Hole Problem
• Layout Can Be Critical
79
Maximum Trace Length
Remember: All traces are transmission
lines, but a trace length longer than this
absolutely must be treated as a
transmission Line:
tR
LMAX = 6 x t
PD
where LMAX is the maximum line length beyond which that line
must be considered a transmission line
tR is the signal rise time
tPD is the signal propagation rate down the board
80
Summary of Rules
• Use A Single, Unified Ground Plane
• Use Separate Power Planes
• Keep All Power Planes in
Same Board Layer
• Tie Down Grounded Copper Areas
at Many Points
• Remember: Traces Are Transmission
Lines
81
Recommended Reading
• High-Speed Digital Design, A Handbook of
Black Magic by Howard W. Johnson and Martin Graham,
Prentice-Hall, 1993 ISBN 0-13-395724-1
• Analog-Digital Conversion Handbook, the
Engineering Staff of Analog Devices,Inc, Prentice-Hall,
edited by Daniel H. Sheingold, 1986, ISBN 0-13-032848-0
82
Evaluating ADCs,
WaveVision Explanation
and Demonstration
Evaluating ADCs
• Garbage in – Garbage Out
– Need spectrally Pure Sine Wave
• Minimize Jitter
• Minimize Output Capacitance
• Follow Manufacturer Suggestions
– Voltages
– Layout
84
WaveVision History
• Need for Easy Data Capture & Evaluation
• Original WaveVision
– 80 MHz Oscillator on Capture Board
– ADC Sample Rates: 80 MHZ Divided by 2, 4, 8, or 16 (40, 20, 10, 5 Msps) ONLY
• WaveVision2
– Added 100 & 120 MHz Osc Possibilities
– ADC Sample Rates: 5, 6.25, 7.5, 10, 12.5, 20, 25, 30, 40, 50, 60 Msps
– Could use 125 MHz Osc for additional sample rates of 7.8125, 15.625, 31.25,
62.5 Msps, but frequencies incorrectly reported.
• WaveVision3
• Added Possibility of Inverting Sample Clock and Delaying Sample Clock by
One Master Clock Cycle for Better Timing
• Problem: All Manual Adjustments
• WavewVision4
– No Manual Adjustments
– Automatically Recognizes Device Board
– Virtually Any Sample Rate to 800 Msps Available
– Automatically Measures Sample Rate
– Better Display Software
85
WaveVision Demonstration
National’s ADCs
High Speed ADCs From
National – 8-Bits
ADC
Res
(Bits)
Speed Pwr. Cons
(Msps)
(mW)
INL
(LSB)
DNL
(LSB)
SNR
(dB)
SINAD
(dB)
SFDR
(dB)
@ fIN
(MHz)
ADC1173
8
15
36
±0.5
±0.4
48
46
51
7.5
ADC1175
8
20
60
±0.5
±0.35
47
46
58
4.4
ADC08351
8
42
40
±0.7
±0.6
45
45
54
4.4
ADC1175-50
8
50
125
±0.8
±0.7
44
44
56
19.9
ADC08060
8
60
1.3/Msps
±0.5
±0.4
47
47
60
25
ADC08L060
8
60
0.65/Msps
±0.5
±0.25
47.4
46.1
54.5
29
ADC08100
8
100
1.3/Msps
±0.4
46.5
46
63
41
ADC08200
8
200
1.05/Msps
±0.5
+1.0
-0.3
±0.4
46
46
60
50
ADC081000
8
1000
1.43 W
±0.35
±0.25
48
47
58.5
100
ADC08D1000*
2x8
1000
1.8 W *
±0.5 *
±0.4 *
47 *
46 *
57 *
100
* Expected specifications: product in development
88
High Speed ADCs From
National – 10-bits
ADC
Res
(Bits)
Speed
(Msps)
Pwr. Cons
(mW)
INL
(LSB)
DNL
(LSB)
SNR
(dB)
SINAD
(dB)
SFDR
(dB)
@ fIN
(MHz)
ADC10321
10
20
98
±0.45
±0.35
60
59
72
4.4
ADC10D020
2x20
Dual 20
150
±0.65
±0.35
59
59
75
4.7
ADC10030
10
30
125
±0.45
±0.4
59
58
68
13.5
ADC10040
10
40
55.6
±0.3
±0.3
59.6
59.4
80
19
ADC10D040
2x40
Dual 40
267
±0.65
±0.35
60
59
72
10.4
ADC10065
10
65
68.6
±0.3
±0.3
59.3
59
80
32
ADC10080
10
80
78.6
±0.5
±0.25
59.2
59
78.8
39
89
High Speed ADCs From
National 12-bits & Higher
ADC
ADC12662
ADC12010
ADC12020
ADC12040
Res
(Bits)
12
12
12
12
ADC12D040 2 x 12
ADC12L063
12
ADC12QS065 4 x 12
ADC12L066
12
ADC12DL066 2 x 12
CLC5957
ADC12L080
CLC5958
ADC16061
12
12
14
16
Speed Pwr. Cons
(Msps)
(mW)
1.5
200
10
160
20
185
40
340
INL
(LSB)
±0.4
±0.5
±0.55
±0.7
DNL
(LSB)
±0.4
±0.3
±0.4
±0.4
SNR
(dB)
70
70
70
69.5
SINAD
(dB)
69.7
69
69
69
SFDR
(dB)
83
85
84
@ fIN
(MHz)
0.1
10
10
10
40
62
65
66
66
600
354
840 *
357
686
±0.7
±1.0
±0.5 *
±1.2
±1.2
±0.4
±0.5
±0.3 *
±0.4
±0.5
68
66
66 *
65
64
68
65
66 *
64
63
80
78
79 *
73
72
10
10
32.5
25
33
70
80
52
2.5
640
357 *
1,400
390
±1.5
±1.2 *
±0.65
±0.4 *
±1.5
±3.0
±0.3
±1.0
66
65 *
69
80
64 *
69
79
74
73 *
80
91
25
25
10
0.5
* Expected specifications: product in development
Coming: ADC12DL040, ADC12L065
ADC14L020, ADC14L040
90
General Purpose ADCs From
National
ADC
Res
Mux Speed Pwr. Cons INL
DNL
(Bits) Inputs (ksps)
(mW)
(LSB) (LSB)
SNR
(dB)
SINAD
(dB)
SFDR
(dB)
@ fIN
(KHz)
ADCS7476
ADC081S101
ADCS7477
8
8
10
1
1
1
1,000
1,000
1,000
10
10
10
±0.05 ±0.07
±0.05 ±0.07
±0.2 ±0.3
49.7
49.7
62
49.7
49.7
61.7
69
69
78
100
100
100
ADC101S101
ADC104S051
ADCS7476
ADC121S101
ADC78H89
10
10
12
12
12
1
4
1
1
7
1,000
500
1,000
1,000
500
10
0.5
10
10
0.5
±0.2
±0.3
±1
±0.4
±0.4
±1
±1
±0.5
±0.5
±1
62
62
72.5
72.5
72.8
61.7
61.7
72
72
72.6
78
78
82
82
88
100
40
100
100
100
ADC78H90
ADC122S051
12
12
8
2
500
500
0.5
0.5
±1
±1
±1
±1
72.8
73
72.6
73
88
88
100
40
Coming: ADC082S051, ADC084S06, ADC102S051, ADC124S051
91
Summary - ABCs of ADCs
•
•
•
•
•
The ADC
Review of Definitions
Sources of Distortion and Noise
Common Design Mistakes
ADCs from National Semiconductor
92
National Semiconductor
Data Converter Web Site
• National Semiconductor’s Data Conversion
web site: www.national.com/adc
–
–
–
–
–
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Application Notes
Data Conversion Calculator
Definitions of Terms (ADC / DAC)
Evaluation Boards, Manuals, Software
Press Releases
Selection Guides
Technical Articles
Technical Presentations
Technical Support Link
93
94