Download Chapter 5 The CMOS Inverter

Digital IC-Design
Chapter 5
The CMOS Inverter
Goal With This Chapter
Analyze Fundamental Parameters
A general understanding of the inverter
behavior is useful to understand more complex
functions
Outline
Noise
Reliability
P f
Performance
Power Consumption
Digital IC-Design
Fundamental
parameters
for digital gates
Robustness
Noise - “unwanted variations of voltages and
currents in logical
g
nodes”
Classical noise such as thermal and flicker noise are
not critical in digital design
Noise sources in digital circuits are
Capacitive coupling
Inductive coupling
Power and ground noise
1
Capacitive and Inductive Coupling
V
CCoupling
V
I
Mutual
Inductance
Power and Ground Noise
A voltage or a current
change may influence
th signal
the
i
l on a parallel
ll l
wire, especially when:
Long wires
Sub micron tech.
Many metal layers
I
Definitions
VDD
RWire
VDD
ISwitch
V
Conclusion: The world is
not digital. We need to
know the limitations
A big
problem on
large
synchronously
clocked chips
On chip
decoupling
capacitors
p
helps
p
(≈ 1/10 of the
switched C)
DC Operation
Voltage Transfer
Characteristic (VTC)
VIN
5
VOUT
Switching Threshold
VM when VIN = VOUT
4
VOUT
DC Operation
Noise Margins
Fan OUT - Fan IN
VOH
3
Vout = VIN
VM
2
Logical “1” at VOH
Logical “0” at VOL
1
VOL
1
2
3
4
Balanced if VM = VDD/2
5
VIN
2
Analog versus Digital Signals
VOH, VOL = nominal
output
t t voltage
lt
VOUT
5
VOH
4
3
Slope = -1
2
Analog versus Digital Signals
Nominal
Output Levels
VOH
VIH, VIL = acceptable
input voltage
Accepteble
Input Levels
NMH
VOL
2
VIL
3
4
VOL
VIN
VIH
Undefined
Region
1
1
The noise margins
are defined as the
difference
between VOH/VOL
and VIH/VIL
NML
NML = VIL - VOL
O
NMH = VOH - VIH
VIL
VIH
The Ideal Gate
Fan-In and Fan-Out
VOUT
Fan-in = M
Fan-in = The
number of
inputs to the
gate
Fan-out = N
Fan-out = The
number of
gates that loads
the gate
Rin=∞
Rout=0
Noise Margin=VDD/2
Gain = ∞
VIN
3
Dynamic Definitions
A Real Gate
NML = VIL - VOL = 0.75 - 0.50 = 0.25V
5
Propagation delay
Rise and fall time
Power consumption
NMH = VOH - VIH = 3.50 - 2.25 = 1.25V
4
VOUT
VOH
3
VM = 1.75V
VDD
VIL
VM
2
VIH
1
VOL
GND
1
2
3
4
5
VIN
Delay Definitions
Ring Oscillator – minimum tp
V1
VIN
V2
V3
V4
V5
Odd # of
inverters
50%
tpHL
tpLH
VOUT
t
90%
50%
t pHL + t pLH
2
V1
“De-facto
Standard” for
performance
V2
V3
V2
10%
tf
tp =
tr
Fan-out = 1
V5
t
2 N tp
t
4
Ring Oscillator
Power Dissipation
Two measures are important
Peak power (Sets wire dimensions)
Do tp = 100ps mean 10 GHz chip?
Good Custom Design ≈ 1/10
Synthesized design ≈ 1/50 - 1/100
Why?
Low load
V1
V2
V3
Ppeak = VDD × iDD max
V4
Short Wires
Fan-out = 1
Low complexity
Power-Delay Product
V5
Average power (Battery and cooling)
T
V
Pav = DD ∫ iDD (t ) dt
T 0
Digital IC-Design
PDP = t p × Pav ( J )
The CMOS Inverter
Energy per operation
Energy per switching event
5
Inverters
The CMOS Inverter
VDD
On-chip resistors are large
St ti power consumption
Static
ti
VOL ≠ 0
Large tpLH
GND
VDD
+ Lower static power
consumption
ti
+ VOH = VDD; VOL = 0
+ tpLH = tpHL If properly designed
+ Low Impedance connection
to ground and VDD
Extra process step
Static power consumption
VOL ≠ 0
Large tpLH
VDD
GND
The CMOS Inverter
GND
- More fab. stages
- Lower hole mobility
The CMOS Inverter
VDD
VDD
Wider PMOS to
compensate for
lower mobility
Shared power and ground
Cascaded Abuted cells
GND
VDD
In
VDD
VDD
VDD
Out
GND
GND
In
Out
GND
In
Out
GND
In
Out
GND
6
CMOS Inverter - Model
VDD
Req-p
CMOS Static Behavior
Complementary i.e. output
y a low impedance
p
have always
connection to GND or VDD
Load characteristics
VTC
Switching threshold
Noise margin
g
VOH = VDD
CL
VOL = 0
Req-n
VM = f(Req-n, Req-p)
VM = VDD/2 if Req-n = Req-p
Load Lines
Inverter Load Characteristics
The VTC can be determined graphically
N-channel
ID
P-channel
IDn = -IDp
ID
VDS
ID
VGS=5V
- IDp IDn
VGS=5V
Vin=0V
VGS=4V
Vin=1V
VGS=4V
VGS=3V
Vin=2V
VGS=3V
VGS=5V
Vin = VDD-V
VGSp
VGS=-3V
VDS
VGS=4V
VGS=-4V
VGS=3V
VGS=-3V
Vout = VDD-VDSp
VDS
VGS=-4V
VGS=-5V
VGS=-5V
Vin =
VDD-VGSp
Vout =
VDD-VDSp
VDS
7
Inverter Load Characteristics
Vin=0V
I
Vin=0V
Region: Linear - Saturation
Vin=5V
5
VOUT
N sat
P lin
N off
P lin
I
Vin=5V
Vin=1V
Vin=4V
4
Vin=2V
Vin=1V
Vin=4V
Vin=2V
Vin=3V
VM
Vin=3V
N sat
P sat
1
VTC graphically
extracted from the
l d li
load
lines
VOH= VDD
4
High noise margin
3
NMH=VOH-VIH ≈ 5-2.9 = 2.1V
NML =VIL-VOL ≈ 2.1-0 = 2.1V
VM= VDD/2
2
Vin=2V
Vout
N lin
P sat
1
2
N lin
P off
3
4
VIN
5
Switching Threshold
CMOS Inverter VTC
5
Vin=3V
2
Vin=2V
Vout
VOUT
3
Vin=3V
VM
Long Channel
Transistors
Both transistors are saturated
k
kn
(VM − VTn ) 2 = −(− p (VM − VDD − VTp ) 2 ) ⇒
2
2
kp
VM − VTn = − (−VM + VDD + VTp ) ⇒
kn
VM + r × VM = VTn + r × (VDD + VTp ) ⇒
1
VOL= 0
1
2
3
4
VIN
5
⇒ VM =
VTn + r (VDD + VTp )
1+ r
with r =
−k p
kn
8
Switching Threshold
VM =
r (VDD + VTp ) + VTn
with r =
1+ r
−k p
Long Channel
Transistors
kn
(VTn = -VTp = 0.5 V)
Switching Threshold
VM =
r (VDD + VTp ) + VTn
1+ r
with r =
−k p
kn
5
5
VM
5
4
4
3
3
2
2
1
1
1
2
4
6
0.1
8
kp/kn10
4
Moderate deviation from
kp/kn = 1 gives only
small changes in VM
VM
VM
0.32
1
3.2
kp/kn10
3
2
Wp = 2Wn common to
t
save area, since the
change in VM is small
1
0.1
0.32
1
3.2
kp/kn10
Wp≈3Wn
Simulated VTC: Short Channel
Switching Threshold: Example
Inverter with W/L = 0.6 μ / 0.35 μ
VTn = 0.50, kn = 300 μ,
r=
−k p
kn
=
103μ
= 0.59
300μ
Balanced 0.25μm inverter
VTp = - 0.65, kp = -103 μ
2.5
2
VDD = 3V
1+ r
0.59 (3 − 0.65) + 0.5
= 1.18 V
1 + 0.59
out
=
V
VM =
(V)
1.5
r (VDD + VTp ) + VTn
1
0.5
GND
0
0
0.5
1
1.5
2
2.5
V (V)
in
9
VTC: Short Channel
Wp
Lp
=
0.375
0.25
VTC: Short Channel
0.25
Minimum sized 0.25μm transistors
ID (mA)
Wn 0.375
=
Ln 0.25
0.25
ID (mA)
VGS = 2.5
25
VIN = 2.5
0.20
0 25
0.25
ID (mA)
0.20
VGS = 2.5
0.20
VIN = 1.875
VGS = 1.875
0.15
VGS = 1.875
0.15
0.10
VIN = 0
0.10
0.10
VGS = 1.25
0
VGS = -0.625
0.05
VGS = 1.25
PMOS
0.05
0
VGS = 1.0
10
VGS = -1.25
VGS = 0.625
VGS = -0.625
VGS = 1.0
VGS = -1.25
VIN = 1.0
10
VIN = 1.25
-0.05
NMOS
VIN = 1.25
VIN = 0.625
VGS = 0.625
VGS = -2.5
-0.10
-2.5
-2.0
-1.5
VGS = -1.5
VGS = -1.875
-1.0
-0.5
0
0.5
VIN = 1.875
0
VDS (V)
1.0
1.5
2.0
VIN = 1.0
10
VIN = 0.625
0.5
1.0
VGS = -2.5
-0.10
-2.5
-2.0 -1.5
VGS = -1.875
-1.0
-0.5
0
0.5
VDS (V)
1.0
1.5
2.0
2.0
2.5
VOUT (V)
2.5
-0.05
VGS = -1.5
1.5
Move the PMOS part to the first quadrant
2.5
VTC: Short Channel - Graphically
Switching Threshold: Short Channel
0.25
Vout (V)
ID (mA)
VIN = 2.5
Vout (V)
2.5
2.5
0.20
20
2.0
VTC
The threshold
VM is when
VIN=VOUT
2.0
1.5
VIN = 1.875
1.5
1.0
0.10
VIN = 0
0.5
VIN = 1.25
VIN = 0.625
VIN = 1.0
VIN = 1.25
VIN = 1.875
0
VM =1 V
1.0
VIN = 1.0
VIN = 0.625
0.5
1.0
1.5
2.0
VOUT (V)
2.5
0.5
0
0.5
1.0
1.5
2.0
2.5
Vin (V)
0
0.5
1.0
1.5
2.0
2.5
Vin (V)
10
Switching Threshold: Short Channel
Both NMOS and PMOS are velocity saturated
kn ((VM −VTn )VDSATn −
2
2
VDSATp
VDSATn
) = k p ((VDD −VM + VTp )VDSATp +
)
2
2
VM =
V
⎞
VDSATn ⎛
+ r ⎜VDD +VTp + DSATp ⎟
2
2 ⎠
⎝
1+ r
Minimum transistor dimensions
VDSATn = 0.63; VDSATp = −1; VTn = 0.43; VTp = −0.4;
0.375
0.375
kn =
×115 = 172.5; k p =
× (−30) = −45
0.25
0.25
r=
Solving VM yields
VTn +
Example 0.25 μm technology
where r =
k p VDSATp
k p VDSATp
kn VDSATn
VTn +
VM =
kn VDSATn
Example 0.25 μm technology
IF VDD >> VDSAT and VT
V
⎛
⎞
V
VTn + DSATn + r ⎜VDD + VTp + DSATp ⎟
2
2 ⎠ r VDD 0.41× 2.5
⎝
≈
=
= 0.73 V
VM =
1+ r
1+ r
1+ 0.41
=
Parameters from
the inside back
cover in the book
−45× (−1)
= 0.41
172.5× 0.63
V
⎞
VDSATn ⎛
+ r ⎜VDD +VTp + DSATp ⎟ 0.43 + 0.63 + 0.41⎛⎜ 2.5 − 0.4 − 1 ⎞⎟
2
2 ⎠
2
2⎠
⎝
⎝
=
= 1.0 V
1+ r
1+ 0.41
Balancing the inverter
It is desirable to have VM around VDD/2
2
kn'
W
V
Wn
V 2
((VM −VTn )VDSATn − DSATn ) = k p' p ((VDD −VM + VTp )VDSATp + DSATp )
Ln
2
Lp
2
Assuming Ln = Lp yields
VDD not high enough in this case
VDSATn2
)
2
=
V 2
Wn
k p' ((VDD −VM +VTp )VDSATp + DSATp )
2
Wp
kn' ((VM −VTn )VDSATn −
11
Balancing the inverter
Balancing the inverter
1.8
Example using the same data
1.7
1.6
2
To be balanced, The PMOS should be 3.5
times wider than the NMOS
M
1.4
V (V)
VDSATn
0.63
)
115× ((1.25 − 0.43) × 0.63 −
)
Wp
2
2 = 3.5
=
=
2
−1
V
Wn
−k p' ((VDD +VM −VTp )VDSATp + DSATp ) −30 × (−2.5 +1.25 − (−0.4) − )
2
2
kn' ((VM −VTn )VDSATn −
15
1.5
2
1.3
1.2
1.1
1
0.9
0
0.8
8
10
2
0
10
W p /W
For the minimal NMOS with Wn=0.375 μm,
the corresponding PMOS has Wp=1.3 μm
Determining VIH and VIL
VIH and VIL when
the slope is -1
⇒
2
V
out
(V)
1.5
1
∂VOUT
= −1
∂Vin
g=
0.5
0
0
0.5
1
1.5
V (V)
in
2
2.5
VM is rather insensitive to changes in the device ratio
A ratio decrease from 3.5 to 2 yields VM = 1.13 V
which often is acceptable
Saves area
Determining VIH and VIL
A reasonable
approximation is
to use the gain (g)
around VM
2.5
1
n
ΔVOUT
ΔVin
Vout (V)
A simplified
piecewise linear VTC
p
VIL
2.5
2.0
g=
1.5
VM
1.0
ΔVOUT
ΔVin
0.5
VIH
0
0.5
1.0
1.5
2.0
2.5
Vin (V)
12
Determining VIH and VIL
g=
Vout (V)
VIL
2.5
g=
VDD −VM
VIL −VM
VIL = VM +
2.0
VDD-VM
ΔVOUT
ΔVin
The Inverter Gain (g)
g =−
VDD −VM
g
Derived at
page 189
1 knVDSATn + k pVDSATp
1+ r
≈−
VDSAT
I D (VM )
λn − λp
(VM −VTn − DSATn
)(λn − λp )
2
0
-2
1.5
Note that the gain is
very
y sensitive to the
channel-length
modulation
-4
VM
-6
VM-VIL
g=
0.5
VIH
0
0.5
1.0
1.5
2.0
2.5
Vin (V)
VM
VM −VIH
V
VIH = VM − M
g
VDD −VM
g
V
VIH = VM − M
g
2.0
VDD-VM
1.5
VM
1.0
NMH = VDD −VIH ;
VM-VIL
-12
-14
-16
-18
0
0.5
1
1.5
2
2.5
V (V)
Example (Minimum sized transistors)
VIL = VM +
VIL
2.5
-8
8
-10
in
Noise Margins
Vout (V)
gain
1.0
0.5
g ≈−
Vout (V)
VIL
2.5
2.0
VDD-VM
=−
1.5
NML = VIL
VM
1.0
= −34.6
VIH
0.5
1.0
1.5
1 + 0.41
=
0.63
(1 − 0.43 −
)(0.06 + 0.1)
2
VM-VIL
0.5
0
1+ r
=
V
(VM −VTn − DSATn )(λn − λp )
2
VIH
2.0
2.5
Vin (V)
0
0.5
1.0
1.5
2.0
2.5
Vin (V)
13
Example (Minimum size transistors)
CMOS Dynamic Behavior
VDD −VM
2.5 −1
= 1+
= 0.96 V
g
−34.6
V
1
VIH = VM − M = 1−
= 1.03 V
g
−34.6
VIL = VM +
Vout (V)
VIL
2.5
2.0
VDD-VM
Capacitors
Propagation delay
Power consumption
1.5
NMH = VDD −VIH = 2.5 − 0.96 = 1.54 V
VM
1.0
NML = VIL = 1.03
1 03 V
VM-VIL
0.5
VIH
0
0.5
1.0
1.5
2.0
2.5
Vin (V)
Inverter Load
Slightly to large
values due to the
approximation
Vin
Vout
CL
Capacitance model
for propagation
d l
delay
calculations
l l ti
Inverter Load
Cgd = Overlap Capacitance
Cdb = Junction Capacitance
Cw = Wire
Wi Capacitance
C
i
VDD
Cg = Overlap & Gate Capacitance
VDD
Vin
i
Cgd2
d2
Cdb2
Voutt
Cg44
Cgd1
Cdb1
Cw
Cg3
Vout2
t2
Vin
Cgd2
Cdb2
Vout
Cg4
Cgd1
Cdb1
Cw
Cg3
Vout2
14
Cgd - Overlap Capacitance
The Miller Effect
Assumed to be in Cut-off or Saturation
If Cgd is modeled from Vout to
GND, the value shall be doubled
GND
- No Channel Capacitance (at output side)
- Only Overlap Capacitance
Cgd
VDD
Vin
Cgd2
Cdb2
Vout
Cg4
Cgd1
Cdb1
Cw
Cg3
ΔV
ΔV
ΔV
Cgd = 2 Cgd0 W
Cw - Wire Capacitance
Cdb = Keq × C j 0
Neglected on short distances
I
Increased
d importance
i
t
in
i new technologies
t h l i
Depends on grading coefficient
Diode area and perimeter
VDD
Cgd2
Cdb2
Vout
Cg4
Cgd1
Cdb1
Cw
Cg3
2Cgdd
Vout2
Cdb - Junction Capacitance
Vin
ΔV
Vout2
VDD
Vin
Cgd2
Cdb2
Vout
Cg4
Cgd1
Cdb1
Cw
Cg3
Vout2
15
Channel Capacitance
Region
Cut off
Linear
Saturation
Cg - Gate Capacitance
Cg
C gs
C gd
C OX WL eff
0
0
Overlap – Cgs (Not Cgd)
Ch
l – WLCox
Channel
0
(1/2)C OX WL eff (1/2)C OX WL eff
0
(2/3)C OX WL eff
0
VDD
Cut off: No channel
Linear: Channel
Saturation:
⇒ CG = CGB
⇒ Divide channel in two parts
Vin
≈ 2/3 Channel connected to source
Expression
Cgdd
2Cgd0
d0W
Cdb
Keq(ACj+PCjsw)
Cg
Cgs0W+CoxWL
Cw
Cdb2
Vout
Cg4
Cgd1
Cdb1
Cw
Cg3
Vout2
Inverter - Transient Response
Inverter Load Model
Capacitor
Cgd2
-
t
Vout = (1- e RC )V ;
VDD
Model
Vin
0.1VDD = (1 − e
Req-p
−
t10
RC
)VDD
tr = t90 - t10
⇔ 0.9 = e
−
t10
RC
⇔
t10 = − RC ln(0.9)
CL
Vout
t90 = − RC ln(0.1)
CL
Area + Fringe
g Cap.
p
Req-n
tr = t90 − t10 = (− ln(0.1)
l ( ) + ln(0.9))
l ( )) RC = tr = 2.2 RC
The values differ for n- and p-channel
The values differ for L to H / H to L
t pHL = t50 = − ln(0.5) RC = t pHL = 0.69 RC
Se table 5-2
16
Req in Short Channel Transistors
Req -n =
Req -n
Digital IC-Design
Chapter 5
Rn (VOUT =VDD ) + Rn (VOUT =VDD / 2)
=
2
⎡VDS ⎤
⎡ VDS ⎤
+
⎢
⎥
⎢
⎥
⎣ I D ⎦ (VOUT =VDD ) ⎣ I D ⎦ (VOUT =VDD / 2)
=
2
Req in Short Channel Transistors
Cont.
Req in Short Channel Transistors
Graphical
Method
I D (mA)
The CMOS Inverter
VGS = 2 V
0 15
0.15
I D VDD / 2 = 145 μ A;
Graphical
Method
I D VDD = 153 μ A;
I D VDD = 153 μ A
I D VDD / 2 = 145 μ A
0.1
In Velocity
Saturation
05
0.5
Req -n
VDS (V)
0
0
0.63 V
1
2
Req -n
⎡VDS ⎤
⎡V ⎤
+ ⎢ DS ⎥
⎢I ⎥
⎣ D ⎦ (VOUT =VDD ) ⎣ I D ⎦ (VOUT =VDD / 2)
=
=
2
2
1
+
−6
145 ×10−6 = 10 kΩ
= 153 × 10
2
17
Req in Short Channel Transistors
Req for Short Channel NMOS
I D (mA)
Find IDSAT
Model Based Method
0.15
VGS = 2 V
0.1
VDD
⎛
⎞
⎟ 3 VDD ⎛ 5
VDD
1⎜
⎞
2
Req = ⎜
1 − λV
+
≈
VDD ⎟ 4 I DSAT ⎜⎝ 6 DD ⎟⎠
2 ⎜ I DSAT (1 + λVDD ) I
)⎟
DSAT (1 + λ
2 ⎠
⎝
with
⎛
V2 ⎞
I DSAT = k ⎜ (VDD − VT )VDSAT − DSAT ⎟
⎜
2 ⎟⎠
⎝
In Velocity
Saturation
Req in Short Channel Transistors
I DSAT = 136 μ A;
λ =0.06 V
VDD
⎛
⎞
⎟ 3 VDD
VDD
1⎜
2
+
≈
Req = ⎜
VDD ⎟ 4 I DSAT
2 ⎜ I DSAT (1 + λVDD ) I
⎟
+
(1
)
λ
DSAT
⎝
2 ⎠
VDSAT = 0.63 V;
kn' = 115 mA/V 2
W = 0.375 μ m;
= 0.25 μ m
I DSAT
VDS (V)
0
0
1
0.63 V
⎛
V2 ⎞
⎜⎜ (VDD − VT )VDSAT − DSAT ⎟⎟ =
2 ⎠
⎝
W
=k
L
'
n
I DSAT = 115
I DSAT
0.5
2
IDSAT = ID when
VDS = 0
(extrapolated)
0.375 ⎛
0.63 ⎞
⎜ (2 − 0.43)0.63 −
⎟ = 136 μ A
0.25 ⎝
2 ⎠
2
Inverter - Transient Response
VDD
⎛ 5
⎞
⎜1 − λVDD ⎟
⎝ 6
⎠
2
⎛
⎞
⎟ 3
1⎜
2
2
⎛ 5
⎞
2
Req = ⎜
+
0 06 × 2 ⎟
⎟≈
⎜1 − 0.06
2 ⎜ 136 ×10−6 (1 + 0.06 × 2) 136 × 10−6 (1 + 0.06 × 2 ) ⎟ 4 136 × 10−6 ⎝ 6
⎠
2 ⎠
⎝
Req = 10.0 kΩ ≈ 9.9 kΩ
VDD = 2 V; VT = 0.43 V;
Req-p
CL = 2 fF ;
Req − n = 10 k Ω
tr = 2.2 RC = 2.2 × 10 × 103 × 2 × 10−15 = 44 ps
CL
Req-n
t pHL = 0.69
0 69 RC = 0.69
0 69 × 10 × 103 × 2 × 10−15 = 14 ps
(1 % error)
18
Inverter - Propagation Delay
Propagation Delay (page 202)
Long Channel
Q = C × ΔU = CL (VOH - VOL ) / 2 = CLVDD / 2 Transistors
Q = I ×t =
t pHL =
kn
k
(VGS - VT ) 2 × t pHL = n (VDD - VT ) 2 × t pHL
2
2
CLVDD
CL
≈
2
kn (VDD - VT )
knVDD
t pHL = 0.69
= 0.52
C
1 1
tp = L ( + )
2VDD kn k p
V
CL
Short Channel
Transistors
What Ratio Should be Chosen? Short-channel
Transistors
-11
t pLH
t pHL
β=
Fan-Out = 1
4.5
tp
t (sec)
p
V
CL
3.5
3
1.5
2
2.5
3
3.5
4
4.5
Wp
Wn
Fan-Out = 1
β=3.5 balance the inverter (VM=VDD/2)
t p (s)4
1
VDSATn
)
2
Ideal Vin (Step)
Propagation Delay Simulation
x 10
CLVDD
CL
Ideal Vin (Step)
5
3 CLVDD
=
4 I DSAT
knVDSATn (VDD − VTn −
V
Short
Channel
Transistors
5
β
β = Wp/Wn
β=2 (or 2.4) for equal delays
(tpLH=tpHL)
V
However, β=2 might be acceptable
(VM≈0.45 VDD)
Wp
Wn
CL
A ratio around 2 is close to optimum
19
Effect of Input Rise Time
tpHL [ns]
tpHL Increase
linearly with the
input rise time trise
Note the
gain
0 35
0.35
Digital IC-Design
Driving a Large Fan-out
0.30
0.25
t pHL ( actual ) = t 2pHL ( step ) +
tr2
4
0.20
0.15
0.2
0.4
0.6
0.8
1.0
trise [ns]
Inverter Chain
In
Driving a Large Fan-Out
Typical examples:
Out
Busses
CL
Driving a large
capacitance
Clock network
Control wires (e.g. set and reset signals)
If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?
Memories (driving many storage cells)
VDD
Worst case:
Off chip signals
CL
20
Inverter with Load (External only)
Inverter with Internal Load
Delay
Delay
Req
Cint
Cext
Req
Cext
Load (Cext)
External Load
tp = 0.69 Req Cext
Internal (intrinsic) load is neglected
Not the case in modern technologies
Device Sizing (W scaled with S)
3.8
x 10
(for fixed load)
3.4
External load
capacitances
dominate
3.2
p
Self-loading if Cint dominate
Should be avoided
Driving Large Capacitances
Cint = Intrinsic capacitance
Req
-11
3.6
t (sec)
tp = 0.69 Req (Cint + Cext)
Cext = Extrinsic capacitance
Req = Resistance in channel
Cint = Cdb+Cgd
Cext = Cw + Cg
3
Self-loading effect:
Intrinsic capacitances
dominate ((W is to
wide compared to the
load)
2.8
2.6
2.4
2.2
2
2
4
6
8
S
10
12
14
Cw = Wire capacitance
Req
VDD
Cg = Gate C in next stage
Req
Req
Cint
Cext
21
Scaling to Increase Driving Capability
Req
Scaling W with a factor S:
Cint = S × Ciref
Cint = Cdb+Cgd
Req =
Req
Rref
Scaling to increase driving capability
Delay RC-model
t p = 0.69 Req (Cint + Cext ) = 0.69 Req Cint (1 +
Scaling with a factor S
t p = 0.69
S
Rref
S
S Ciref (1 +
Cext
C
) = t p 0 (1 + ext )
S Ciref
S Ciref
VDD
tp0 = intrinsic delay
Req
Req
Cint
Independent of S
Cext
Scaling Example (page 206)
Scaling Example (page 206)
t p 0 = 19.3 ps; Cext = 3.15 fF ; Ciref = 3.0 fF
t p = t p0
Cext
)
Cint
t p = 19.3 × (1 +
C
1
(1 + ext ) = 19.3 (1 +
) ps
S Ciref
1.05 × S
tp (ps)
1
)
1.05 × S
ps
S =5, Substantial improvement
40
S >10, ”No more gain”
30
Ciref
Cext
20
10
S
0
5
10
15
22
Sizing a Chain of Inverters
Sizing a Chain of Inverters
γ = Capacitive proportionality
γ=
factor for each inverter
- Technology Dependent
- Independent of the size (W)
- Close to 1 in Submicron
1
Cg,1
Cg,2
f=
Cg, j
N
Cint,2
Cg,N
1
Cint,N
Cg,N+1= CL
Sizing a Chain of Inverters
Cg,1
2
f=
Cint,1
Cg,2
Cint,2
Cg , j +1
f=
Cg , j
Total Delay:
t p , j = t p 0 (1 +
1
Cg,1
Cext , j
Cint , j
) = t p 0 (1 +
2
Cint,1
Cg,2
C g , j +1
γ Cg , j
) = t p 0 (1 +
fj
γ
)
N
Cint,2
Cg,N
t p = t p0
Cg,N+1= CL
Cg,1
fj
N
∑ (1 + γ
Cg,N
Cg ,2
Cg ,1
2
Cint,1
Cg,2
=
Cg ,3
Cg ,2
=
Cint,N
Cg,N+1= CL
Known
Cg , j
Cg , j −1
=
Cg , j +1
Cg , j
=
CL
Cg , N
If each stage is scaled
with the same factor f
)
j =1
1
Cint,N
Cg , j
N
Sizing a Chain of Inverters
Cint, j = γ Cg, j
Cg , j +1
f = The loading capacitive ratio
in two following stages
The in- and
output
capacitive ratio
2
Cint,1
Cint, j
N
Cint,2
Cg,N
Cint,N
Cg,N+1= CL
23
Sizing a Chain of Inverters
f=
Sizing a Chain of Inverters
Cg ,2
C
f =N L =NF
Cg ,1
Cg ,1
f2=
Known
Cg ,3
t p = t p0
Cg ,1
∑ (1 +
j =1
fj
γ
) = N × t p 0 (1 +
F
γ
)=
γ
(F = overall effective fan- out)
1
2
f =e
N
1
Cint,1
Cg,2
Cint,2
Cg,N
Cint,N
Sizing a Chain of Inverters
γ
f =e
(1+ )
f
2
(1+ )
f
N
Cg,N+1= CL
Cg,1
Cint,1
Cg,2
Cint,2
Cg,N
Cint,N
Has no closed form
solution
so
u o except
p for
o
γ=00
Normalized delay
f=
1
Cint,1
Cg,2
Common
Practice
Around 4
2
N
Cint,2
Cg,N
Cg , j
6
Otherwise: f is
solved numerically
2
Cg , j +1
Too many
stages
tp
t popt
4
f =e
Cg,N+1= CL
Sizing a Chain of Inverters
γ=0 when intrinsic capacitance is neglected
Cg,1
N
Optimum is found by setting the derivative to 0
C
fN= L =F
Cg ,1
Cg,1
N
f =NF
Cint,N
Cg,N+1= CL
f
1
2
3
4
for f = e
1
(1+ )
f
5
24
Buffer Design
Inverter Chain
1
f
tp
Common practice:
1
64
65
Optimum fan-out around f=4
2
8
18
64
3
4
15
64
4
2.8
15.3
64
1
8
1
4
16
2.8
8
1
N
64
22.6
Digital IC-Design
1
4
16
I
In
O t
Out
CL
Dynamic Power Consumption
VDD
Charge
Power Consumption
Energy charged in a capacitor
EC =
C V2
CV2
= L DD
2
2
Energy EC is also discharged, i.e.
2
Etot = CL VDD
Discharge
Power consumption
2
P = f CL VDD
25
Dynamic Power Consumption
VDD
Charge
Note: The power is
dissipated in the transistor
resistance, Req
Current Spikes – Direct Path
Edp = VDD
Pdp =
I peak × tr
tr × t f
2
2
+ VDD
I peak × t f
2
=
tr × t f
2
Current peak
when both Nand PMOS are
open
VDD I peak
VDD I peak f
However: the power
consumption is independent
of the value of Req
VDD-VT
VT
Discharge
P = CL VDD2 f
Static Power Consumption
Ileakage increases
with decreasing VT
0
Dynamic vs. Static Power
The dynamic and static power is about
equal in the 65 nm Technology
Pstat =Ileakage × VDD
Drain leakage
to bulk &
drain-source
subthreshold
current
100
Normalized power
VDD
Ipeak
N open
P open
Dynamic power
1
65 nm
0.01
0.0001
0.0000001
1990
Source: ITRS
Static power
2000
2010
Year
2020
26
Digital IC-Design
Power-Delay Product
Helps to measure the quality
of different circuit topologies
Power Delay Product
(PDP)
Power-Delay Product
Energy per switching event
For static CMOS
2
2
PDP = P × t p = CL × VDD
× f max × t p = CL × VDD
×
2
CL × VDD
2
2t p
=
2
CL × VDD
2
(J )
Independent of operating
frequency
Some Examples - Cascaded Inverters
Compensated to
Decrease tpLH
Minimal Design
Energy per switching event
PDP = P × t p =
tp
If we lower the supply, the
PDP will be reduced, but also
the performance
VDD
15 kΩ
30 kΩ
In
Out
2 fF
Out
Energy and performance
EDP = P × t p2 =
2
CL × VDD
×tp
2
Some claims that EDP is a
better measure since it
includes the delay
10 kΩ
10 kΩ
GND
1 fF + 2 fF
1 fF + 3 fF
Req − n = 10 k Ω; Req − p = 30 k Ω;
Req − n = 10 k Ω; Req −Comp = 15 k Ω;
CMin = 4 fF
CComp = 6 fF
27
Propagation Delay
Power Consumption at Max Speed
Req − n = 10 k Ω; Req − p = 30 k Ω; Req − Comp = 15 k Ω;
CMin = 4 fF ; CComp = 6 fF ; VDD = 2 V
CMin = 4 fF ;
Not much faster but
more symmetric
t pHL − Min = 0.69 × CMin × Req − n = 28 ps
t pLH − Min = 0.69 × CMin × Req − p = 83 ps
t p − Min =
t pHL − Min + t pLH − Min
2
t pHL − Comp = 0.69 × CComp × Req − n = 41 ps
= 55 ps
t pHL −Comp + t pLH −Comp
t pLH − Comp = 0.69 × CComp × Req − Comp = 62 ps t p −Comp =
2
= 52 ps
f Max − Min =
CComp = 6 fF ;
1
= 9.1
9 1 GHz
GH ;
2t p
VDD = 2 V
f Max − Comp =
2
2
PMin = CMin × VDD
× f Max − Min = CL × VDD
×
1
= 99.7
7 GH
GHz
2t p
1
= 140 μW
2t p − Min
2
2
× f Max − Comp = CL × VDD
×
PComp = CComp × VDD
Compensating
gives higher
power
consumption
1
= 230 μW
2t p − Comp
VDD
In
Out
In
Out
VDD
In
Out
In
Out
GND
Total Power Consumption and PDP
Power-Delay Product
2
2
PDP = P × t p = CL × VDD
× f max × t p = CL × VDD
×
PDPComp
tp
2t p
=
2
CL × VDD
2
(J )
Compensating
gives higher
energy per
switching event
2
CMin × VDD
= 8 fJ
2
2
CComp × VDD
=
= 12 fJ
2
PDPMin =
VDD
In
Out
In
GND
Out
Ptot = Pdyn + Pdp + Pstat =
2
= CLVDD
f
+
tr + t f
2
VDD I peak f
2
CL × VDD
PDP = P × t p =
2
+
I leakageVDD
(J )
GND
28