Download Dynamic Logic Circuits

Dynamic Logic Circuits
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Static logic circuits allow
implementation of logic functions
based on steady state behavior of
simple nMOS or CMOS structures.
All valid output levels in static
gates are associated with steady
state operating points of the circuit
in question.
This detects that a certain time
delay be allowed before the output
corresponding to the applied
input(s) can be valid.
The output level is preserved as
long as the power supply is
provided.
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In high density, high-performance
digital implementations where
reduction of circuit delay and silicon
area are objectives dynamic circuits
offer several advantages over static
logic circuits.
Operation of dynamic logic gates
depends on temporary (transient)
storage charge in parasitic node
capacitances instead of steady state
behavior. This operational property
necessitates updating of internal node
voltage levels since charge in a
capacitor cannot be retained
indefinitely.
Dynamic circuits require periodic clock
signals for control of charge refreshing.
Dynamic Logic Circuits
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Temporarily storing a state at
capacitive nodes permits for
implementation of simple
sequential circuits with memory
functions.
Use of common clocks throughout
the system allows for
synchronization of operations in
various circuit blocks.
The D-latch static D-Latch studied
earlier in the semester can now be
implemented using dynamic
circuits as shown below.
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The hold operation is occurs when
the clock is low and charge is
temporarily stored in the parasitic
capacitance Cx.
Correct operation depends on how
long charge can be retained at node
X, before the output state changes
due to charge leakage.
Charge Sharing
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In many structures a bus can be
modeled as a capacitor Cb.
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bus
Vb
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Vs
Cb
Cs
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The voltage on this bus might be
sampled from time to time (e.g. writing
the data on the bus into memory).
In general we can represent the
capacitances associated with this bus as
Cb and Cs .
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The charge associated with each
capacitor before closing the switch
is described by Qb = CbVb and
Qs = CsVs.
The total charge QT is described by
QT = CbVb + CsVs
The total capacitance CT is given
by: CT = Cb + Cs .
When the switch is closed the
resultant voltage VR is:
V 
R
Q CV CV

C
C C
T
T
b
b
s
b
s
s
Charge Sharing
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If Vb = VDD and Vb >>Vs then the
desired voltage VR is:
 C 0 
V V 

C  C 
b
R
DD
b
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s
To ensure proper data transfer from
Cb to Cs, we must have that Cs <<
Cb .
The charge sharing problem is
prominent in dynamic circuits