Download vlsiintroduction

A 46
X=(AB*CD)+
(A+D)+(A(B+C))
Y = (A(B+C)+AC+
D+A(BC+D))
F 8
E
23
H
37
G 19
I 12
K 27
D 56
VLSI Layout Algorithms
CSE 6404
Dr. Md. Saidur Rahman
J 14
B
65
C 11
Text Books
• Algorithms for VLSI Physical Design
Automation by Naveed Sherwani
• Planar Graph Drawing by Takao Nishizeki
and Md. Saidur Rahman
• Physical Design Automation: Theory and
Practice by S. M. Sait and H. Youssef
Marks Distribution
•
•
•
•
Attendance
15
Presentation / Class Lecture
Discussions on Class Lecture
Examination
55
25
5
Presentation Schedule
• Presentation/ Lecture time: 30 minutes
• Presentation will start from 3rd week.
Multi-layer Channel Routing: Complexity and
Algorithms by Rajat K. Pal
Objectives
• General understanding of ICs and their
production process.
• Study the basic algorithms used in designing the
layout of a chip.
Why are algorithms needed?
mannual
System specification
chip
automation
Large number of devices
Optimization required for high performances
Time-to-market competetion
Cost
Transistors
Microprocessors
10M
80386
68020
68000
1M
100K
10K
1K
100
10
1
8086
4004
8080
PPC603
Pentium
80486
Pentium Pro
PPC601
MIPS R4000
68040
Clock speed GHz
11
9
7
5
3
1
0
1997
1999
2001 2003
2006 2009
On-chip, local clock, high performance
On-chip, global clock, high performance
2012
Increasing Device and Context Complexity
• More complex system contexts
Complexity
• Exponential increase in device
complexity
• Require exponential increases in
design productivity
We have exponentially more transistors!
[©Keutzer]
Deep Submicron Effects
DSM Effects
• Smaller geometries are causing a wide
variety of effects that we have largely ignored
in the past:
– Crosscoupled capacitances
– Resistance
– Inductance
Design of each transistor is getting more difficult!
[©Keutzer]
Heterogeneity on Chip
• Greater diversity of onchip
elements
– Processors
– Software
– Memory
– Analog
Heterogeneity
More transistors doing different things!
[©Keutzer]
Stronger Market Pressures
• Less tolerance for design
revisions
Time-to-market
Exponentially more complex, greater design risk,
greater variety!
[©Keutzer]
A QuadrupleWhammy
Complexity
Time-to-market
Heterogeneity
DSM Effects
[©Keutzer]
How Are We Doing?
58% / Yr. compound
complexity growth rate
10,000,000
1,000,000
100,000
10,000
1,000
100,000
Productivity
gap
10,000
1,000
100
10
21% / Yr. compound
productivity growth rate
Productivity
Trans. / Staff . Month
1,000,000
100,000,000
100
2009
2005
2001
1997
1993
1989
1981
10
1985
Logic transistors per chip
(K)
10,000,000
Source:
SEMATECH
We need efficient design algorithms to reduce the production gap.
[©Keutzer]
LAYOUT
Geometric description of a circuit
A layout consists of set of planar geometric
shapes in several layer.
Physical design process
The process of converting the specification of an
electrical circuit into a layout is called physical
design process.
VLSI Physical Design Automaion
VLSI physical design automation is essentially
the study of algorithms and data structures
related to physical design process.
VLSI Design Cycle
High-level
Description
System Specifications
Factors considered
Performance
Functionality
Physical dimension
Fabrication technology
Design techniques
Market requirements
compromise
Cost
Technology
Specifications
High-level
Description
Functional
Description
Figs. [©Sherwani]
High-level
Description
Specifications
Physical
Design
Placed
& Routed
Design
Packaging
Synthesis
Technology
Mapping
Gate-level
Design
Fabrication
Functional
Description
Logic
Description
X=(AB*CD)+
(A+D)+(A(B+C))
Y = (A(B+C)+AC+
D+A(BC+D))
Figs. [©Sherwani]
High-level
Description
Specifications
Physical
Design
Placed
& Routed
Design
Packaging
Synthesis
Technology
Mapping
Gate-level
Design
Fabrication
Functional
Description
Logic
Description
X=(AB*CD)+
(A+D)+(A(B+C))
Y = (A(B+C)+AC+
D+A(BC+D))
Figs. [©Sherwani]
Physical Design
Physical design converts a circuit description into
geometric description.
This geometric description is used to manufacture a
chip.
Physical design cycle consists of
1. Partioning
2. Floorplannig and placement
3. Routing
4. Compaction
Design Styles
Full Custom Design Example
I/O Pad
Via
comp
PLA
I/O
Metal2
Metal1
RAM
A/D
(standard
cell design)
[©Sherwani]
ASIC (Standard Cell) Design Example
VDD
Metal1
D
GND
Metal2
C
C
C
A
Cell library
B
C
B
A
C
Cell
D
D
C
C
C
D
C
B
B
Placement [©Sherwani]