Download EE 4345 Lecture

EE 4345 - Semiconductor
Electronics Design Project
Spring 2002 - Lecture 26
--draft-Professor Ronald L. Carter
[email protected]
http://www.uta.edu/ronc/
L26 04/18/02
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Fig 5.10* Simplified ic Class B output stage
• Q1 (npn) and Q2 (pnp),
are a complementary
pair  b1 = b2
• Q1 off if
IL 
Vi < VbeOn
• Q2 off if
Vi > -VbeOn
Dead zone: IL = 0 if
-VbeOn < Vi < VbeOn
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Fig 5.11* Transfer Characteristic of the
Class B Stage
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Fig 5.13* Class AB output stage. The gummel
diodes reduce crossover distortion.
• For all conditions,
IQFB is the minimum curr. to for.
bias Q3 and Q4
• IQ > IB1 + IQFB
• For Vi > -Vbe2,
Q1 cond. the est.
currents are as
shown 
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IFB
IB1
IC1 = b IB1
IC1max ~
(VCC-Vcesat)/RL
IL
Ii
IB1
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Fig 5.14* Transfer characteristic of the
circuit of Fig 5.13
Q1 conducting 
Q2 cond. 
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Fig 5.13* Class AB output stage. Q2
conducting
• For Vi < -Vbe2,
• Q2 cond. the estimated currents
are as shown 
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IFB
IB1
IL
Ii
IB1
IC2 = b IB2
IC1max ~
(VCC-Vcesat)/RL
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Fig 5.15* Voltage and
current waveforms for
Class B output stage
(a) Input voltage
(b) Output voltage
(c) Q1 collector
current
(d) Q2 collector
current
hmax = p(VCC-VCEsat)
4VCC
< 78.6%
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Fig 5.16* Load line for one device in a Class B
stage
Tj-Tamb = (IpkVpk/4)*Rth, (Note: Both
devices dissipate IpkVpk/4)
, (for this device conducting)
Pmax,RL = VCC2/2RL
Load line for other
device conducting
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Fig 5.20a* Simplified schematic of the 741
output stage
See Group Project
Optimize current,
voltage gain, fT
Use Cadence to cap.
schematic, set bias,
etc. and generate
outputs
Q17 inverts input
-- biased by Q13B (c.m.)
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Fig 5.20b* 741
incl. Q18 and Q19
Q18 and Q19 are biased
by Q13A (a current
mirror)
Q14 and Q20 are biased
by R19 and
AQ18,Q19/AQ14, AQ20
chosen so comp. Q14
Q23 drives output as low
res follower
Q17 inverter drives Q23
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Vo (V)
Q13 sat, so Vomax =
VCC-VCE13Asat-Vbe14
Vi < 0 
Q17 inverts Vi so V1
rises so V2 & Vo
follow w/Q23 & Q14
Vi > 0 
Q17 sat, so Vomin =
-VCC+VCE17sat-Vbe23-Vbe20
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Fig 5.21* SPICEgen. transf. Char.
VCC = 15 V, RL = 1k
Vi (V)
Q17 inverts Vi so
V1 goes < 0 so
V2 & Vo follow
w/Q23 & Q20
sinking thru RL
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Fig 5.22* All npn Class B output stage
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Fig 5.23* Transfer char of Fig. 5.22
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References
*
Analysis and design of analog integrated circuits,
4th ed., by Gray, Hurst, Lewis and Meyer, Wiley,
New York, ©2001.
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