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MIXED SIGNAL MODELING AND PHYSICAL
LAYOUT DESIGN OF A SIMPLE FPGA WITH
VERILOG-AMS AND SCHEMATIC TOOL
A Thesis Submitted
By
1. BISWAS, RICHARD VICTOR
ID: 12-20789-1
2. HOSSAIN,MD.SAJJAD
ID: 12-20184-1
3. NAWAL, NAFISA
ID: 11-19632-3
4. EHSAN, SM.EKRAMUL
ID: 12-20706-1
Under the Supervision of
Shahriyar Masud Rizvi
Assistant Professor
American International University - Bangladesh
Department of
Electrical and Electronic Engineering
Faculty of Engineering
Summer Semester 2014-2015,
July, 2015
American International University - Bangladesh
MIXED SIGNAL MODELING AND PHYSICAL LAYOUT DESIGN
OF A SIMPLE FPGA WITH VERILOG-AMS AND SCHEMATIC
TOOL
A thesis submitted to the Electrical and Electronic Engineering Department of the Engineering Faculty,
American International University - Bangladesh (AIUB) in partial fulfillment of the requirements for the
degree of Bachelor of Science in Electrical and Electronic Engineering.
1. BISWAS,RICHARD VICTOR
ID: 12-20789-1
2. HOSSAIN,MD.SAJJAD
ID: 12-20184-1
3. NAWAL,NAFISA
ID: 11-19632-3
4. EHSAN,SM.EKRAMUL
ID: 12-20706-1
Department of
Electrical and Electronic Engineering
Faculty of Engineering
Summer Semester2014-2015,
July, 2015
American International University - Bangladesh
DECLARATION
This is to certify that this thesis is our original work. No part of this work has been submitted elsewhere
partially or fully for the award of any other degree or diploma. Any material reproduced in this project has
been properly acknowledged.
Students’ names & Signatures
1. BISWAS,RICHARD VICTOR
___________________
2. HOSSAIN,MD.SAJJAD
____________________
3. NAWAL,NAFISA
____________________
4. EHSAN,SM.EKRAMUL
____________________
© Faculty of Engineering, American International University-Bangladesh (AIUB)
i
APPROVAL
The Project titled “MIXED SIGNAL MODELING AND PHYSICAL LAYOUT DESIGN OF A SIMPLE
FPGA WITH VERILOG-AMS AND SCHEMATIC TOOL” has been submitted to the following
respected members of the Board of Examiners of the Faculty of Engineering in partial fulfillment of the
requirements for the degree of Bachelor of Electrical and Electronic Engineering on July, 2015 by the
following students and has been accepted as satisfactory.
1. BISWAS,RICHARD VICTOR
ID: 12-20789-1
2. HOSSAIN,MD.SAJJAD
ID: 12-20184-1
3. NAWAL,NAFISA
ID: 11-19632-3
4. EHSAN,SM.EKRAMUL
ID: 12-20706-1
__________________
Supervisor
Shahriyar Masud Rizvi
Assistant Professor
Faculty of Engineering
American International UniversityBangladesh
_________________
External Supervisor
Habib Muhammad Nazir Ahmad
Assistant Professor
Faculty of Engineering
American International UniversityBangladesh
__________________
Prof. Dr. ABM Siddique Hossain
Dean
Faculty of Engineering
American International UniversityBangladesh
__________________
Dr. Carmen Z. Lamagna
Vice Chancellor
American International UniversityBangladesh
© Faculty of Engineering, American International University-Bangladesh (AIUB)
ii
ACKNOWLEDGEMENT
First of all we would like to thank our creator for giving us the strength to complete our thesis work
successfully. After that we would like to express our sincere gratitude to our supervisor Mr. Shahriyar
Masud Rizvi, Assistant professor, Faculty of Engineering, American International University- Bangladesh
for his continuous support, patience and motivation. Without his support it would have been impossible
for us to complete the whole work. We are also extremely indebted to our external supervisor Mr. Habib
Muhammad Nazir Ahmad, Assistant professor, Faculty of Engineering, American International
University- Bangladesh for providing his valuable suggestions.
We express our appreciation to Dr. Md. Abdul Mannan, Head (Undergraduate program), Department of
Electrical and Electronic Engineering, for his support.
Furthermore, we would like to thank our honorable Dean of Faculty of Engineering Prof. Dr. ABM
Siddique Hossain and Dr. Carmen Z. Lamagna, Vice Chancellor, American International UniversityBangladesh for their encouragement and approving our thesis work.
Last but not the least we are really blessed to have our family and friends for providing continuous
motivation and support throughout our whole work.
1. BISWAS,RICHARD VICTOR
2. HOSSAIN,MD.SAJJAD
3. NAWAL NAFISA
4. EHSAN,SM.EKRAMUL
© Faculty of Engineering, American International University-Bangladesh (AIUB)
iii
TABLE OF CONTENTS
MIXED SIGNAL MODELING AND PHYSICAL LAYOUT DESIGN OF A SIMPLE FPGA WITH
VERILOG-AMS AND SCHEMATIC TOOL............................................................................................... I
DECLARATION ....................................................................................................................................... I
APPROVAL .............................................................................................................................................. II
ACKNOWLEDGEMENT ....................................................................................................................... III
LIST OF FIGURES .................................................................................................................................VII
LIST OF TABLE ......................................................................................................................................XI
ABSTRACT ............................................................................................................................................XII
CHAPTER 1 ................................................................................................................................................. 1
INTRODUCTION ........................................................................................................................................... 1
1.1. Introduction ................................................................................................................................ 1
1.2. Historical Background ................................................................................................................ 1
1.2.1. Earlier Research................................................................................................................................... 1
1.2.2. Recent Research .................................................................................................................................. 2
1.3.
Future Scope of This Study ........................................................................................................ 4
1.3.1. Future Scopes ...................................................................................................................................... 4
1.3.2. Recommendations ............................................................................................................................... 4
1.4.
1.5.
1.6.
Limitation of the Study ............................................................................................................... 5
Advantage over Traditional Method........................................................................................... 5
Objective of this Work ............................................................................................................... 5
1.6.1. Primary objectives ............................................................................................................................... 5
1.6.2. Secondary Objectives .......................................................................................................................... 6
1.7.
Introduction to this Thesis .......................................................................................................... 6
CHAPTER 2 ................................................................................................................................................. 7
MIXED SIGNAL CIRCUIT DESIGN WITH VERILOG-AMS ............................................................................. 7
2.1. Introduction to Mixed Signal System ......................................................................................... 7
2.1.1.
2.1.2.
2.1.3.
2.1.4.
2.2.
2.3.
Types of signals in Mixed Signal Circuit ............................................................................................ 7
Generic architecture............................................................................................................................. 8
FPGAs as a Mixed Signal Circuit........................................................................................................ 8
Abstraction level of Mixed Signal System .......................................................................................... 9
Introduction to design rules ...................................................................................................... 10
Introduction to Hardware Description Languages .................................................................... 12
2.3.1. Goal of HDLs .................................................................................................................................... 12
2.3.2. Modeling using HDLs ....................................................................................................................... 12
2.4.
Introduction to Verilog-AMS .................................................................................................. 12
2.4.1.
2.4.2.
2.4.3.
2.4.4.
2.5.
Evolution of Verilog-AMS ................................................................................................................ 12
Comparison of the three members of Verilog family ........................................................................ 13
Verilog –AMS simulators.................................................................................................................. 13
Applications of Verilog-AMS ........................................................................................................... 14
Effect of Verilog-AMS on simulation ...................................................................................... 14
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2.6.
Generating model using Verilog-AMS..................................................................................... 15
2.6.1. New keywords for analog version of verilog ................................................................................... 15
2.6.2. Analog modeling ............................................................................................................................... 16
2.6.3 Digital system modeling ...................................................................................................................... 19
2.7 Summary ........................................................................................................................................ 21
CHAPTER 3 ............................................................................................................................................... 22
TYPICAL FPGA ARCHITECTURE .............................................................................................................. 22
3.1. Introduction .............................................................................................................................. 22
3.2. Elements of FPGA .................................................................................................................... 22
3.2.1. Configurable logic block(CLB) ......................................................................................................... 23
3.2.1.1. Slice overview ........................................................................................................................... 24
3.2.1.2. Elements within a slice .............................................................................................................. 24
3.2.1.3. logic Cells .................................................................................................................................. 25
3.2.1.4. Look-Up Tables ......................................................................................................................... 25
3.2.1.5. Wide Multiplexers ..................................................................................................................... 26
3.2.2. Digital Clock Managers ..................................................................................................................... 26
3.2.3. DCM Functional Overview ............................................................................................................... 26
3.2.3.1. Delay-Locked Loop(DLL .......................................................................................................... 27
3.2.3.2. Digital Frequency Synthesizer (DFS)........................................................................................ 27
3.2.3.3. Phase Shift(PS) .......................................................................................................................... 27
3.2.4. IOB Overview ................................................................................................................................... 28
3.2.4.1. General-Purpose of I/O .............................................................................................................. 28
3.2.4.2. paths of IOB .............................................................................................................................. 30
3.2.4.3. Configurable I/O standards ........................................................................................................ 30
3.2.5. Block RAM ....................................................................................................................................... 30
3.2.5.1. Arrangement of RAM Blocks.................................................................................................... 31
3.2.5.2. The Internal Structure of the Block RAM ................................................................................. 31
3.2.5.3. Differences of Block RAM in Spartan-3 Generation Families.................................................. 32
3.2.5.4. Block RAM Routing Interaction ............................................................................................... 33
3.2.5.5. Data Flows ................................................................................................................................. 33
3.3.
Summary ................................................................................................................................... 33
CHAPTER 4 ............................................................................................................................................... 34
ADC AND DAC MODELING WITH VERILOG-AMS ................................................................................... 34
4.1. Introduction .............................................................................................................................. 34
4.2. Modeling an Analog to Digital Converter (ADC): ................................................................... 35
4.3. Modeling an Digital to Analog Converter(DAC) ..................................................................... 41
4.3.1. Verilog-AMS Code of Digital to Analog module (dac.vams) ........................................................... 42
4.4.
Summary ................................................................................................................................... 45
CHAPTER 5 ............................................................................ ERROR! BOOKMARK NOT DEFINED.
CLOCK MANAGEMENT UNIT .............................................................. ERROR! BOOKMARK NOT DEFINED.
5.1. Introduction .............................................................................. Error! Bookmark not defined.
5.2. The Phase Locked Loop (PLL) ................................................ Error! Bookmark not defined.
5.2.1. Phase-Frequency Detector (PFD)&Charge-Pump (CP) ..................... Error! Bookmark not defined.
© Faculty of Engineering, American International University-Bangladesh (AIUB)
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Second Ordered Low-Pass Filter (LPF) ......................................................... Error! Bookmark not defined.
5.2.2. Voltage-Controlled Oscillator (VCO) ................................................ Error! Bookmark not defined.
5.2.3. Frequency Divider (FB) ..................................................................... Error! Bookmark not defined.
5.2.4. DC Voltage &Clock Pulse.................................................................. Error! Bookmark not defined.
5.2.5. Top Level of PLL ............................................................................... Error! Bookmark not defined.
5.2.6. Analysis of Result............................................................................... Error! Bookmark not defined.
5.3.
The Delay Locked Loop (DLL) ................................................ Error! Bookmark not defined.
5.3.1.
5.3.2.
5.3.3.
5.3.4.
5.3.5.
5.3.1.
Phase Detector (PD) ........................................................................... Error! Bookmark not defined.
Delay Line .......................................................................................... Error! Bookmark not defined.
4-bit Synchronous UP/DOWN Counter ............................................. Error! Bookmark not defined.
Serial In-Parallel Out Shift Register ................................................... Error! Bookmark not defined.
Top Level of DLL .............................................................................. Error! Bookmark not defined.
Results ................................................................................................ Error! Bookmark not defined.
5.4.
Summary ................................................................................... Error! Bookmark not defined.
CHAPTER 6 ............................................................................................................................................... 72
MODELING SOME DIGITAL COMPONENTS OF FPGA USING VERILOG-AMS ........................... 72
6.1. Introduction .................................................................................................................................. 72
6.2. Configurable Logic Block (CLB) ................................................................................................. 73
6.3. Programmable Interconnection..................................................................................................... 79
6.4. Summary ....................................................................................................................................... 90
CHAPTER 7 ............................................................................................................................................... 91
MIXED SIGNAL MODELING OF A SIMPLE FPGA ARCHITECTURE.............................................................. 91
7.1. Introduction .................................................................................................................................. 91
7.2. Simple FPGA Model .................................................................................................................... 91
7.2.1 Verilog-AMS code of simple FPGA using LUT, ADC and DAC ....................................................... 92
7.3. Summary ....................................................................................................................................... 92
CHAPTER 8 ............................................................................................................................................... 93
DISCUSSIONS AND CONCLUSIONS ............................................................................................................. 93
REFERENCES ........................................................................................................................................... 95
© Faculty of Engineering, American International University-Bangladesh (AIUB)
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LIST OF FIGURES
FIGURE 1.1: DIAGRAM SHOWING THE COMPONENTS OF A MIXED SIGNAL FPGA…….... ..... 3
FIGURE 1.2: ULTRA SCALE FPGAS [15] ................................................................................................ 3
FIGURE 2.1: DIFFERENT TYPES OF SIGNALS [1] [6] .......................................................................... 8
FIGURE 2.2: INTERNAL COMMUNICATIONS WITHIN A MIXED SIGNAL SYSTEM. [2] ............. 8
FIGURE 2.3: ARCHITECTURE OF SPARTAN3 FPGA SHOWING ANALOG AND DIGITAL
BLOCKS [7] .......................................................................................................................................... 9
FIGURE 2.4: ABSTRACTION LEVEL HIERARCHIES [2] ................................................................... 10
FIGURE 2.5: TYPICAL TOP-DOWN DESIGN FLOW FOR MIXED SIGNAL DESIGN. [3] .............. 11
FIGURE 2.6: RELATIONSHIP BETWEEN VERILOG-AMS,VERILOG-A AND VERILOG-HDL[1] 13
FIGURE 2.7: INTERRELATIONSHIP OF MODEL AND SIMULATOR[2].......................................... 14
FIGURE 2.8: A SIMPLE CIRCUIT [1] ..................................................................................................... 18
FIGURE 3.1: BLOCK DIAGRAM OF A TYPICAL FPGA[28] .............................................................. 22
FIGURE 3.2: ARRANGEMENT OF SLICES WITHIN THE CLB[28] ................................................... 24
FIGURE 3.3: DCM FUNCTIONAL BLOCK DIAGRAM[28] ................................................................. 26
FIGURE 3.4: GENERAL-PURPOSE OF I/O BANKS[26] ....................................................................... 28
FIGURE 3.5 : SIMPLIFIED IOB DIAGRAM[28] .................................................................................... 29
FIGURE 3.6: BLOCK RAM DATA PATHS[27] ...................................................................................... 31
FIGURE 4.1: BLOCK DIAGRAM OF AN XADC (FPGA INCLUDING ADC)[23] .............................. 34
FIGURE 4.2: CIRCUIT DIAGRAM OF A FLASH ADC ......................................................................... 35
FIGURE 4.3: WAVEFORM OF ANALOG TO DIGITAL CONVERTERS USING VERILOG-AMS .. 39
© Faculty of Engineering, American International University-Bangladesh (AIUB)
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FIGURE 4.4: PHYSICAL LAYOUT OF AN ADC. .................................................................................. 40
FIGURE 4.5: WAVEFORM OF AN FLASH ADC ................................................................................... 41
FIGURE 4.6: DIGITAL TO ANALOG CONVERTER WITH BINARY-WEIGHT INPUTS. ................ 42
FIGURE 4.7: WAVEFORM OF DIGITAL TO ANALOG CONVERTER USING VERILOG-AMS. ... 44
FIGURE 4.8: LAYOUT OF A DAC . ....................................................................................................... 44
FIGURE 4.9: WAVEFORM OF DAC LAYOUT . ................................................................................... 45
FIGURE 5.1: BLOCK DIAGRAM OF PHASE LOCKED LOOPERROR!
BOOKMARK
NOT
DEFINED.
FIGURE 5.2: PHASE-FREQUENCY DETECTOR (PFD)& CHARGE-PUMP (CP) ................ ERROR!
BOOKMARK NOT DEFINED.
FIGURE 5.3:
SECOND ORDERED LOW-PASS FILTER ERROR! BOOKMARK NOT DEFINED.
FIGURE 5.4:
VOLTAGE CONTROLLED OSCILLATOR ERROR! BOOKMARK NOT DEFINED.
FIGURE 5.5:
FREQUENCY DIVIDER .............................. ERROR! BOOKMARK NOT DEFINED.
FIGURE 5.6:
TOP LEVEL OF PLL .................................... ERROR! BOOKMARK NOT DEFINED.
FIGURE 5.7:
TRANSIENT ANALYSIS OF PLL USING VERILOG-AMS IN SMASH. ....... ERROR!
BOOKMARK NOT DEFINED.
FIGURE 5.8:
TRANSIENT ANALYSIS OF PLL [23] ....... ERROR! BOOKMARK NOT DEFINED.
FIGURE 5.9:
BLOCK DIAGRAM OF DELAY LOCKED LOOPERROR!
BOOKMARK
NOT
DEFINED.
FIGURE 5.10: PHASE DETECTOR (PD)............................. ERROR! BOOKMARK NOT DEFINED.
FIGURE 5.11: LAYOUT OF PHASE DETECTOR (PD) IN MICROWINDERROR!
BOOKMARK
NOT DEFINED.
© Faculty of Engineering, American International University-Bangladesh (AIUB)
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FIGURE 5.12: DELAY LINE ................................................ ERROR! BOOKMARK NOT DEFINED.
FIGURE 5.13: LAYOUT OF DELAY LINEIN MICROWINDERROR!
BOOKMARK
NOT
DEFINED.
FIGURE 5.14: SYNCHRONOUS UP/DOWN COUNTER .. ERROR! BOOKMARK NOT DEFINED.
FIGURE 5.15: LAYOUT OF SYNCHRONOUS UP/DOWN COUNTERIN MICROWIND..... ERROR!
BOOKMARK NOT DEFINED.
FIGURE 5.16: SERIAL IN - PARALLEL OUT SHIFT REGISTERERROR!
BOOKMARK
NOT
DEFINED.
FIGURE 5.17: LAYOUT OF SERIAL IN - PARALLEL OUT SHIFT REGISTER. .................. ERROR!
BOOKMARK NOT DEFINED.
FIGURE 5.18: TOP LEVEL OF DLL .................................... ERROR! BOOKMARK NOT DEFINED.
FIGURE 5.19: LAYOUT OF DLL......................................... ERROR! BOOKMARK NOT DEFINED.
FIGURE 5.20: SIMULATION RESULT OF DLL WHEN FREQUENCY OF BOTH INPUT AND
INTERNAL CLOCK IS 1GHZ IN DSCH ....................... ERROR! BOOKMARK NOT DEFINED.
FIGURE 5.21: SIMULATION RESULT OF DLL WHEN FREQUENCY OF INPUT CLOCK IS 0.5
GHZ AND INTERNAL CLOCK IS 1GHZ WITH LOCK SELECT HIGH IN DSCH ......... ERROR!
BOOKMARK NOT DEFINED.
FIGURE 5.22: SIMULATION RESULT OF DLL WHEN FREQUENCY OF INPUT CLOCK IS 0.5
GHZ AND INTERNAL CLOCK IS 1GHZ WITH LOCK SELECT LOW IN DSCH .......... ERROR!
BOOKMARK NOT DEFINED.
FIGURE 5.23: SIMULATION RESULT OF DLL WHEN FREQUENCY OF INPUT CLOCK IS 0.33
GHZ AND INTERNAL CLOCK IS 1GHZ WITH LOCK SELECT HIGH IN DSCH ......... ERROR!
BOOKMARK NOT DEFINED.
FIGURE 5.24: SIMULATION RESULT OF DLL WHEN FREQUENCY OF INPUT CLOCK IS 0.33
GHZ AND INTERNAL CLOCK IS 1GHZ WITH LOCK SELECT LOW IN DSCH .......... ERROR!
BOOKMARK NOT DEFINED.
© Faculty of Engineering, American International University-Bangladesh (AIUB)
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FIGURE 6.1: FPGA ARCHITECTURE. [19] ............................................................................................ 73
FIGURE 6.2: (A) A CLB HAVING FOUR BLES [20]. (B) BASIC LOGIC ELEMENT.[20] ................ 73
FIGURE 6.3: BLOCK DIAGRAM OF A LOOK UP TABLE. ................................................................. 74
FIGURE 6.4 : CLB DESIGNED FOR THIS THESIS. .............................................................................. 75
FIGURE 6.5 : WAVE FORM OF CLB SCHEMATIC USING DSCH. .................................................... 75
FIGURE 6.6: WAVE FORM OF CLB BLOCK USING VERILOG-AMS. ............................................ 78
FIGURE 6.7: LAYOUT OF CLB. .............................................................................................................. 79
FIGURE 6.8: IMPLEMENTATION OF BIG FUNCTION USING SMALL FUNCTION[19]. .............. 80
FIGURE 6.9: FOUR CLASSES OF FPGA ARCHITECTURE. [28] ........................................................ 80
FIGURE 6.10: BLOCK DIAGRAM OF A ISLAND BASED ROUTING ARCHITECTURE. ............... 81
FIGURE6.11 : PROGRAMMABLE ROUTING SWITCH.......................................................................81
FIGURE 6.12 : A SMALL BLOCK OF ROUTING SWITCH ................................................................ 82
FIGURE 6.13: WAVEFORM OF A SMALL BLOCK OF ROUTING SWITCH USING VERILOG-AMS
................................ ............................................................................................................................. 84
FIGURE 6.14: LAYOUT OF A SMALL BLOCK OF ROUTING SWITCH USING MICROWIND. .... 85
FIGURE 6.15: COMBINATION OF FOUR ROUTING SWITCHES. ..................................................... 86
FIGURE 6.16 : A ROUTING CONNECTION BLOCK. .......................................................................... 87
FIGURE 6.17: WAVEFORM OF A SMALL BLOCK OF A CONNECTION BLOCK USING
VERILOG-AMS. ................................................................................................................................. 89
FIGURE 6.18: LAYOUT OF A CONNECTION BLOCK. ....................................................................... 89
FIGURE
6.19.
IMPLEMENTATION
OF
A
LOGIC
FUNCTION
USING
CLB
AND
PROGRAMMABLE INTERCONNECTION. .................................................................................... 90
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FIGURE 7.1:
MODEL OF A SIMPLE FPGA ........................................................................................ 91
LIST OF TABLE
TABLE 2.1: effect of SPICE and behavioral model (Verilog-AMS) of different components of PLL on
CPU time...............................................................................................................................................14
TABLE 2.2: Code for Simple Circuit....................................................................................................17
TABLE 2.3: Code for Series RLC Circuit.............................................................................................19
TABLE 2.4: Verilog-HDL code for an inverter......................................................................................20
TABLE 2.5: Verilog-AMS code for digital component...........................................................................20
TABLE 3.1: Block RAM Available in Spartan-3 Generation FPGAs .......................................................31
TABLE 3.2: Comparison between Spartan-3/3E, Spartan-3A/3AN, and Spartan-3A DSP FPGA Block
RAMs...........................................................................................................................................................32
TABLE 4.1: Verilog-AMS Code of Analog to digital converter..........................................................36
TABLE 4.2: Verilog-AMS Code of voltage source.............................................................................37
TABLE 4.3: Verilog-AMS Code of Resistor......................................................................................38
TABLE 4.4: Verilog-AMS code of a top level ADC circuit.................................................................38
TABLE 4.5: Verilog-AMS Code of Digital to Analog module...........................................................42
TABLE 4.6: Verilog-AMS code of a top level DAC circuit.................................................................43
TABLE 5.1: Verilog-AMS code for Phase-Frequency Detector & Charge-Pump....................................48
TABLE 5.2: Verilog-AMS code for Second Ordered Low-Pass Filter..................................................50
TABLE 5.3: Verilog-AMS code for Voltage-Controlled Oscillator.......................................................51
© Faculty of Engineering, American International University-Bangladesh (AIUB)
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TABLE 5.4: Verilog-AMS code for Frequency Divider.......................................................................52
TABLE 5.5: Verilog-AMS code for DC Voltage................................................................................54
TABLE 5.6: Verilog-AMS code for Clock Pulse (manual)........................................................................54
TABLE 5.7: Verilog-AMS code for Top level of PLL...............................................................................56
TABLE 6.1: Verilog-AMS code of a CLB..................................................................................................75
TABLE 6.2: Verilog-AMS code of the test bench of LUT...................................................................76
TABLE 6.3: Verilog-AMS code of a small block of Routable Switch Block...........................................82
TABLE 6.4: Verilog-AMS code of the test bench of a small block of Routable Switch Block.................82
TABLE 6.5: Verilog-AMS code of a Complete Routable Switch Block...............................................84
TABLE 6.6: Verilog-AMS code of a connection block.......................................................................86
TABLE 6.7: Verilog-AMS code of the testbench of a connection Block...............................................87
TABLE 7.1: Verilog-AMS code of a connection block........................................................................91
ABSTRACT
FPGAs have become one of the dominant implementation technologies for digital circuits today. Even
though FPGAs are digital in nature, due to the presence of clock management units (and in some cases
ADCs and DACs), which are generally analog in nature, FPGA architectures are mixed signal circuits to
be precise. We modeled logic cells and interconnect in Verilog and ADC, DAC and Phase Locked Loop
(PLL) for clock management in Verilog-AMS (mixed signal version of Verilog) using the free VerilogAMS simulator SMASH (from Dolphin Integration). Initially we wanted physical layout to be generated
from AMS models. However, the academic IC615 tool from CADENCE available at the university does
not support AMS languages. That is why, we eventually had to model these individual components (both
digital and mixed signals) using schematic tools such as DSCH3.5. Physical layouts for these components
were generated using Microwind 3.5. Due to tool limitations and time constraints, we could not simulate
or generate layout for the whole FPGA, but we were very close and future thesis groups are welcome to
accomplish this remaining task.
© Faculty of Engineering, American International University-Bangladesh (AIUB)
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© Faculty of Engineering, American International University-Bangladesh (AIUB)
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Chapter 1
Introduction
1.1. Introduction
Since 1985, with the invention of first commercially viable Field Programmable Gate Arrays by
the cofounder of Xilinx the importance of FPGA is still following the rising trend. [8] The
evolution of FPGA in digital electronics have replaced semi-custom IC design in many
applications due to the flexibility FPGA offers to the designers to reprogram their own logic
functions within few minutes. The decrease in cost with increase in speed of FPGAs has
provided an additional advantage to the designers. [9] Recently, FPGAs are playing a vital role
in digital signal processing (FFT- Fast Fourier Transform, FIR-Finite Impulse Response filters
and Converters) as they are suited for high speed Parallel multiply and accumulate functions.
[10]
1.2. Historical Background
In the history PROMs were the first programmable logic devices from Harris and Monolithic
Memories. Later, FPLA (Field Programmable Logic Array) was introduced by Monolithic
Memories. In FPLAs, bipolar fusible links were used. Birkner and Chua at the Monolithic
Memories invented the PAL architecture that replaced the traditional TTL method for
implementing logic functions. Later on GAL was introduced as an improved version of PAL.
These devices were erasable either electrically or by the exposure to UV light[11]. Larger scale
PLDs were introduced by Atmel and Lattice semiconductors. These large scale PLDs were
termed as CPLDs. The term SPLDs was used to distinguish the PALs and GALs from CPLDs.
Last of all is the largest programmable device FPGAs. These are manufactured by
Altera and
Xilinx [12].
1.2.1. Earlier Research
FPGA research works originated from the work in late 1960s and early 1970s on cellular array.
This work was mainly on how to improve the fault tolerances of logic structures, thus allowing
the whole silicon wafers to be used to implement logic. Important early work in this area was
© Faculty of Engineering, American International University-Bangladesh (AIUB)
1
done by Manning [Mann77], Minnick [Minn64], Wahlstrom [Wahl67], and Shoup [Shoup70]. A
good survey article of the early research appears in [Minn67] [11].
The first FPGA was released by Xilinx in 1985 the XC-2064.1990s were an explosive time for
FPGA because of the growth of several competitors in market share during the mid 90s[13].
In the early years of Mixed Signal system modeling, Verilog-A was used to model the analog
components. It is an extension of Verilog-HDL and Spectre. Verilog-HDL was used to design
Digital components. Initially Verilog-A was compatible for SPICE-class circuit simulation
engines. As a result designers had to model the analog and digital blocks separately. Hence,
complexity used to arise during interconnections of the MS system.
1.2.2. Recent Research
Modern FPGAs are entire programmable systems on SoC. They are suited for wide range of
applications.
The two recent FPGAs from Altera and Xilinx are Altera Stratix III and Xilinx Virtex-5. They
have 65 nm copper interconnect. Though features have changed drastically but the basic
architecture did not change in that rate. Earlier FPGAs had four input LUTs whereas Stratix-III
has seven input and Virtex-5 has six input LUTs. Nowadays embedded blocks are extensively
used in FPGAs to improve delay, reduce power consumption and improve area. The multipliers
that were previously present have been replaced by DSP blocks which support logical operations,
shift, addition and complex multiplication. [18]
The recent Xilinx FPGA family comprises of low cost and high performance Spartan 3
generation and the 7 series families which also consist of analog mixed signal technology, Artix7, Kintex-7 and Virtex-7[14].
© Faculty of Engineering, American International University-Bangladesh (AIUB)
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Figure 1.1 Diagram showing the components of a mixed signal FPGA. [14]
Figure 1.1 shows that a Mixed Signal FPGA consists of ADCs with digitally customizable
analog interface and programmable logic.
The most recent FPGA family in Xilinx is the ultra-scale+ FPGA 3-D IC families.3-D ICs have
enabled large memory capacities by stacking the memories in layers. The memory can be
accessed by high bandwidth vertical interconnect. If FPGAs are integrated with the 3-D memory
where FPGAs will be used as reconfigurable logic layers then that FPGAs are termed as 3-D
memory integrated FPGAs. [15]
Figure 1.2 Ultra scale FPGAs. [15]
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Microsemi were probably the first manufacturers who developed Mixed signal FPGAs. The
recent Fusion Mixed Signal FPGAs have soft microcontroller cores such as ARM Cortex-M1,
programmable analog interface with ADC, 1.5 million gates and 292 analog and digital IO pins
[17].
The recent analog HDL family is comprised of Verilog-AMS, VHDL-AMS, System VerilogAMS and System C-AMS. However, only VHDL-AMS has been certified by IEEE. VerilogAMS, the member of Verilog family evolved in the year 2000. However due to delays VerilogAMS remains at Accellera while Verilog-HDL became System Verilog and became IEEE
standard [16].
1.3. Future Scope of This Study
In this thesis we have tried to generate the layout of a FPGA having a simple architecture. This
study can be further improved by taking more complex logic blocks and clock managers in other
words more complex architecture into account. With the help of proper software the simulations
and the layout can be generated in a more effective way within a short period of time.
1.3.1. Future Scopes
Other than the presence of ADCs and DACs analog filter can be added as an analog
component.
Further studies can be carried out on analog filters as this plays a major part in mixed
signal
FPGAs. Extensive studies can be continued to analyze the analog HDLs adaptability to
the designers.
1.3.2. Recommendations
Our thesis can be extended to complete simulation and layout of a mixed signal FPGA
using industrial EDA like CADENCE software.
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1.4. Limitation of the Study
We modeled and simulated almost all parts of a sample FPGA but could not integrate them and
simulate the whole FPGA ( or generate complete layout).
Lack of access to the full version of open source software mainly “SMASH” made it difficult for
us to simulate large complex circuits having greater than 15 signals. Student version of
CADENCE software did not support layout generation from mixed signal circuit. So, later on
part of the design (that is the clock management unit and LUT) was done in schematic using
DSCH. This software can only deal with digital circuits. DSCH is unable to provide us with the
analog characteristic curve. As a result we were able to generate the layout of the digital blocks
only from the DSCH schematic using Microwind.
1.5. Advantage over Traditional Method
Traditional method means SPICE based simulation for analog components and Verilog based
simulation for digital components. Designing complex mixed signal system is a challenging task.
Spice –based simulation provides highest accuracy but is too slow to handle the system level
verification. Verilog-AMS reduces modeling complexity and simulation time by describing
analog circuits at behavioral level. It simplifies mixed signal system design by raising the level
of abstraction beyond circuit level in analog domain, making it compatible with the behavioral
level of abstraction in digital domain. In order to overcome the simulation based verification
challenges for large MS system, mixed level simulation at behavioral level is getting popular.
1.6. Objective of this Work
The objective is subdivided into two parts mainly Primary objectives and secondary objectives.
1.6.1. Primary objectives
The primary objective of our work is
a) Model the main components of a simple FPGA block such as the Delay Locked Loop
(DLL), ADCs, DACs, Configurable Logic Blocks(CLBs) , Look up Tables (LUTs) and
Programmable Interconnect( PI) using Verilog-AMS.
b) Verify the model using test benches in Verilog-AMS simulator (SMASH).
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c) Make interconnections and cascade the blocks to generate the layout using Virtuoso
Layout Editor from CADENCE.
1.6.2. Secondary Objectives
If possible, the verified layout is to be sent to a Silicon foundry for fabrication
1.7. Introduction to this Thesis
In chapter one, we have discussed about the importance and the trend of FPGAs starting from
1985 till now. The historical background of Verilog-AMS was also discussed. This chapter also
covered the advantages of our work over traditional method and future scopes that our work will
provide.
In chapter two, we discussed about mixed signal system in details and the importance of VerilogAMS on mixed signal modeling. At the end of this chapter some codes of basic components have
been discussed.
In chapter three, the architecture of a typical FPGA have been described. The Xilinx and Altera
family is compared but Spartan 3 member of the Xilinx family is discussed in details.
Chapter four deals with the modeling of ADCs and DACs using Verilog-AMS. It contains brief
description about the converters and the Verilog- AMS codes along with the simulated outputs
are described.
Chapter five is all about the Clock Management Unit. This unit has two parts Phase Locked
Loop (PLL) and Delay Locked Loop (DLL). In this chapter the verilog-AMS codes of PLL and
their simulated result have been discussed. The schematic diagram of DLL along with the layout
has been shown there.
In chapter six, we have designed the digital components of FPGA(CLBs and PI) using verilogAMS. The Verilog-AMS codes and their corresponding simulated outputs are described.
The last chapter is chapter six and it contains the overall view of our work and concludes with
the final result.
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Chapter 2
Mixed Signal Circuit Design with Verilog-AMS
2.1. Introduction to Mixed Signal System
The term “Mixed Signal” refers to a system that has both digital and analog components
processing digital and analog signals. In this chapter we have discussed about designing the
Mixed Signal system using behavioral description through analog Hardware Description
Language (HDLs) such as Verilog –AMS that supports both analog and digital domain design
[1].
2.1.1. Types of signals in Mixed Signal Circuit
As stated above Mixed Signal system contains digital signals that are discrete in time and
discrete in value. They have two discrete levels commonly known as HIGH and LOW or TRUE
and FALSE or logic level ‘1’ and logic level’0’. On the other hand, analog signals that are
mainly continuous in time and continuous in value. Simplest form of an analog signal is a
sinusoidal wave.
Another type of signal called discontinuous signals discrete in time &
continuous in value is also present in a mixed signal system [1].
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Figure 2.1
Different types of signals. [1] [6]
2.1.2. Generic architecture
The generic architecture of mixed analog-digital systems being integrated into one IC, which is
known
as the System-on-a-Chip (SoC) style, which can consist of DSP cores and microcontrollers
surrounded by A/D and D/A converters, which interface the internal bulk of digital processing to
the analog sources and sinks of external information [2].
Figure 2.2 Internal communications within a Mixed Signal System. [2]
2.1.3. FPGAs as a Mixed Signal Circuit
Even though FPGAs are considered purely digital circuits, they do contain small analog
components such as PLL or DLL (digital clock managers). Modern FPGAs that are used for
signal processing (DSP) have ADCs and DACs which are also analog in nature. Phase- locked
loop (PLL) contains Analog multiplier (phase detector) and loop components like VCOs and
LPF that are analog in nature. Hence PLL is also called APLL. ADCs (flash ADC) typically
comprise of analog components like comparators (Op Amps) and resistors that are analog.
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Similarly the simple DACs are constructed by using summing amplifiers (adder) and resistor
pairs. Therefore DACs are also constituted of analog components.
Figure 2.3 Architecture of Spartan3 FPGA showing analog and digital blocks. [7]
2.1.4. Abstraction level of Mixed Signal System
The abstraction hierarchy of mixed signal system is divided into two levels Functional and
Behavioral classes. Functional model class is divided into two levels Conceptual and Analytical
[2].
Conceptual: this level uses temporal logic and some flow calculus to specify the functionality.
However, the impact of this level on mixed signal modeling is not yet clear.
Analytical: As conceptual level in a sense is not applicable for mixed signal system, therefore
the topmost level of functional class is analytical level. This also addresses functionality but by
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using idealized analytical equations for continuous signal and abstract processing for discrete
signals.
Behavioral model is divided into three sub levels. Algorithmic, Procedural and Component.
Algorithmic: this type of behavioral model usually exploits acausal modeling concept for
continuous signals that are conservation laws and causal or acausal representations of event
processing algorithms. Both the behavior and data flow are processed in algorithmic level.
Procedural: this level refines the algorithmic model into modules. The modules represent either
the model entities of available building blocks or processing units.
Component: the component level is a direct representation of structural net lists of circuits
composed from primitive components like transistors or logic gates.
Figure 2.4 Abstraction level hierarchies. [2]
2.2. Introduction to design rules
Top- Down design rules are followed while designing as it offers a wide range of advantages
over Bottom- Up design. A well designed top-down process begins with architecture and ends
with transistor level design. It acts to partition the whole complex system into smaller well
defined blocks so that more designers can work simultaneously reducing the total time required
to complete the design. While doing so it also improves communications among designers
ensuring less number of flaws that might creep into the design because of miscommunication.
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Top-down methodology also provides flexibility to the designers so changes can me made late in
the design cycle without any effect[1].
Analog behavioral models and RTL are used at the top of the design process, to establish systemlevel behavior. Using these models designers verify the system. The mixed signal system is also
validated. These ensure that the problems are identified early in the design process which will
minimize any potential complications in the downstream. Then, functional blocks are translated
into transistor level designs. And simulations are carried out in SPICE. Once the transistor level
blocks are verified using test benches, layouts are created and post-layout simulations are done
for further verification and testing. Analog behavioral models are recalibrated against the
transistor level implementations using post-layout data[4].
Figure 2.5 Typical Top-Down design flow for Mixed Signal design. [3]
There are two major problems in modeling a Mixed Signal design. Firstly, the design tools that
are applicable for analog and digital domain designing are different so they must have to “talk to
each other”. Secondly, the Top-Down design methodology that has been proven adequate in
digital system design needs to be adopted in the mixed signal domain [2].
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2.3. Introduction to Hardware Description Languages
In the subsequent subtopics we have about the goal of Hardware Description Languages and how
to model a system using HDLs to solve the problem of slower simulation run time.
2.3.1. Goal of HDLs
Hardware description languages exist to describe hardware. To properly describe the hardware,
the language must be able to define the behavior of individual components as well as the
interconnections that exist among them. Hardware description languages have two applications
Simulation and Synthesis. Simulation will help to understand the behavior of the circuit
beforehand. So that time and expense are not wasted in implementation. Synthesis is the process
of actually implementing the hardware. This means that HDLs are just a way of describing the
components at an abstract level that do not yet have a physical implementation. The goal for
HDLs used in simulation is expressiveness whereas for synthesis it is changed to reliability. As
Mixed Signal systems are becoming more complex it is not feasible and practical to design
without abstraction [1].
2.3.2. Modeling using HDLs
As the size and complexity of on chip subsystems are increasing it is impossible to rely on
SPICE simulations only for verification of on chip systems.
There are two possible solutions for this problem. One solution is to use a Fast Spice simulator.
Here shorter run times are achieved by automatic simplification of transistor models and possibly
partitioning the whole circuit into subsystems where sub simulations may run in parallel. The
most popular alternative is to use HDLs which will raise the abstraction level of simulation
above the transistor level reducing simulation run time [5].
2.4. Introduction to Verilog-AMS
In the following subsections we have discussed about the historical background of Verilog-AMS,
how this language evolved and became a new member of the Verilog family. We have made
comparison among the three members and explained in brief how the Verilog-AMS simulator
differs from logic simulator or circuit simulator. Lastly we have stated the applications of this
language.
2.4.1. Evolution of Verilog-AMS
The Verilog-HDL is still the most popular language for describing complex digital hardware. It
started life as a proprietary language but was donated by Cadence Design Systems to the design
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community to serve as the basis of an open standard. That standard was formalized in 1995 by
the IEEE in standard 1364-1995. At about the same time a group named Analog Verilog
International was formed to provide extensions to support analog and mixed signal simulation.
Hence in 1996 Verilog-A was released .Initially, Verilog-A was not compatible to work directly
with Verilog-HDL. As more implementations of Verilog-A started to emerge the group
continued their work releasing the definition of Verilog-AMS in 2000. Later on Version 2.1 was
released in 2003 [1].
2.4.2. Comparison of the three members of Verilog family
The three members of Verilog family are Verilog-HDL, Verilog-A and Verilog-AMS.
Verilog –HDL allows the description of digital components and Verilog-A deals with the
description of analog .Verilog-AMS has a diverse range of capabilities because it allows the
description of mixed signal components. There are currently two competitors for describing
mixed signal hardware Verilog-AMS and VHDL-AMS. Verilog-A is designed to allow modeling
system that process continuous time signals but it is not so efficient in handling systems that
process other types of signal. Verilog-AMS is more straightforward in writing behavioral models
for mixed signal blocks. Blocks like ADCs, DACs PLLs etc. are very easily modeled using
Verilog-AMS [1].
Figure 2.6 Relationships between Verilog-AMS, Verilog-A and Verilog-HDL [1].
2.4.3. Verilog –AMS simulators
Mixed-signal simulators will combine two different methods of simulation that means it will
work as logic simulators and circuit simulators. They have two kernels named as discrete-event
kernel and continuous–time kernel. VERILOG AMS provide a single standard input language
that supports mixed-signal descriptions, and is based on the standard languages used by logic
simulators.
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There are two types of mixed signal simulator. a) Integrated and b) Glued.
Integrated approach combines two established simulators whereas the glued approach adds an
event-driven kernel to an established circuit simulator (continuous –time driven kernel) [1].
Figure 2.7 Interrelationship of model and simulator [2].
2.4.4. Applications of Verilog-AMS
The five main applications of Verilog-AMS are stated as follows:
a)To model components, b) to create test benches, c) to accelerate simulation d) to verify mixedsignal systems and e) to support the top-down design process.[1]
2.5. Effect of Verilog-AMS on simulation
Table 2.1: Effect of SPICE and behavioral model (Verilog-AMS) of different components of
PLL on CPU time [3].
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Table 2.1shows that behavior modeling using Verilog-AMS makes simulations faster compared
to SPICE models. The simulation speed of any circuit is inversely proportional to the number of
SPICE components present in that circuit. The greater the number of components means more
time is needed to run the simulation. However, simulation speed is also dependent on other
factors like switching activity. When a component with significant switching activity is replaced
by its behavioral model, there is a great improvement in simulation speed. But replacing smaller
components having small amounts of switching activity may not give faster performance, and in
one case, actually the speed is reduced [3].
2.6. Generating model using Verilog-AMS
The following subsections have been used to introduce the most basic keywords that are new for
verilog –AMS and then this language have been used to model analog and digital systems.
2.6.1. New keywords for analog version of verilog [5][1]
A) real- real is a parameter type in Verilog-AMS. Real signifies number of infinite extent. It is
an abstract mathematical representation. But as described by IEEESTD-754-1985 real variables
are stored as 64 bits. (Double precision floating point numbers). The precision and range
degrades from real to floating point to fixed point to integer. Real numbers can be specified in
either decimal notation or scientific notation.
B )electrical: Verilog-AMS deals with both analog and digital signals. So, electrical keyword is
used to represent the signal in continuous domain that is to differentiate electrical from the
default logic discipline.
This implies that
// electrical is a discipline of domain continuous.
discipline electrical
domain continuous;
enddiscipline
C)analog - keyword is used define an analog process. It is an analog process that is used to
describe continuous time behavior. Syntactically, it is the analog keyword followed by a
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statement that describes the relationship between signals. [1] Analog is a procedural block that
can only contain analog statements and operators.
D) branch- This keyword is used to describe the path between two nets.
E) discipline- Verilog –AMS is a multidiscipline language. Discipline is a collection of related
signal types.eg- discipline electrical, discipline logic.
F) domain- domain keyword is used to represent the type of signals behavior corresponding to
its discipline such as electrical discipline consists of continuous domain whereas logic discipline
contains the discrete domain.
G) ddt– This operator computes the time derivative of its argument. In other words, it is
differentiation operator.
H)idt- It integrates the argument that is provided.
I) genvar-This keyword is used for generating integer variables for looping. This variable can
only be used inside the for loop. This keyword is also available in Verilog-2001 and onwards.
J) $abstime- returns absolute time that is a real valued number in seconds.
K) absdelay() implements the absolute transport delay for continuous waveforms.
2.6.2. Analog modeling
‘disciplines.vams’ is a file that contains the collection of common disciplines and nature. ` with
the keyword include means that it is a preprocessor directory. The basic building blocks of
Verilog-A/MS are modules. Modules are descriptions of individual components. In VerilogA/MS modules are a block of statements that begin with the keyword module, which is then
followed by the name of the module and the list of ports. The statement is terminated with a
semicolon. A parameter is specified for the module using the parameter statement. If the
parameter value is not defined during instantiation then a default value of zero is set. Ports are
the points where connections can be made to the component .The keyword inoutrepresents the
port direction. There are three directions possible, input, output, and bidirectional as designated
by the input, output, and inout keywords. Each port should be given a direction. The net is
characterized by the discipline it follows. Then to describe the behavior formulae are applied
inside the analog block. In Verilog-AMS the symbol <+ is equivalent to = operator. The code
ends with the endmodule keyword.
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Simple examples of behavioral and structural descriptions:
Table 2.2: Code for Simple Circuit
Code for Simple Circuit
// DC voltage source
` include“disciplines.vams”
module vsrc (p, n);
parameter real dc=0; // dc voltage (V)
output p, n;
electrical p, n;
analog
V(p,n) <+ dc;
endmodule
// Linear resistor (resistance formulation)
`include“disciplines.vams”
module resistor (p, n);
parameter real r=0; // resistance (Ohms)
inout p, n;
electrical p, n;
analog
V(p,n) <+ r* l(p,n);
endmodule
//A simple circuit
`include“disciplines.vams”
`include“vsrc.vams”
`include“resistor.vams”
module smpl_ckt;
electrical n;
ground gnd;
vsrc #(.dc(1)) V1(n, gnd);
resistor #(.r(1k)) R1(n, gnd);
endmodule
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Figure 2.8 A simple circuit [1]
As discussed earlier, the code begins with the keyword Module, here the functional block is
resistor so, the module is named such. Inside bracket the ports are mentioned to be p and n.
Module resistor (p, n);
Then the parameter is specified for the module as
parameterreal r=0;
The types of ports p, n are defined as inout. Afterwards the discipline is declared to be electrical.
Here resistance formulation that is V=I×R.
is used inside the analog procedural block. In the
same way conduction formulation could be used.
The second code represents the model of a constant DC source.
The simple circuit code is the top-level circuit code that used both the resistor and DC source
model to represent the structural model of the circuit. So along with the discipline file the
resistance and DC source file is included. Electrical nodes are defined n and gnd. The circuit
itself is constructed by creating
instances of predefined modules, wiring them together by connecting them to nodes, and
specifying parameters for them. This is done for the voltage source and the resistor in the
following two lines.
vsrc #(.dc(1)) V1(n, gnd);
resistor #(.r(1k)) R1(n, gnd);
In a similar manner the behavioral code for a series RLC circuit can be generated as given
below.
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Table 2.3: Code for Series RLC Circuit
Code for Series RLC Circuit
// Series RLC
`include“disciplines.vams”
module series_rlc (p, n);
parameter real r=0;
parameter real l=0;
parameter real c=1p exclude 0;
inout p, n;
electrical p, n;
analog begin
V(p,n) <+ r*l(p,n);
V(p,n) <+ l*ddt(l(p,n));
V(p,n) <+ idt(l(p,n))/c;
end
endmodule
To begin with, the” disciplines.vams” file is included. The series RLC module is defined. The
parameters of type real are given a default value. The direction and type of the port is stated.
Afterwards the analog formulae for resistor, inductor and capacitor are stated in the analog block
and the loop ends with end keyword. As usual the endmodule is also used to terminate the
code.[1]
2.6.3 Digital system modeling
Disciplines are a concept that is not a part of Verilog-HDL. But discipline concept was first
introduced in Verilog-Aand later it continued to Verilog-AMS. As Verilog-AMS deals with both
analog and digital signals so it is optional for digital signals so that Verilog-HDL models can be
used by a Verilog-AMS simulator without any modification.
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Table 2.4: Verilog-HDL code for an inverter [1].
Verilog-HDL code for an inverter
module inverter (q, a);
output q;
input a;
wire a, q; // digital net type (declaration optional)
assign q=~a;
endmodule
The default discipline is logic which is stored in the discipline.vams file as given below
discipline logic
domain discrete;
enddiscipline
Analog signal values are represented in continuous time domain, whereas digital signal values
are represented in discrete time domain. The domain attribute of the discipline stores this
property of the signal. It takes two possible values, discrete or continuous[5].
Table 2.5: Verilog-AMS code for digital component
Verilog-AMS code for digital component
`include“disciplines.vams”
module inverter (q, a);
output q;
input a;
wire a, q; // digital net type (declaration optional)
logic a, q;
assign q = ~a;
endmodule
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2.7 Summary
To sum up verilog-AMS is an extended version of verilog-HDL that supports both analog and
digital semantics. The single unified language provides backward compatibility. For certain
reasons, like to speed up the simulation time or to make the runtime faster, behavioral modeling
with HDLs such as Verilog-AMS for complex Mixed Signal System is playing a significant role
in the design process. The designing part is an iterative process, until or unless the specifications
or design requirements are met, model components are refined and customized. After several
steps the prototype results. The simulations are carried out in SMASH and tested or validated
using test benches. Part of the design is done in schematic using DSCH. Layout is created from
DSCH schematic.
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Chapter 3
Typical FPGA Architecture
3.1. Introduction
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a
customer or a designer after manufacturing .The FPGA configuration is generally specified using
a hardware description language (HDL)
FPGAs contain an array of programmable logic block and a hierarchy of reconfigurable
interconnects that allow the blocks to be "wired together", like many logic gates that can be interwired
in
different
configurations. Logic
blocks can
be
configured
to
perform
complex combinational functions . In most FPGAs, logic blocks include memory elements, it's
may be simple flip-flops or more complete blocks of memory [27].
Figure 3.1:Block diagram of a typical FPGA[28]
3.2. Elements of FPGA
The most popular two companies of FPGA are 'Xilinx' & 'Altera'. Xilinx FPGA has some
Configurable logic Block(CLB). In lieu of CLB Altera has logic Array Block(LAB)/ Adaptive
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Logic Modules(ALM) . In Xilinx, CLB has four SLICEs. In SLICE there are two logic cells(LC)
and each Logic Cell has 1 LUT, 1MUX & 1 flip-flop .
In Altera, there are some logic element(LE) in logic Array Block(LAB)/ Adaptive Logic
Modules(ALM). each Logic Element has 1 LUT, 1MUX & 1 flip-flop .
In a block diagram ,these description can be shown-
3.2.1. Configurable logic block(CLB)
The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing
synchronous as well as combinatorial circuits. Each CLB contains four slices, and each slice
contains two Look-Up Tables (LUTs) to implement logic and two dedicated storage
elements that can be used as flip-flops or latches. The LUTs can be used as a 16x1 memory
(RAM16) or as a 16-bit shift register (SRL16), and additional multiplexers and carry logic
simplify wide logic and arithmetic functions. Most general-purpose logic in a design is
automatically mapped to the slice resources in the CLBs. The details of the CLB resources
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are helpful when estimating the number of resources required for an application or when
optimizing a design to the architecture [28].
Figure 3. 2 : Arrangement of slices within the CLB[28]
3.2.1.1. Slice overview
Both SLICEM and SLICEL have the following elements1. Two 4-input LUT function generators, F and G
2. Two storage elements
3. Two wide-function multiplexers, F5MUX and FiMUX
4.Carry and arithmetic logic
The SLICEM pair supports two additional functions:
1. Two 16x1 distributed RAM blocks, RAM16
2. Two 16-bit shift registers, SRL16
3.2.1.2. Elements within a slice
All four slices have the following elements , two logic function generators, two storage elements,
wide-function multiplexers, carry logic, and arithmetic gates. Both the left-hand and right-hand
slice pairs use these elements to provide logic, arithmetic, and ROM functions. Besides these, the
left-hand pair supports two additional functions, storing data using Distributed RAM and shifting
data with 16-bit registers.
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The RAM-based function generator—also known as a Look-Up Table or LUT—is the main
resource for implementing logic functions. Furthermore, the LUTs in each left-hand slice pair
can be configured as Distributed RAM or a 16-bit shift register.
The storage element, which is programmable as either a D-type flip-flop or a level-sensitive
latch, provides a means for synchronizing data to a clock signal, among other uses. The storage
elements in the upper and lower portions of the slice are called FFY and FFX, respectively.
Wide-function multiplexers effectively combine LUTs in order to permit more complex logic
operations. Each slice has two of these multiplexers with F5MUX in the lower portion of the
slice and FiMUX in the upper portion. Depending on the slice, FiMUX takes on the name
F6MUX, F7MUX, or F8MUX.
The carry chain, together with various dedicated arithmetic logic gates, support fast and efficient
implementations of math operations. The carry chain enters the slice as CIN and exits as COUT.
Five multiplexers control the chain: CYINIT, CY0F,and CYMUXF in the lower portion as well
as CY0G and CYMUXG in the upper portion. The dedicated arithmetic logic includes the
exclusive-OR gates XORG and XORF (upper and lower portions of the slice, respectively) as
well as the AND gates GAND and FAND (upper and lower portions, respectively)[28].
3.2.1.3. logic Cells
The combination of a LUT and a storage element is known as a “Logic Cell”. The additional
features in a slice, such as the wide multiplexers, carry logic, and arithmetic gates, add to the
capacity of a slice , implementing logic that would otherwise require additional LUTs
Benchmarks have shown that the overall slice is equivalent to 2.25 simple logic cells.
3.2.1.4. Look-Up Tables
The Look-Up Table or LUT is a RAM-based function generator and is the main resource for
implementing logic functions. Each of the two LUTs (F and G) in a slice have four logic inputs
(A1-A4) and a single output(D). Any four-variable Boolean logic operation can be implemented
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in one LUT. Functions with more inputs can be implemented by cascading LUTs or by using the
wide function multiplexers.
3.2.1.5. Wide Multiplexers
Wide-function multiplexers combine LUTs in order to permit more complex logic operations.
Each slice has two of these multiplexers with F5MUX in the bottom portion of the slice
anFiMUX in the top portion. The F5MUX multiplexes the two LUTs in a slice. The FiMUX
multiplexer has two CLB inputs which are connected directly to the F5MUX and FiMUX results
from the same slice or from other slices.
3.2.2. Digital Clock Managers
Digital Clock Managers (DCMs) provide advanced clocking capabilities to Spartan-3 generation
FPGA applications. DCMs integrate advanced clocking capabilities directly into the FPGA’s
global clock distribution network. Consequently, DCMs solve a variety of common clocking
issues, especially in high-performance and high-frequency applications.
3.2.3. DCM Functional Overview
Digital Clock Manager (DCM) consists of four distinct functional which is shown in the
simplified diagram-
Figure 3.3 :DCM Functional Block Diagram[28]
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3.2.3.1. Delay-Locked Loop(DLL
The Delay-Locked
Loop (DLL) provides
an on-chip
digital
deskew circuit
that
effectively generates clock output signals with a net zero delay. The deskew circuit
compensates for the delay on the clock routing network by monitoring an output clock,
from either the DCM’s CLK0 or the CLK2X outputs. The DLL unit effectively eliminates
the delay from the external clock input port to the individual clock loads within the device.
The well-buffered global network minimizes the clock skew on the network caused by
loading differences. The input signals to the DLL unit are CLKIN and CLKFB. The output
signals from the DLL are CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and
CLKDV. The DLL unit generates the outputs for the Clock Doublers (CLK2X, CLK2X180), the
Clock Divider (CLKDV) and the Quadrant Phase Shifted Outputs functions[26].
3.2.3.2. Digital Frequency Synthesizer (DFS)
The Digital Frequency Synthesizer (DFS) provides a wide and flexible range of output
frequencies based on the ratio of two user-defined integers, a Multiplier(CLKFX_MULTIPLY)
and a Divisor (CLKFX_DIVIDE). The output frequency is derived from the input clock
(CLKIN) by simultaneous frequency division and multiplication. The DFS feature can be used in
conjunction with, or separately from, the DLL feature of the DCM. If the DLL is not used, the
DFS output clocks will not be de-skewed because the DLL is required to provide the de-skew
feedback clock. The DFS unit generates the Frequency Synthesizer (CLKFX, CLKFX180)
outputs [26].
3.2.3.3. Phase Shift(PS)
The Phase Shift unit shifts the phase of all nine DCM clock output signals by a fixed fraction of
the input clock period. The fixed phase shift value is set at design time and loaded into the DCM
during FPGA configuration. If the DLL is not used, the DFS output clocks will not be de-skewed
because the DLL is required to provide the deskew feedback clock.
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3.2.4. IOB Overview
The Input /Output Block (IOB) provides a programmable, unidirectional or bi-directional
interface between a package pin and the FPGA’s internal logic. It supports a wide variety of
standard interfaces. The robust feature set, includes programmable control of output strength and
slew rate, registered or combinatorial inputs and outputs with dedicate double data rate (DDR)
registers, programmable input delays, on-chip termination, and hot-swap capability.
3.2.4.1. General-Purpose of I/O
To create special FPGAs to accommodate with all different variation, an FPGA’s general
purpose I/O can be configured to accept and generate signals conforming to whichever standard
is required. These general purpose I/O signals will be split into a number of banks. It will assume
eight such banks numbered from 0 to 7 .The interesting point is that each bank can be configured
individually to support a particular I/O standard. Thus, in addition to allowing the FPGA to work
with devices using multiple I/O standards, this allows the FPGA to actually be used to interface
between different I/O standards.
Figure 3. 4: General-Purpose of I/O banks[26]
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Simplified IOB Diagram is given below-
Figure 3.5 :Simplified IOB Diagram[28]
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3.2.4.2. paths of IOB
There are three main path s of IOB. The three are-
1. The input path, carries data from the pad, which is bonded to a package pin, through an
optional programmable delay element directly to the I line. After the delay element, there are
alternate routes through a pair of storage elements to the IQ1 andIQ2 lines. The IOB outputs I,
IQ1, and IQ2 lead to the FPGA’s internal logic
2. The output path, starting with the O1 and O2 lines. It carries data from the FPGA's internal
logic through a multiplexer and then a three-state driver to the IOB pad. In addition to this direct
path, the multiplexer provides the option to insert a pair of storage elements.
3. The 3-state path determines when the output driver is high impedance. The T1 and T2 lines
carry data from the FPGA’s internal logic through a multiplexer to the output driver. In addition
to this direct path, the multiplexer provides the option to insert a pair of storage elements.
3.2.4.3. Configurable I/O standards
To create special FPGAs to accommodate with all different variation, an FPGA’s general
purpose I/O can be configured to accept and generate signals conforming to whichever standard
is required. These general purpose I/O signals will be split into a number of banks. It will assume
eight such banks numbered from 0 to 7 .The interesting point is that each bank can be configured
individually to support a particular I/O standard. Thus, in addition to allowing the FPGA to work
with devices using multiple I/O standards, this allows the FPGA to actually be used to interface
between different I/O standards.
3.2.5. Block RAM
All Spartan-3 devices support block RAM, which is organized as configurable, synchronous
18Kbit blocks. Block RAM stores relatively large amounts of data more efficiently than the
RAM feature . (The latter is better suited for buffering small amounts of data anywhere along
signal paths.) This section describes basic Block RAM functions.
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3.2.5.1. Arrangement of RAM Blocks
The XC3S50 has one column of block RAM. The Spartan-3 devices ranging from the
XC3S200 to XC3S2000 have two columns of block RAM. The XC3S4000 and XC3S5000
have four columns. The position of the columns on the die is shown belowTable3.1 : Block RAM Available in Spartan-3 Generation FPGAs [28]
3.2.5.2. The Internal Structure of the Block RAM
The block RAM has a dual port structure. The two identical data ports called A and B permit
independent access to the common RAM block, which has a maximum capacity of 18,432 bits—
or 16,384 bits when no parity lines are used. Each port has its own dedicated set of data, control
and clock lines for synchronous read and write operations. There are four basic data paths, as
shown in Figure 3: (1) write to and read from Port A, (2) write to and read from Port B, (3) data
transfer from Port A to Port B, and (4) data transfer from Port B to Port A.
Figure 3. 6: Block RAM data paths[27]
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3.2.5.3. Differences of Block RAM in Spartan-3 Generation Families
Overall, block RAM is similar in all Spartan-3 generation FPGAs. However, Extended Spartan3A family FPGAs have some difference but significant block RAM enhancements over Spartan3E and Spartan-3 family FPGAs, as summarized in the table given belowTable 3.2: Comparison Between Spartan-3/3E, Spartan-3A/3AN, and Spartan-3A DSP FPGA
Block RAMs [28].
Feature
Spartan-3/3E
Spartan-3A/AN
FPGA
FPGA
Block RAM
Block RAM
Spartan-3A
DSP
FPGA
Block RAM
Individual write-enables No
for each byte
(single write-enable
Yes
Yes
lane in x9, x18, or x36 only)
configurations
Special routing resources
between block
RAM
General
and multiplier for x36
No
Yes
Purpose
configurations
Output register
No
No
Supported by RAMB16 Yes
Yes
primitive
Supported
Yes
Yes
by
RAMB16BWE
Yes
primitive(RAMB16 with
Yes
No
byte-level write enable)
Supported
by
RAMB16BWER
No
No
Yes
primitive(RAMB16BWE
with output register)
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3.2.5.4. Block RAM Routing Interaction
Each multiplier is located adjacent to an 18 Kbit block RAM and shares some interconnect
resources. In the Spartan-3 and Spartan-3E families, configuring an 18 Kbit block RAM
for32/36-bit wide data (512 x 36 mode) prevents use of the associated dedicated multiplier
because the lower 16 bits of the A multiplicand input are shared with the upper 16 bits of the
block RAM’s Port A Data input. Similarly, the lower 16 bits of the B multiplicand input are
shared with Port B’s Data input.
3.2.5.5. Data Flows
Sparten-3 generation Block RAM is constructed of true dual-port memory and simultaneously
supports all the Data flows and operations.
1. Port A behaves as an independent single-port RAM supporting simultaneous read and write
operations using a single set of address lines.
2. Port B behaves as an independent single-port RAM supporting simultaneous read and write
operations using a single set of address lines.
3. Port A is the write port with a separate write address, and Port B is the read port with a
separate read address. The data widths for Port A and Port B can also be different .
4. Port B is the write port with a separate write address, and Port A is the read port with a
separate read address. The data widths for Port B and Port A can also be different [Fig-3.6].
3.3. Summary
This chapter mainly focus on the FPGA architecture. Though there are many companies that
maintain FPGA the Xilinx's FPGA has been described in this chapter as a model. CLB,DCM,I/O
block, Block ram are the main components of FPGA. These elements have different task to
perform in FPGA. So, these topics have been described in this chapter .
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Chapter 4
ADC and DAC Modeling with Verilog-AMS
4.1. Introduction
Field-Programmable Gate-Arrays (FPGA) are well established for implementing programmable
digital logic. However, traditional manufactures did not used to integrate analog interfaces in
their device and all interfaces between FPGA and analog signal were done by means of ADC and
DAC. But recent FPGAs have implemented ADC and DAC on such digital chip for several
reasons, including cost, board space and reduced number of components.
ADC and DAC both are ideal analog mixed signal devices. These two devices are used for
converting the form of a signal (analog to digital or digital to analog) and FPGA are used for
performing deferent operations on the digitalized signal. In fig. 4.1 a block diagram of XADC in
the Xilinx 7 series FPGAs has been shown. It contains dual 12-bit, 1 Mega sample per second
(MSPS) ADCs. This ADC can access up to 17 external analog input channels and produce digital
outputs.
Simulation of a simple FPGA including ADC and DAC can be done using Verilog-AMS. In this
chapter the Verilog-AMS codes of ADC and DAC have been demonstrated. Later in chapter 7
these modules will be used for modeling a very simple FPGA.
Figure 4.1: Block diagram of an XADC (FPGA including ADC)[23]
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4.2. Modeling an Analog to Digital Converter (ADC):
An analog to digital converter is a device that converts a continuous time domain signal to digital
number. As we can see in fig. 3.2 a flash ADC contains several numbers of resisters,
comparators and a priority encoder. The number of resisters and comparators depends on the
number of bit of the ADC. If it is an 3- bits ADC eight resistors and seven comparators are
required (n-bits ADC requires 2n resistors and 2n -1 comparators). Resistors are used for
changing the level of reference voltage and comparators are used to compare input voltage with
different level of reference voltage. The priority encoder (MSB having higher priority) changes
the output of comparator to a binary value.[22]
Figure 4.2: Circuit diagram of a flash ADC
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Verilog-AMS code of a flash ADC is given below Table 4.1: Verilog-AMS Code of Analog to digital converter
Verilog-AMS Code of Analog to digital converter
`include "disciplines.vams"
`timescale 1ns / 1ps
module adc (out, in, clk);
parameter integer bits = 8 from [1:24];// Resolution (bits) , range form 0 to 24 ;
parameter real ref=4 ;
// Refference voltage has been cosidered as 4volts;
parameter real td = 10p;
input in, clk;
// 'in' and 'clk' has been decleared as input port;
output out;
voltage in;
// Delay from clock to output (ns)
// 'out' has decleared as output;
// 'in' port has been decleared as analog and its voltage will be used later;
reg [0:bits-1] plot_out;
reg [0:2] out;
// plot_out is an intermidiate digital signal;
// out is 'out' is a delecleared a digital port;
real sample, new_ref;
// 'sample' and 'new_ref' are two variable parameters;
integer i;
always @(posedgeclk)
begin
sample = V(in) // In any possitive edge of clock 'sample' will store the value of input
new_ref = ref*0.72; // value of ref has beeen reduced for fristcomperism;
for (i = 0; i<=7; i = i + 1)
//The comparism of 'sample' will be repeated for 8 times with seven diffrent values;
begin
if(sample >new_ref) //Compering 'sample' with new_ref;
begin
plot_out[i] <= #(td) 1;
sample = sample - new_ref// Reduction of ref. size;(what resistor does)
end
else
plot_out[i] <= #(td) 0;
end
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end
// Priority Encoder
always @ (plot_out)
begin
if
(plot_out[7]==1) out=3'b111; // Input:1XXXXXXX ; Output:111
else if (plot_out[6]==1) out=3'b110;//Input:01XXXXXX ; Output:110
else if (plot_out[5]==1) out=3'b101;//Input:001XXXXX ; Output:101
else if (plot_out[4]==1) out=3'b100;//Input:0001XXXX
; Output:100
else if (plot_out[3]==1) out=3'b011; //Input:00001XXX
; Output:011
else if (plot_out[2]==1) out=3'b010; //Input:000001XX
; Output:010
else if (plot_out[1]==1) out=3'b001; //Input:0000001X
; Output:001
else if (plot_out[0]==1) out=3'b000; //Input:00000001
;Output: 000
else plot_out =3'b000;
end
endmodule
For testing this ADC module we need a voltage source and a resistor. Using Verilog-AMS any
kind of analog voltage source can be generated. Verilog-AMS code of Sinusoidal Voltage source
has been given below.
Table 4.2: Verilog-AMS Code of voltage source.
Verilog-AMS Code of voltage source
`include "disciplines.vams"
`include "constants.vams"
module v_source(p, n);
inout p, n;
voltage p, n;
analog
V(p,n) <+ (10+6 * sin (`M_2_PI * 500 * $abstime));
Endmodule
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Table 4.3: Verilog-AMS Code of Resistor.
Verilog-AMS Code of Resistor
module res(p, n); // positive and negative connections on res
inout p;
inout n;
electrical p, n;
parameter real r=1;
//defining variable parameter for future operation; r cannot be 0
branch (p,n) resistor;
analog begin
I(p,n) <+ V(p,n)/r;
//defining current through res (conductance form, large r)(r>1)
end
endmodule
Veriog-AMS code of a complete ADC circuit with ADC module, voltage source and resistor is
given below-
Table 4.4: Verilog-AMS code of a top level ADC circuit.
Verilog-AMS code of a top level ADC circuit
`timescale 10ns / 10ps
`include "disciplines.vams"
module top ;
electrical gnd;
ground gnd;
reg clock;
wire [0:2] y;
initial clock=0;
always #10000 clock=~clock;
// generating clock pulse with period 10000ns;
adc
ADC_IC (.out(y),.in(x),.clk(clock));
v_source
INPUT (x,gnd);
res
R1 (y,gnd);
endmodule
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Waveforms of Analog to digital converters have been given below.
Figure 4.3: Waveform of Analog to Digital Converters using Verilog-AMS
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Physical layout of a flash ADC was generated using “Mricowind” . Layout of an ADC has been
shown below.
Figure 4.4 Physical layout of an ADC.
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Waveforms of this layout are shown below.
Figure 4.5: Waveform of an Flash ADC
4.3. Modeling an Digital to Analog Converter(DAC)
A DAC performs the opposite job of an ADC. It converts digital signal to analog signal. In fig.
3.4 a 4-bits DAC of binary-weighted input is represented .In this method of digital to analog
conversion a resistor network is used with resistance values that represents the binary weight of
the input bits of digital code. Each input resistor will either have current or no current. Each
resistor is connected to the input of op-amp. So the entire input current sum together and go
through Rf . Drop across Rf is equal to output, Vout =If Rf . The values of the input resistors are
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chosen to be inversely proportional to the binary weight to the corresponding input. The lowest
binary weight gets the highest resistor and the highest binary weight gets the lowest resistor [22].
Figure 4.6: Digital to Analog Converter with Binary-Weight inputs.
4.3.1. Verilog-AMS Code of Digital to Analog module (dac.vams)
Verilog-AMS code of a Binary-Weight inputs Digital to Analog Converter is given belowTable 4.5 : Verilog-AMS Code of Digital to Analog module.
Verilog-AMS Code of Digital to Analog module
`timescale 1ns / 1ps
`include "disciplines.vams"
module dac (out, in, clk);
parameter integer bits = 8 from [1:24];
// resolution (bits)
parameter real fullscale = 1.0;
// output range is from 0 to fullscale (V)
parameter real td = 0.0;
// delay from clock edge to output (s)
output out;
electrical out;
input logic [0:bits-1] in;
input logic clk;
real result, aout;
integer weight;
integer i;
always @(posedge clk)
begin
aout=0.0;
//At posedge Output has been set to be zero.
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weight = 2;
// Lowest resistor.
for (i=bits-1; i>=0; i=i-1)
// Counting will be done from LSB to MSB..
begin
if (in[i]) aout = aout + fullscale / weight; // Output will be updated for each count.
weight = weight * 2;
// resistance will increase with decreases of binary weight.
end
result = #(td / 1.0E-9) aout;
end
end
analog begin
V(out) <+ result;
end
endmodule
Verilog-AMs code of a complete Digital to Analog circuit is given below-
Table 4.6: Verilog-AMS code of a top level DAC circuit.
Verilog-AMS code of a top level DAC circuit
`include "constants.vams"
`include "disciplines.vams"
`timescale 10ps / 1ps
module testbench ();
reg clk;
reg [0:7] in
electrical out;
initial begin
clk=0;
in=0;
end
always #100 clk=~clk;
always #33 in=in+8'b00000001;
dac dac0 (.out(out), .in(in), .clk(clk));
endmodule
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The waveform of simulated Digital to Analog Converter has been given below.
Figure 4.7: Waveform of Digital to Analog Converter using Verilog-AMS.
Layout was generated using “Microwind”. The layout and waveforms of a Digital to Analog
converter are shown below.
.
Figure 4.8: Layout of a DAC .
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Figure 4.9 :Waveform of DAC layout .
4.4. Summary
Integrating ADC and DAC to the digital component of an FPGA has made an FPGA a truly
mixed signal processing device. A simple FPGA including ADC and DAC can be designed using
Verilog-AMS. In this chapter Verilog-AMS code of a flash ADC and a binary weight DAC has
been demonstrated. Beside these, layouts of ADC and DAC were also generated using
“Microwind”.
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Chapter 5
Clock Management Unit
5.1. Introduction
Since last few decades, VLSI system has taken tremendous advantage of semiconductor
manufacturing process by the help of continuous technological progress. The degree of
complexity and the clock frequency of VLSI circuits increase when high-speed system is
required. Aligning frequency of system clocks would be necessary for such synchronous VLSI
circuits. Suppressing the clock skew and jitter by clock tree synthesis in high-speed VLSI and
System-On-Chip (SoC) become very important because clock skew and jitter increase the total
clock phase error. Data may not be transmitted properly on exact rising or falling edge of the
clock if skew and jitter are being the parts of the clock. As, Setup time and hold time, data access
times, and accuracy of internal control signals are violated by clock skew, data might not be
latched [23].
In microprocessors and high-speed I/O interfaces i.e. Field Programmable Gate Arrays
(FPGA’s), clock skew problems can be eliminated by clock management circuits such as Phase
Locked Loops (PLL’s) and Delay-Locked Loops (DLL’s).Shifting, de-skewing, and frequency
synthesis functions are performed by typical Clock management circuits [23].
By adjusting an analog voltage, PLL controls the phase and frequency of the distributed clock
which is known as frequency synthesis [24].On the other hand, Jitter performance of DLL is
better than PLL as PLL aggregates phase error [24].
5.2. The Phase Locked Loop (PLL)
The Phase Locked Loop (PLL) is a feedback system which locks output clock frequency with
reference clock frequency by adding a voltage controlled oscillator and a phase detector. PLL is
often used to generate stable output frequency signals from a low frequency signal. The
difference in phase i.e. error signal between feedback signal and input signal produces by phase
detector and such error signal makes the phase of output clock aligned with the phase of input
reference clock [25]. Main Parts of PLL includes Phase Frequency Detector (PFD), Charge
Pump (CP), Low pass Filter of second order (LPF), Voltage controlled Oscillator (VCO) and
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frequency divider (FD). Simple block diagram of PLL is given below with the above mentioned
parts:
Figure 5.1
Block Diagram of Phase Locked Loop
5.2.1. Phase-Frequency Detector (PFD)&Charge-Pump (CP)
The Phase-Frequency Detector generates “UP” or “DOWN” signals if the frequency of
feedback clock is lagging or leading the reference input frequency. Current is passed to the
low pass filter if “UP” signal is received by charge pump and current is dragged from the
low pass filter if “DOWN” signal is received by charge pump [25]. By changing controlled
voltage and frequency in VCO, phase of the output clock can be matched with the input
reference clock.
Basically, phase frequency detector consisting of two d-flip flops, one generates “UP” signal
and another produces “DOWN” signal. “UP” signal goes high when input reference signal is
lagging and “DOWN” signal goes high when feedback divided signal is leading.
Charge Pump is consisted of current sources and two switches. Charge Pump passes current
to the low pass filter which is exactly proportional to the phase/frequency difference. The
circuit diagram and Verilog-AMS code of PFD/CP are given below:
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Schematic Diagram of Phase-Frequency Detector (PFD) & Charge-Pump:
Figure 5.2
Phase-Frequency Detector (PFD) & Charge-Pump (CP)
Table 5.1 Verilog-AMS code for Phase-Frequency Detector & Charge-Pump
Verilog-Ams code for Phase-Frequency Detector & Charge-Pump
`include "disciplines.vams"
`include "constants.vams"
module PFD_CP (out, ref, fb);
input ref; voltage ref;
input fb; voltage fb;
output out;
electrical out;
parameter real iout=100u;
// RATED CURRENT SOURCE IN CHARGE PUMP
parameter real vh=+1;
// UP VOLTAGE
parameter real vl=-1;
// DOWN VOLTAGE
parameter real vth=(vh+vl)/2;
// THRESHOLD VOLTAGE
parameter integer dir=1 from [-1:1] exclude 0;
parameter real tt=1p from (0:inf);
// DURATION OF OUTPUT TRANSITION (IF
//TRANSITION TIME IS LARGER THAN PICO RANGE(i.e. NANO,MICRO etc.), NOISE
//WILL BE ADDED TO THE PFD_CP_OUT)
parameter real td=0n from [0:inf);
// DELAY IS SET 0 TO GET THE EXACT
//FREQUENCY RESPONSE OF REFERENCE AND FEEDBACK SIGNALS
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integer state;
analog
begin
@(initial_step)
state=0;
@(cross(V(ref)- vth, dir))
if (state > -1)
//The cross function produces events when they detect a
//threshold crossing
// WHEN REFERENCE SIGNAL IS LEADING, DOWN
//SIGNAL GOES HIGH
state = state - 1;
@(cross(V(fb)- vth, dir)) // WHEN FEEDBACK SIGNAL IS LEADING, HIGH
//SIGNAL GOES HIGH
if (state < 1)
state = state + 1;
I(out) <+ transition( iout * (V(fb)-V(ref)), td, tt); // PRODUCE OUTPUT WITH WELL//CONTROLLED TRANSITION
//"transition" MUST BE FOUND WITHIN AN ANALOG
//PROCESS
// transition( constant piecewise waveform or operand, td, (tr, tf)
//or tt)
end endmodule
Second Ordered Low-Pass Filter (LPF)
To set average Voltage Controlled Oscillator (VCO) frequency, low pass filter derives the
current from charge pump to the C1 capacitor. Without affecting the average frequency, instant
phase correction can be done by the resistor used in the low pass filter. To smooth large
capacitor’s insulation resistance (IR) ripples on Vctl, the second capacitor is used [25]. The
circuit diagram and Verilog-AMS code of LPF are given below:
Schematic Diagram of Second Ordered Low-Pass Filter:
Figure 5.3
Second Ordered Low-Pass Filter
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Table 5.2
Verilog-AMS code for Second Ordered Low-Pass Filter
Verilog-AMS code for Second Ordered Low-Pass Filter
`include "disciplines.vams"
`include "constants.vams"
module LPF (vin, vout);
input vin;
output vout;
electrical vin, vout;
parameter real LPF_BW_GHz = 1000G from (0:inf];
// BANDWIDTH OF LOW
//PASS FILLER
real r1; real r2; real c1; real c2; real wc; // CUTOFF FREQUENCY (wc)
analog
begin
@( initial_step ("tran", "ac", "dc"))
//"ac", "dc", "noise" and "tran" analyses can
//be specified by initial_step event
begin
r1 = 1K;
// COMBINATION OF r1 & r2 IS "Res"
r2 = 1K;
wc = 2 * `M_PI *LPF_BW_GHz;
// CUT-OFF FREQUENCY, f = wc / 2 * pi
c1 = 1.59e-7;
// f = 1 / 2 * pi* RC
c2 = 1.59e-7;
end
V(vout, vin) <+ I(vout, vin) * r1;
// V =IR
V(vout, vin) <+ I(vout, vin) * r2;
I(vout) <+ ddt (V (vout) * c1);
I(vout) <+ ddt (V (vout) * c2);
end
endmodule
// ddt stands for differentiation &idt is integration
// current, I = C * d/dt (V) and voltage,V=(1/C)idt(I)
5.2.2. Voltage-Controlled Oscillator (VCO)
The Voltage-Controlled oscillator is divided into three main parts which are - Active circuit,
resonating circuit and feedback path. Main circuit of VCO is active circuit, which can be of
NMOS, PMOS or CMOS type depending on the applications. For, the VCO circuit of less
number of elements and low voltage, NMOS and PMOS configuration is widely used in active
circuit. For timing and frequency control circuit, the resonating circuit used in VCO comprises of
integrated inductors [25]. The circuit diagram and Verilog-AMS code of VCO are given below:
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Schematic Diagram of Voltage-Controlled Oscillator:
Figure 5.4
Table 5.3
Voltage Controlled Oscillator
Verilog-AMS code for Voltage-Controlled Oscillator
Verilog-AMS code for Voltage-Controlled Oscillator
`include "disciplines.vams"
`include "constants.vams"
module VCO (vin,vout);
input vin;
output vout;
electrical vin, vout;
parameter real amp = 1;
parameter real center_freq = 0.9G;
parameter real vco_gain = 1G;
parameter integer steps_per_period = 32;
real phase;
real inst_freq;
// INSTANTANEOUS
FRQUENCY
analog begin
inst_freq = center_freq + vco_gain * V(vin);
// kvco = (fi - fc) / vin
$bound_step (1.0 / (steps_per_period * inst_freq)); // The $bound_step function places
// bound on the size of the next time step.
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phase = idtmod (inst_freq, 0, 1);
V(vout)<+ amp * sin(2 * `M_PI * phase);
end endmodule
//itdmod (integrand, initial condition,
//modulus, offset, tolerance).
// Output of VCO
5.2.3. Frequency Divider (FB)
Frequency dividers are consisting of logic gates and flip flops. The frequency divider
using JK flip flop consist of three stages where the output of first stage is given to second
and second stage input and output is given to and gate; whose output is fed to the final
block. Each block of JK flip flop itself acts like a divide-by-2 circuit. In this type of
divider each stage changes at the clock edges. The circuit diagram and Verilog-AMS
code of VCO are given below:
Schematic Diagram of Frequency Divider:
Figure 5.5
Table 5.4
Frequency Divider
Verilog-AMS code for Frequency Divider
Verilog-AMS code for Frequency Divider
`include "disciplines.vams"
`include "constants.vams"
`timescale 10ps / 1ps
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module FD(q, clk, j, k);
input clk, j, k;
output q;
voltage q, clk, j, k;
parameter real tdelay = 0n from [0: inf),
ttransit = 0n from [0: inf),
vout_high = 1.0,
vout_low = 0 from (-inf: 1),
vth
= 0.5;
integer x;
analog begin
@(initial_step)
x = 0;
@(cross(V(clk) - vth, +1)) // The cross function produces events when they detect a
threshold crossing
begin
if (V(j) >vth&& V(k) >vth) // TOGGLE MODE (j = 1 & k = 1 ; q = TOGGLED O/P)
x = !x ;
else if (V(j) >vth&& V(k) <vth) // SET MODE (j = 1 & k = 0 ; q = SET O/P)
x = 1;
else if (V(j) <vth&& V(k) >vth) // RESET MODE (j = 0 & k = 1 ; q = RESET O/P)
x = 0;
else if (V(j) <vth&& V(k) <vth) // NO CHANGE (j = 0 & k = 0 ; q = NO CHANGE
//IN O/P)
x = x;
end
V(q) <+ transition (vout_high * x + vout_low * !x, tdelay, ttransit);
end
endmodule
5.2.4. DC Voltage &Clock Pulse
DC Voltage of 5v is used at J and K ports JK flip-flop. Also, Clock Pulse is created
manually to show the versatility of Verilog-AMS language. Verilog-AMS code of DC
Voltage and Clock Pulse are given below:
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Table 5.5
Verilog-AMS code for DC Voltage
Verilog-AMS code for DC Voltage
`include "constants.vams"
`include "disciplines.vams"
module VDC (p,n);
parameter real dc = 1; // dc voltage (V)
inoutp,n;
electrical p,n;
analog
V(p,n) <+ dc; endmodule
Table 5.6
Verilog-AMS code for Clock Pulse (manually created)
Verilog-AMS code for Clock Pulse (manually created)
`include "disciplines.vams"
`include "constants.vams"
`timescale 10ns / 1ps
module CLK_PULSE (p, n);
inout p, n;
electrical p, n;
parameter real val0 = 0;
//start value
parameter real val1= 1;
//end value
parameter real td = 2n;
//delay time
parameter real rise = 10p; //rise time
parameter real fall = 10p; //fall time
parameter real width= 2n;
//pulse width
parameter real period = 4n;
//period width
parameter real cycles = 1e100; //number of cycles
parameter real mag = 1.0;
//must be greater than 0 (integer only)
real t, t0, t1, t2, t3, t4, Vout;
real cnt = 0;
analog begin
t = $abstime;
//absolute time; real time in seconds during
simulation
t0 = td + cnt * period;
//starting time
t1 = rise+ td+ cnt * period;
t2 = width+ rise+ td+ cnt * period;
t3 = fall+ width+ rise+ td+ cnt * period;
t4 = td + (cnt + 1) * period;
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if (t <= t0) Vout = val0;
// VOLTAGE IS CONSTANT AT ZERO
else if( (t0 < t) && (t <= t1) )
Vout = val0 + (val1 - val0) * (t - t0) / rise;
// VOLTAGE IS RISING UPTO 5v
else if( (t1 < t) && (t <= t2) )
Vout = val1;
// VOLTAGE IS CONSTANT AT 5v
else if( (t2 < t) && (t <= t3) )
Vout = val1 + (val0 - val1) * (t - t2) / fall;
// VOLTAGE IS FALLING TILL ZERO
else if( (t3 < t) && (t <= t4) )
Vout = val0;
// VOLTAGE IS CONSTANT AT ZERO
else if (cnt< cycles)
cnt = cnt + 1;
//update after complete period is achieved
V(p,n) <+ Vout + ac_stim("ac", mag);
//AC SIMULATION: ac_stim
(analysisName, //magnitude, phase)
end
endmodule
5.2.5. Top Level of PLL
After Cascading Phase Detector, Low Pass Filter, Voltage Controlled Oscillator and
Frequency Divider, Phase Locked Loop is created. The overall circuit diagram and top
level Verilog-AMS code of Phase locked loop are given below:
Schematic Diagram of Top Level of PLL:
Figure 5.6
Top Level of PLL
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Table 5.7
Verilog-AMS code for Top level of PLL
Verilog-AMS code for Top level of PLL
`include "constants.vams"
`include "disciplines.vams"
`timescale 1ns / 1ps
module plltop ();
electrical gnd;
ground gnd;
// PARTITIONING OF INSTANCE STATEMENTS INTO THEIR COMPONENT
//PIECES
// MODULE_NAME # (PARAMETER_LIST) INSTANCE_NAME (NODE_LIST)
CLK_PULSE
PFD_CP
LPF
VCO
FD
VDC
VDC
endmodule
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CLK_IN (ref, gnd );
PFD_CP (PFD_CP_out, ref, fb);
LPF (PFD_CP_out, LPF_out);
VCO (LPF_out, VCO_out);
FD (fb, VCO_out, p1, p2);
VDC1 (p1, gnd);
VDC2 (p2, gnd);
56
5.2.6. Analysis of Result
Transient Analysis of Top Level of PLL:
Figure 5.7:
Transient Analysis of PLL using Verilog-AMS in SMASH.
From the Waveforms of each element of PLL, it is evident that frequency of Reference
Clock is lower than feedback divided clock. Also, 200mV can be denoted as “Up” and 200mV can be denoted as “DOWN” in PFD_CP_OUT waveform. At 1ns, reference
clock leads feedback clock. Therefore, “DOWN” signal passed. Between 1ns and 2ns, 0V
signal emerged because reference clock and feedback clock are in same phase. At this
very moment, Locking is being ensured by PLL. At 2ns, feedback clock leads reference
clock. Therefore, “UP” signal passed. VCO produces one analog signal and one digital
signal. Digital signal is fed to the FD and analog signal is passed to RF modules. Pulse
width and characteristic parameters of these two signals are different. Dividing the
frequency of digital clock signal makes pulse width of this signal equal to the analog
signal. When phase of reference clock and feedback clock is same, such phenomenon is
seen.
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Finally, approximately at 6.7ns feedback clock frequency and reference clock frequency
are same and from this point locking phase starts.
5.3. The Delay Locked Loop (DLL)
A DLL consists of a Phase Detector (PD), a Delay-line, and a DLL controller. PD passes phase
error signal to the DLL controller for sending digital control signal to the Delay line. The phase
error between reference clock and remote clock can be compensated by selecting an optimal
delay (Td). Propagation delay (Tc) of the clock buffer can be ignored after DLL is locked. The
lock condition is the following equation:
𝑲 ∗ 𝑻𝒓𝒆𝒇 = 𝑻𝒅 + 𝑻𝒄
Where K is a positive integer, Tref represents the clock period of the reference clock. Td and Tc
denote the delay time of delay line and clock buffer respectively [23]. When DLL is locked,
there is no phase error between reference clock and remote clock.
Figure 5.8:
Simple Block Diagram of DLL [23]
There are several types of DLL: Register controlled DLL, counter controlled DLL, successive
approximation register-controlled DLL, time to digital converter-based DLL, Mixed-Mode
Delay-Locked Loop etc.
Counter-controlled DLL is chosen in this paper for creating delay and phase shifting of the clock
to the remote distributed system.
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The Counter-controlled DLL comprises of Phase Detector (PD), N-bit UP/DOWN Counter and
Delay-line. According to the output error signal of phase detector, UP/DOWN counter changes
its value. The counter sends count signal into delay line until the output clock synchronizes with
input clock.
The block diagram of counter-controlled DLL [23] is shown below:
Figure 5.9
Block Diagram of counter-controlled Delay Locked Loop
5.3.1. Phase Detector (PD)
Phase Detector is composed of 2 D-flip flops and an AND gate. If reference clock leads
feedback clock, “UP” signal goes high. Conversely, if reference clock lags feedback
clock, “DOWN” signal goes high. When, reference clock and feedback clockare in phase,
AND gate resets both D-flip flops. The circuit diagram and layout of Phase Detector (PD)
are shown below:
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Schematic Diagram of Phase Detector (PD):
Figure 5.10
Phase Detector (PD)
Layout of Phase Detector (PD):
Figure 5.11
Layout of Phase Detector (PD) in Microwind
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5.3.2. Delay Line
Delay line can be created by bunch of D-flip flops and Multiplexers. Reference clock
feeds into the first D-flip flop and it successively transits to the last D-flip flop on every
rising edge of delay clock. Whenever, counter signals (AddDt) come across delay line,
each D-flip flop creates switching delay with the help of 2-to-1 mux. The circuit diagram
and layout of Delay Line are shown below:
Schematic Diagram of Delay Line:
Figure 5.12
Delay Line
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Layout of Delay Line:
Figure 5.13
Layout of Delay-Line in Microwind
5.3.3. 4-bit Synchronous UP/DOWN Counter
4-bit Synchronous UP/DOWN Counter comprises of four D-flip flops, four Full Adders
and one comparator for comparing whether UP signal is greater or less than DOWN
signal. Reset signal is automatically going to be high, at the moment of locking mode.
The circuit diagram and layout of 4-bit Synchronous UP/DOWN Counter are shown
below:
Schematic Diagram of 4-bit Synchronous UP/DOWN Counter
Figure 5.14
Synchronous UP/DOWN Counter
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Layout of Synchronous UP/DOWN Counter:
Figure 5.15
Layout of Synchronous UP/DOWN Counter in Microwind
5.3.4. Serial In-Parallel Out Shift Register
Serial in-Parallel out Shift Register shifts phase of the output clock by 90֯, 180֯, 270֯.
These shifted clocks are passed to the distant configurable logic blocks (CLB’s).The
circuit diagram and layout of Serial in-Parallel out Shift Register are shown below:
Schematic Diagram of Serial in-Parallel out Shift Register
Figure 5.16
Serial in - Parallel out Shift Register
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Layout of Serial in - Parallel out Shift Register:
Figure 5.17
Layout of Serial in - Parallel out Shift Register.
5.3.5. Top Level of DLL
External clock (Cin) and feedback clock from different distant CLB’s are fed into Phase
Detector to check the phase error between them. Phase error signals i.e. UP/DOWN; are
passed to UP/DOWN synchronous counter. Having phase error signals from external
clock and feedback clock, UP/DOWN synchronous counter produces binary data signals
that are decoded by 4-bit decoder. Later, Decoded signal is sent to the delay line to create
delay. Outputs of delay line are passed to the distributed network by 16-to-1 MUX. An
XNOR gate is used to observe the locking state by considering external clock and
distributed clocks. Preceding stage of XNOR gate is an OR gate with the inputs of high
logic and output of XNOR. Arrangement of this stage is done for locking external clock
with distributed clocks while glitches encounter in the 0֯ phase shift of output clock.
Finally, Serial in-Parallel out Shift Register shifts 0֯ phase shift of output clock by 90֯,
180֯, 270֯.
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Schematic Diagram of Top Level of DLL:
Figure 5.18
Top Level of DLL
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Layout of whole DLL:
Figure 5.19
Layout of DLL
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5.3.1. Results
Case-1
At locked condition:

Frequency of input clock = 1 GHz

Internal clock frequency = 1 GHz
Figure 5.20
Simulation result of DLL when frequency of both input and internal clock is
1GHz in DSCH
In this case, frequency of input clock and internal clock is same. Thus, CLK_OUT_0 is
exactly equal to the Cin. This is known as lock state.
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Case-2

Frequency of input clock = 0.5 GHz

Internal clock frequency = 1 GHz

Lock Select – HIGH
Figure 5.21
Simulation result of DLL when frequency of input clock is 0.5 GHz and internal
clock is 1GHz with Lock Select high in DSCH
In this case, frequency of input clock and internal clock is not same and lock select is high .
Thus, CLK_OUT_0 is not equal to the Cin. As a result, glitch appears in CLK_OUT_0. To
get rid of this, next case should be considered.
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Case-3

Frequency of input clock = 0.5 GHz

Internal clock frequency = 1 GHz

Lock Select – LOW
Figure 5.22
Simulation result of DLL when frequency of input clock is 0.5 GHz and internal
clock is 1GHz with Lock Select low in DSCH
In this case, frequency of input clock and internal clock is not same and lock select is low.
Thus, CLK_OUT_0 is not equal to the Cin. At this time, glitches do not appear in
CLK_OUT_0 because DLL passes external clock (Cin) directly to the CLK_OUT_0 and
only then lock state arisen.
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Case-4

Frequency of input clock = 0.33 GHz

Internal clock frequency = 1 GHz

Lock Select - HIGH
Figure 5.23
Simulation result of DLL when frequency of input clock is 0.33 GHz and internal
clock is 1GHz with Lock Select high in DSCH
In this case, frequency of input clock and internal clock is not same and lock select is high .
Thus, CLK_OUT_0 is not equal to the Cin. As a result, glitch appears in CLK_OUT_0. To
get rid of this, next case should be considered.
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Case-5

Frequency of input clock = 0.33 GHz

Internal clock frequency = 1 GHz

Lock Select – LOW
Figure 5.23
Simulation result of DLL when frequency of input clock is 0.33 GHz and internal
clock is 1GHz with Lock Select low in DSCH
In this case, frequency of input clock and internal clock is not same and lock select is low.
Thus, CLK_OUT_0 is not equal to the Cin. At this time, glitches do not appear in
CLK_OUT_0 because DLL passes external clock (Cin) directly to the CLK_OUT_0 and
only then lock state arisen.
5.4. Summary
In Field Programmable Gate Unit (FPGA), clock management unit i.e. Phase Locked Loop or
Delay Locked Loop plays a vital role in synchronizing clocks and generating clocks. Design,
analysis, simulation and making layout of these were our target to be accomplished. Designing
and making layout were completed using DSCH 3.5 and MICROWIND 3.5, respectively.
Simulation was solely done by Dolphin Integration SMASH – a mixed-signal multi-language
simulator.
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Chapter 6
Modeling Some Digital Components of FPGA using Verilog-AMS
6.1. Introduction
Field Programmable Gate Array (FPGA) is a programmable electronic device that allows users
to implement any digital logic systems. A typical FPGA contains billions of logic blocks which
are connected through a reconfigurable routing system. This routing system is used for wiring
the logic blocks together to constitute user defined combination or sequential circuits. Another
important part of an FPGA is programmable interconnection which is employed to interface the
logic blocks and routing architectures to the wide range of external components to FPGA. Beside
these, modern FPGAs have been developed through the addition of some special block such as
Block RAM, multiplier. All of these reconfigurable components of an FPGA are digital in
nature.[20]
Generally, a logic block contains some memory cells (SRAM), multiplexers and flip-flops and
the programmable routing system consists of multiplexers, pass transistors and tri-state buffers.
In this chapter we will design some of these two digital components of an FPGA using VerilogAMS.
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Figure 6.1: FPGA Architecture. [19]
6.2. Configurable Logic Block (CLB)
A configurable logic block (CLB) is the building block of an FPGA that provides basic logic
and storage functionality for target design. There are billions of CLBs integrated in an FPGA. In
general, a CLB consists of one or more logical cells called basic logic element (BLE). A CLB
can comprise of (BLE), or a cluster of interconnected BLEs. A simple BLE consists of a LUT,
and a Flip-Flop.
Figure 6.2: (a) A CLB having four BLEs [20]. (b) Basic logic element.[20]
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Look Up Table (LUT) is the core of a BLE. It contains some configurable memory cell and
multiplexer.A LUT with k inputs (LUT-k) contains 2kconfiguration bits and it can implement
any k-input Boolean function. An important characteristic of this component is its functionality.
A simple LUT can be used for implementing huge number of logic functions. For example, A
3
three input LUT has 23 (=8) memory cell and 22 (= 256)logic function of three inputs can be
implemented using this. [20]. In fig. 6.3 A block diagram of a 4 input LUT has been shown.
Figure 6.3: Block diagram of a Look Up Table.
In fig.6.4 schematic diagram of a three input has been LUT shown. It has 8 memory cell, for
configuring the memory cells a three bit counter and an external signal ‘we’(write enable) has
been used. If “we” is LOW data will be written to the memory cell which is highlighted by the
outputs of counter. For making the system auto configurable and synchronized to the serial
“data_in” the counter has been designed in such a way that it’s output will remain HIGH after
counting up to seven and ‘we’ will remain HIGH which will make the memory cell isolated
from the counter until restarting the system.
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Figure 6.4 : CLB Designed for this thesis.
Waveform of this schematic is given below.
Figure 6.5 : Wave form of CLB schematic using DSCH.
Verilog-AMS code of designed CLB is given below-
Table. 6.1: Verilog-AMS code of a CLB.
Verilog-AMS code of a CLB
‘include "disciplines.vams"
`include "constants.vams"
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`timescale 1 ns / 1 ps
module clb(clb_out,ff_sel,areset,clk,in_put,data_in);
input wire [2:0] in_put;
input wire data_in;
input wire clk,areset,ff_sel;
output regclb_out;reg [7: 0] Mem ;
reg [2: 0] count;
// output of counter
regwe,ff_out,mem_out; // we=write_enable;
// Enable signal selector
always @ (count or areset )
begin
we=count[0]&count[1]&count[2]; // when every bits of count is HIGHT , we will be HIGH.
end
// Counter;
always @ (posedgeclk, posedgeareset, posedge we)
begin
if (areset==1) // when asynchronus reset is HIGH every bits of counter will be LOW.
count<=3'b000;
else if (we) //Otherwise, when we is HIGH every bits of counter will be HIGH.
count <= 3'b111;
else if(clk) //Otherwise, at every pulse value of counter will increase by 1..
count<=count + 3'b001;
end
//RAM
always @(we or count or data_in)
begin
if (!we)
Mem[count] = data_in;
/* when we is HIGHT , selected bit of mem will store the value of Data_in. and the mem. Bit
will be selected by counter.*/
end
//MUX
always @(in_put or Mem)
begin
if (in_put==3'b000) mem_out=Mem[0];
else if (in_put==3'b001) mem_out=Mem[1];
else if (in_put==3'b010) mem_out=Mem[2];
else if (in_put==3'b011) mem_out=Mem[3];
else if (in_put==3'b100) mem_out=Mem[4];
else if (in_put==3'b101) mem_out=Mem[5];
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else if (in_put==3'b110) mem_out=Mem[6];
else if (in_put==3'b111) mem_out=Mem[7];
else mem_out=1'bz;
end
always @ (posedgeclk or posedgeareset)
begin
if (areset) ff_out<= 1'b0;
else if (clk) ff_out<= mem_out;
end
always @ (ff_sel or mem_out or ff_out)
begin
if (ff_sel==0) clb_out=mem_out;
else if (ff_sel==1) clb_out = ff_out;
end
endmodule
A testbench was generated for checking the accuracy of the CLB module. The verilog-AMS
code of the test bench is given below.
Table 6.2: Verilog-AMS code of the test bench of LUT.
Verilog-AMS code of the test bench of LUT
`include "disciplines.vams"
`timescale 1 ns / 1 ps
module CLB_TOP();
reg [2:0] in;
regreset,clock,din,ff_sel;
wire dout;
initial
begin
reset=1'b0;
clock=1'b1;
din=3'b000;
in=3'b111;
ff_sel=1'b0;
end
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always #10 clock=~clock;
always #20 din=~din;
always #40 in= in + 3'b001;
always #300 reset=~reset;
always #600 ff_sel=~ff_sel;
clb IC(.clb_out(dout),.ff_sel(ff_sel),.areset(reset),.clk(clock),.in_put(in),.data_in(din));
endmodule
The wave form of generated CLB module has been given below.
Figure 6.6: Wave form of CLB block using Verilog-AMS.
The layout of this CLB has been generated using “Microwind”.
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Figure. 6.7: Layout of CLB.
6.3. Programmable Interconnection
As discussed earlier, in an FPGA, the computing functionality is done by its logic blocks (In
fig.6.5 the implementation of a big function using small logic block has been shown) and these
blocks connect to each other through programmable routing network. This programmable routing
network provides routing connections among logic blocks and I/O blocks to implement any userdefined circuit. The routing interconnect of an FPGA consists of wires and programmable
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switches that form the required connection. These programmable switches are configured using
the programmable technology.
Figure 6.8 Implementation of big function using small function[19].
Commercial FPGAs can be classified into the four major groups, based on their routing
architecture.[28]
 Island – Style FPGA
 Row – Based FPGA
 Sea – Gates FPGA
 Hierarchical FPGA
Figure 6.9: Four classes of FPGA Architecture. [28]
Island- Style is a popular architecture among academic and commercial FPGAs. It is called
island-style architecture because in this architecture configurable logic blocks look like islands in
a sea of routing interconnect. In this architecture, configurable logic blocks (CLBs) are arranged
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on a 2D grid and are interconnected by a programmable routing network. The Input/Output (I/O)
blocks on the periphery of FPGA chip are also connected to the programmable routing network.
The routing network comprises of wiring segments and programmable switches that are
organized in horizontal and vertical routing channels.
Figure 6.10: Block diagram of a island based routing architecture.
An Island Based FPGA routing network consists of horizontal and vertical routing tracks which
are interconnected through routing switch. Logic blocks are connected to the routing network
through connection boxes. These two are also used making connection between I/O block and
internal components. Generally, the output pins of a block can connect to any routing track
through pass transistors. Each pass transistor forms a tristate output that can be independently
turned on or off.
As shown in fig.6.10 a programmable switch consists of a pass transistor controlled by a static
random access memory cell. If transistor between upper portion and lower portion is ON, these
two portions will be connected. There are six pass transistor and six different connections are
possible within a small block. Based on this theory Verilog-AMS code of each can be generated,
hence four small blocks can be cascaded to form a complete Switch Block.
A circuit diagram of a routing switch has been given below.
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Figure 6.11 : Programmable Routing Switch
This Switch Box contains four small blocks. Schematic diagram of this small block has been
shown below.
Figure 6.12 : A small block of Routing Switch .
Verilog-AMS code of a small block of a routing switch has been given below.
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Table. 6.3: Veriog-AMS code of a small block of Routable Switch Block.
Veriog-AMS code of a small block of Routable Switch Block.
module switch_block
(UP,DOWN,LEFT,RIGHT,UD,
UR,RD,LR,UL,LD);
input wire UD;
input wire UR;
input wire RD;
input wire LR;
input wire UL;
input wire LD;
input wire
UP,DOWN,LEFT,RIGHT;
assign DOWN= (UD==1)? UP:(UR==1)? RIGHT: (LD==1)? LEFT:1'bz;
assign LEFT= (UL==1)? UP: (LR==1)? RIGHT:1'bz;
assign RIGHT=(UR==1)? UP:1'bz;
endmodule
A testbench was generated for testing the accuracy of the circuit.
Table 6.4: Verilog-AMS code of the test bench of a small block of Routable Switch Block.
Verilog-AMS code of the test bench of a small block of Routable Switch Block.
`include "disciplines.vams"
`include "constants.vams"
`timescale 1ns / 10ps
module top;
reg UD,UR,RD,LR,UL,LD;
wire UP,DOWN,LEFT,RIGHT;
reg aa,bb,cc;
assign UP=(UD|UL|UR) ? aa : 1'bz;
assign LEFT = (UD) ? bb : 1'bz;
assign RIGHT = (RD|LR) ?cc: 1'bz;
initial
begin
UD=1'b0; UR=1'b0; RD=1'b0; LR=1'b0; UL=1'b0; LD=1'b0; aa=1'b0; bb=1'b0; cc=1'b0;
end
always # 20 UD=~UD;
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always # 40 UR=~UR;
always # 80 RD=~RD;
always # 160 LR=~LR;
always # 320 UL=~UL;
always # 640 LD=~LD;
always # 1280 aa=~aa ;
always # 2560 bb=~bb ;
always # 5120 cc=~cc ;
switch_block
IC(.UP(UP),.DOWN(DOWN),.LEFT(LEFT),.RIGHT(RIGHT),.UD(UD),.UR(UR),.RD(RD),.L
R(LR),.UL(UL),.LD(LD));
endmodule
In figure. 6.13 Waveform of a small block of Routing Switch Routing Switches has been shown.
Figure 6.13: Waveform of a small block of Routing Switch using Verilog-AMS .
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Figure 6.14: Layout of a small block of Routing Switch using Microwind.
This module can be used for generating Verilog-AMS code of a complete routing switch block
(shown in figure 6.9).
Table 6.5: Verilog-AMS code of a Complete Routable Switch Block
Verilog-AMS code of a Complete Routable Switch Block
`include "disciplines.vams"
`include "constants.vams"
`timescale 1ns / 10ps
module comple_switch_block (UP1,DOWN1,LEFT1,RIGHT1,UD1,UR1,RD1,LR1,UL1,LD1,
UP2,DOWN2,LEFT2,RIGHT2,UD2,UR2,RD2,LR2,UL2,LD2,
UP3,DOWN3,LEFT3,RIGHT3,UD3,UR3,RD3,LR3,UL3,LD3,
UP4,DOWN4,LEFT4,RIGHT4,UD4,UR4,RD4,LR4,UL4,LD4 );
input wire
input wire
input wire
input wire
input wire
input wire
UD1, UD2, UD3, UD4;
UR1, UR2, UR3, UR4;
RD1, RD2, RD3, RD4;
LR1, LR2, LR3, LR4;
UL1, UL2, UL3, UL4;
LD1, LD2, LD3, LD4;
inout wire UP1, DOWN1, LEFT1, RIGHT1;
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inout wire UP2, DOWN2, LEFT2, RIGHT2;
inout wire UP3, DOWN3, LEFT3, RIGHT3;
inout wire UP4, DOWN4, LEFT4, RIGHT4;
switch_block SB1(UP1,DOWN1,LEFT1,RIGHT1,UD1,UR1,RD1,LR1,UL1,LD1);
switch_block SB2(UP2,DOWN2,LEFT2,RIGHT2,UD2,UR2,RD2,LR2,UL2,LD2);
switch_block SB3(UP3,DOWN3,LEFT3,RIGHT3,UD3,UR3,RD3,LR3,UL3,LD3);
switch_block SB4(UP4,DOWN4,LEFT4,RIGHT4,UD4,UR4,RD4,LR4,UL4,LD4);
endmodule
These Routing Switches are mounted together for forming a programmable interconnection
architecture. In Figure 6.13 combination of four Routing Switches has been shown.
Figure 6.15: Combination of four Routing Switches.
Schematic diagram of a connection block has given below. It consists of some pass transistor and
MUX, Pass transistors are user for connecting horizontal and vertical lines and MUX’ s select
which wire will be connected as a input of CLB. Pass transistors are connected with the wires
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connected to IO block or which are the output of CLB block. On the other hand MUX’s are
connected with the input wires of CLBs.
Figure 6.16 : A Routing Connection Block.
Verilog-AMS code of a connection block is given below.
Table 6.6: Veriog-AMS code of a connection block.
Veriog-AMS code of a connection block
`include "disciplines.vams"
`include "constants.vams"
`timescale 1ns / 10ps
module connection_block(A,B,C,D,
Sel_A,Sel_B,Sel_C,Sel_D,Mux0,Mux1,I,O
);
input wire Sel_A,Sel_B,Sel_C,Sel_D,I,Mux0,Mux1;
inout wire A,B,C,D;
output wire O;
assign A=(Sel_A)?I :1'bz;
assign B=(Sel_B)?I :1'bz;
assign C=(Sel_C)?I :1'bz;
assign D=(Sel_D)?I :1'bz;
assign O= ((~Mux0) & (~Mux1) ) ? A:
((~Mux0) & Mux1 ) ? B:
( Mux0 & (~Mux1) ) ? C:
( Mux0 & Mux1 ) ? D:1'bz;
Endmodule
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Verilog-AMS code of the testbench of a connection block is shown below.
Table 6.7: Verilog-AMS code of the testbench of a connection Block.
Verilog-AMS code of the testbench of a connection Block
`include "disciplines.vams"
`include "constants.vams"
`timescale 1ns / 10ps
module top;
reg Sel_A,Sel_B,Sel_C,Sel_D,Mux0,Mux1,I;
wire O;
wire A,B,C,D;
reg aa,bb,cc,dd;
assign A=((~Mux0) & (~Mux1) ) ? aa : 1'bz;
assign B=((~Mux0) & Mux1 ) ? bb : 1'bz;
assign C=( Mux0 & (~Mux1) ) ? cc : 1'bz;
assign D=( Mux0 & Mux1 ) ? dd : 1'bz;
initial
begin
Sel_A=1'b0;Sel_B=1'b0;Sel_C=1'b0;Sel_D=1'b0;
Mux0=1'b0;Mux1=1'b0;
I=1'b0; aa=1'b0; bb=1'b0; cc=1'b0; dd=1'b0;
end
always #10 Sel_A=~Sel_A;
always #20 Sel_B=~Sel_B;
always #40 Sel_C=~Sel_C;
always #80 Sel_D=~Sel_D;
always #160 I=~I;
always #20 Mux0=~Mux0;
always #40 Mux1=~Mux1;
always #320 aa=~aa;
always #640 bb=~bb;
always #480 cc=~cc;
always #550 dd=~dd;
connection_block IC (.A(A), .B(B), .C(C), .D(D), .Sel_A(Sel_A), .Sel_B(Sel_B), .Sel_C(Sel_C),
.Sel_D(Sel_D), .Mux0(Mux0), .Mux1(Mux1), .I(I),. O(O) );
endmodule
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The following figures show the wave form and layout of a connection block .
Figure 6.17: Waveform of a small block of a connection block using Verilog-AMS.
Figure 6.18: Layout of a connection block.
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In figure. 6.17 implementation of a logic function (f = (x1x6’ + x2x7)(x3 + x4x5) ) using CLB and
programmable interconnection has been shown.[24]
Figure 6.19. Implementation of a logic function using CLB and programmable interconnection.
6.4. Summary
The basic components of a typical FPGA are configurable logic block, programmed
interconnection and programmable IO block whose allows an FPGA to implement any user
defined digital circuit. All of these components are digital in nature. In this chapter we have
modeled a CLB and some components of Programmable Interconnection using Verilog-AMS .
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Chapter 7
Mixed Signal Modeling of a Simple FPGA Architecture
7.1. Introduction
In previous chapters, some digital and analog components were designed and simulated of an
FPGA. By integrating LUT, ADC, DAC and DLL, we were constructed a simple FPGA.
7.2. Simple FPGA Model
Two ADC were used to take continuous signal from analog source. Both of these signals were
passed through two LUT’s for adding those signals. Finally, outputs of those two LUT’s were
used as a inputs of a DAC. For synchronizing clocks of the LUT’s, a DLL was employed. As
both of LUT’s performed adding operation, data inputs of those LUT’s were 0 1 1 0(output of a
half adder). Model of the simple FPGA(excluding DLL) is shown below-
Figure 7.1:
Model of a Simple FPGA
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7.2.1 Verilog-AMS code of simple FPGA using LUT, ADC and DAC
Verilog-AMS code of a simple FPGA using the modules of ‘ADC’, ‘DAC’ and ‘LUT’ is given
belowTable 7.1: Veriog-AMS code of a connection block
Veriog-AMS code of a connection block
`timescale 1ns / 1ps
`include "disciplines.vams"
module FPGA(fpgaout,X,Y,Z,reset,clk,data,ff_sel);
input X,Y,Z;
output fpgaout;
input logic reset,clk,data,ff_sel;
electrical X,Y,Z,fpgaout;
logic [0:2]A;
logic [0:2]B;
logic [0:2]C;
logic [0:2]D;
adc adc1(.out(A), .in(X), .clk(clk)); // ‘adc’ is the module of Analog to digital converter.
adc adc2(.out(B), .in(Y), .clk(clk));
adc adc3(.out(B), .in(Z), .clk(clk));
lut LUT1(.clb_out(D[0]),.ff_sel(ff_sel),.areset(reset),.clk(clk),.in_put(A),.data_in(data));
// LUT is the module of a Look Up table.
lut LUT2(.clb_out(D[1]),.ff_sel(ff_sel),.areset(reset),.clk(clk),.in_put(A),.data_in(data));
lut LUT3(.clb_out(D[2]),.ff_sel(ff_sel),.areset(reset),.clk(clk),.in_put(A),.data_in(data));
dac dac1(.out(fpgaout), .in(D), .clk(clk)); // dac is the module of a digital to analog converter.
Endmodule
.
7.3. Summary
As, DSCH does not support analog signal simulation, we were unable to evaluate the
performance of our simple FPGA. Alternatively, we tried to simulate the whole FPGA in
SMASH. But, we also could not do that because SMASH cannot simulate more than 15 signals
at a time. Thus, future work of our thesis would be to accomplish the above mentioned task as
effectively as possible with analog mixed signal simulator that does not have limitations.
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Chapter 8
Discussions and Conclusions
8.1. Discussions
An analog-mixed model simulator has great capacity to deal with both continuous and discrete
signals. Even though FPGAs are digital circuits, they have clock management unit (involving
PLL’s or DLL’s) and in some cases ADC and DAC- all of which are analog components. That’s
why a mixed signal language such as Verilog-AMS can be used to model such circuit. In this
thesis, we have designed some digital and analog components of an FPGA such as, Phase
Locked Loop (PLL), Analog-To-Digital Converter (ADC), Digital-To-Analog Converter (DAC),
Configurable Logic Block (CLB) and Programmable Interconnection with Verilog-AMS using
Dolphin Integration - SMASH and designed schematic diagram of a simple FPGA using DSCH.
We planned to use Virtuoso Layout Editor from Cadence for creating physical layout of a simple
FPGA including some digital and analog components. But, Cadence tools those we have in our
institute do not support Verilog-AMS. For that, we could not use Virtuoso Layout Editor for
generating physical layout of this analog mixed signal circuit .We simulated some digital and
analog components of this circuit using SMASH. As, we used a free version of SMASH that
does not support more than 15 signals at a time, simulation of a big circuit was not possible. For
this reason, we could not simulate the clock management unit. As a result, integration of the
whole FPGA was not done using SMASH.
8.2. Suggestion for future Work
We modeled most common FPGA components (programmable logic blocks, interconnect, ADC,
DAC, clock management unit) in Verilog-AMS and also in schematic. Physical layouts were
generated for some of these components. In future, all the components can be integrated to
model the whole FPGA and then full layout could be generated if relevant EDA software is
available.
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8.3. Conclusions
We successfully modeled and simulated ADC, DAC and PLL in Verilog-AMS (mixed signal
version of Verilog). We also successfully modeled and simulated programmable logic block,
Programmable Interconnect using both schematic entry and Verilog. Physical layouts were also
generated for those components. In future, all the components could be integrated to model the
whole FPGA and then full layout could be generated if relevant EDA software is available.
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REFERENCES
[1] Kenneth S.Kundert and Olaf Zinke, The Designer’s Guide To Verilog-AMS,1st edition, New
York, Boston ,Dordrecht, London, Moscow, Kluer Publishers,2004
[2] SorinA.Huss, Model Engineering in Mixed Signal Circuit Design, New York, Boston,
Dordrecht, London, Moscow, Kluer Publishers, 2001
[3] Chip Design Tools Technologies and Methodologies [Online] [Accessed: June 19, 2015]
Available: http://chipdesignmag.com/display.php?articleId=105
[4] Design and Reuse [online] [Accessed: June 19, 2015] Available: http://www.designreuse.com/articles/25954/ams-rf-system-verification-above-transistor-level.html
[5] Verilog-AMS Language Reference Manual, version 2.1, Accelera, January 20, 2003
[6] MylesoFril, Frequency Domain Adaptive Filtering, BE project report, National University of
Ireland, April 2005
[7] “Spartan 3 FPGA family Data Sheet” DS099 October 29, 2012, Xilinx
[8] EE Times. [Online] [Accessed: July 13, 2015] Available:
http://www.eetimes.com/story/OEG20010622S0091
[9] Wai- Kai Chen, The VLSI Hand Book,2nd edition, Boca Raton London New York, CRC
Press,2007
[10] COTS Journal [online] [Accessed: July 13, 2015] Available:
http://www.cotsjournalonline.com/articles/view/100247
[11] Safari [Online] [Accessed: July 13, 2015] Available:
https://www.safaribooksonline.com/library/view/field-programmable-gatearrays/9780471556657/s69-69.html
[12] EE Times. [Online] [Accessed: July 14, 2015] Available:
http://www.eetimes.com/document.asp?doc_id=1213080
[13] Source Tech 411 [Online] [Accessed: July 14, 2015] Available:
http://sourcetech411.com/2013/04/top-fpga-companies-for-2013/
[14] Xilinx [Online] [Accessed: July 13, 2015] Available:
http://www.xilinx.com/products/technology/analog-mixed-signal.html
[15] Xilinx [Online] [Accessed: July 13, 2015] Available:
http://www.xilinx.com/products/technology/ultrascale.html
[16] Accellera [Online] [Accessed: July 14, 2015] Available:
http://accellera.org/activities/working-groups/verilog-ams/about
© Faculty of Engineering, American International University-Bangladesh (AIUB)
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[17] Microsemi [Online] [Accessed: July 14,2015] Available:
http://www.microsemi.com/products/fpga-soc/fpgas
[18] Philip H.W. Leong“Recent Trends in FPGA Architecturesand Applications” in 2008 IEEE
DOI 10.1109/DELTA.2008.14
[19].Stephen
D.
Brown,Robert
J.
Francis,JonathanRose,Zvonko
G.
Vranesic
"Field-
Programmable Gate Arrays." Springer Science+Business Media, LLC, chapter 3,4,5ed 1992,
ISBN 978-1-4615-3572-0.
[20].Tree-based Heterogeneous FPGA Architecture Application Specific Exploration and
Optimization
[21].Russell G. Tessier,"Fast Place and Route Approaches for FPGAs". S.M., Massachusetts
Institute of Technology, 1992 , Department of Electrical Engineering and Computer Science.
[22] Thomas L. Floyd, Digital Fundamentals, 11th Ed, ISBN-13: 978-0132737968
[23] Chia-Lin Chang, "A Wide-Range All-Digital Delay-Locked
Loop in 65nm CMOS technology", M. Eng. thesis, National Chung Cheng University, Taiwan,
26-29 April 2010
[24]Pierre Maillard,
"RADIATION-HARDENED-BY-DESIGN (RHBD) DELAY LOCKED LOOPS (DLLs):
SINGLE EVENT TRANSIENT ANALYSIS, SIMULATION, AND HARDENING",
M.Science.thesis, Graduate School of Vanderbilt University, Nashville, Tennessee, May, 2010
[25]Nivedita, UshabenKeshwala,
"System Level Design of Timing and Frequency Control Circuit", IOSR Journal of VLSI and
Signal Processing (IOSR-JVSP),
Volume 4, Issue 4, Ver. II (Jul-Aug. 2014), PP 40-48
e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197
[26]. Clive “Max” Maxfield, “FPGAsWorld Class Designs” Newnes publications, ISBN: 978-185617-621-7, 2009.
[27]. Clive “Max” Maxfield, “FPGAs: Instant Access”, Newnes publications, 2008.
[28]. (2011), “Spartan-3 Generation FPGA User Guide” UG331 (v1.8) June 13, 2011, Available:
http://www.xilinx.com/
[28]. FPGA Routing Architecture [Online] [Accessed: July 14,2015] Available:
http://islab.soe.uoguelph.ca .
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