Download Schmitt Trigger

Schmitt Trigger
LAB:- CEII (SEM V EXTC)
Aim and Apparatus
Aim : Design an Inverting Schmitt Trigger for UTP = 3V and LTP = -1.5V. Assume Vcc = +15V
APARATUS REQUIRED: CRO, function generator, breadboard, OP-Amp 741, Resistors, Diode and Connecting
wires.
LAB:- CEII (SEM V EXTC)
Inverting Schmitt trigger
Fig 1. Inverting Schmitt Trigger
/
Reference:- http://www.circuitstoday.com/schmitt-trigger-using-op-amp
LAB:- CEII (SEM V EXTC)
Fig 2. Input and Output Waveforms
Theory
• Upper Threshold Voltage, VUT = +Vsat (Rdiv1/[Rdiv1+Rdiv2])
• When Vout = -Vsat, the voltage across Rdiv1 is called Lower Threshold Voltage (VLT). The input voltage, Vin
must be slightly more negaitive than VLT inorder to cause the output Vo to switch from -Vsat to +Vsat. When
the input voltage is less than VLT, the output voltage Vout is at -Vsat.
• Lower Threshold Voltage, VLT = -Vsat (Rdiv1/[Rdiv1+Rdiv2])
• If the value of VUT and VLT are higher than the input noise voltage, the positive feedback will eliminate the false
output transitions. With the help of positive feedback and its regenerative behavior, the output voltage will
switch fast between the positive and negative saturation voltages.
Reference:- http://www.circuitstoday.com/schmitt-trigger-using-op-amp
Hysterisis Curve
LAB:- CEII (SEM V EXTC)
Theory
• Vhysteresis = VUT – VLT
• Subsituting the values of VUT and VLT from the above equations:
• Vhysteresis = +Vsat (Rdiv1/Rdiv1+Rdiv2) – {-Vsat (Rdiv1/Rdiv1+Rdiv2)}
• Vhysteresis = (Rdiv1/Rdiv1+Rdiv2) {+Vsat – (-Vsat)}
LAB:- CEII (SEM V EXTC)
For Different UTP and LTP Levels
• When the output is positive ,D1 gets forward
bias and VUT is the drop across R2. When the
output is negative D1 is reverse biased and the
only input current flows through R2. Hence VLT is
almost zero.
VUT = ([Vsat -VF] R2)/ (R1+R2)
VLT = ([Vsat -VF] R2)/ (R2+R3)
• Where VF is the forward voltage drop of D1.
Reference: For Diagram Protues Software is
used.
LAB:- CEII (SEM V EXTC)
Design Problem :
• Design the Schmitt Trigger for different UTP and LTP Levels
UTP=3V and LTP= 1.5V
Solution:
𝑉 − 𝑉𝑜 𝑅2
𝑈𝑇𝑃 =
𝑅1 + 𝑅2
Assume R2=10KΩ; R1=?
𝑉 − 𝑉𝑓 𝑅2
𝐿𝑇𝑃 =
𝑅2 + 𝑅3
R2=?
LAB:- CEII (SEM V EXTC)
• PROCEDURE:
1.
Design the given problem and connect the circuit.
2.
Apply the given input voltage.
3.
Observe the output on the Cathode ray Oscilloscope.
4.
Observe the hysteresis curve
• OBSERVATION TABLE:
Vcc= 15V
Assume R2=10KΩ
Parameters
Calculated
VUT
VLT
+Vsat
-Vsat
VH
LAB:- CEII (SEM V EXTC)
Observed
References
•
Internet and Books by Sergio Franco and Ramakant Gaykwad
LAB:- CEII (SEM V EXTC)